Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Interpretation
The claims include terms such as “...determining a parameterized diode value...” and “parameterized diode”, see [claim 1 lines 3-4]. The following definitions of a “cell”, a “cell library”, a “cell instance”, and a “cell type” represent how a person having skill in the art may interpret a “parameterized diode” as a “diode cell”:
cell ... (9) A primitive in an integrated circuit library. Primitive means the timing properties of the cell are directly described in the DPCM without reference back to the application for the internal structure of the cell. This primitiveness typically is a result of the characterization of that cell by the semiconductor vendor, but it may instead be a result of the construction of a timing model for a subcircuit by the application, and its loading into the DPCM at run-time. For PDEF, cell refers to a logical instance, and a library primitive is called a gate. The term cell can arise in the context of the abstraction of a type of cell available in the library or in the concrete selection and placement of a cell in the final design. If the context is not clear, the terms cell type and cell instance (or just instance) shall be used. See also: cell type; instance.
cell instance A particular, concrete appearance of a cell in the fully expanded (flattened, unfolded, elaborated) design description of an integrated circuit; also referred to elsewhere as an “occurrence.” An instance is a “leaf” of the unfolded design hierarchy. In Physical Design Exchange Format (PDEF), this is a physical cluster or a logical cell. See also: cell; cell type; cluster; hierarchical instance.
cell library A collection of cells used to design and lay out application-specific integrated circuits in accordance with the functional requirements of particular end users.
cell type (2) Name used to identify a particular cell in the library.
(Breitfelder, Kim, and Don Messina. "IEEE 100: the authoritative dictionary of IEEE standards terms." Standards Information Network IEEE Press. v879 (2000): 1249, pages 153-154)
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6, 12, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “less than full sized” in claims 6, 12, and 18 is a relative term which renders the claim indefinite. The term “full sized” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Because “full sized” is indefinite, there is no way to determine the parameterized diode value, which must be “less than full sized”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
With respect to claims 13-19, the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because a computer readable medium may include signals and/or data per se under broadest reasonable interpretation, and signals per se and data per se are not one of the statutory categories (see MPEP 2106.03).
Examiner has taken note of the following excerpt from the specification:
A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
(Specification [0054] lines 12-15).
The claim language is directed to a “computer readable medium” (claim 13 line 3) and a “storage medium”, (claim 19 line 2), but never a “computer readable storage medium” (Specification [0054] lines 12-15). Because the terminology is different, the carve-out in the specification does not apply.
To overcome this rejection, Applicant may amend to the specific language of the specification or simply amend to include “non-transitory” in the CRM language.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over "Building OpenLANE: A 130nm OpenROAD-based Tapeout-Proven Flow" (2020-Shalan) in view of “Impact of Plasma Charging Damage and Diode Protection on Scaled Thin Oxide” (1993-Shin)
With respect to claim 1, Shalan teaches A method for providing a parameterized IP algorithm for power reduction across a chip hierarchy, the method comprising (see FIG. 2, [page 3]; where designer is optimizing for power, "(e.g., minimum area, delay, or power)", [page 3 col 1 paragraph 1 lines 10-11]; example chip hierarchy is shown in FIG. 1, [page 2]):
for each input pin at a chip hierarchy level (in FIG. 2, this is step labeled "fake ant. diodes insertion script", [page 3]; where "antenna diode cell next to every cell input pin", [page 4 col 1 paragraph 2 line 3]; except the diode cell in this case is a “dummy”, [page 4 col 1 paragraph 2 line 1]), determining a parameterized diode value only for an indication of an antenna violation (In FIG. 2, this is the step labeled "Fake ant. diodes swapping script", [page 3]; the value refers to one of the values of the real diode defined in the standard cell library, which is used to calculate aggregate values during the exploration step "(e.g., minimum area, delay, or power)", [page 3 col 1 paragraph 1 lines 10-11]; Once the detailed routing is performed we run the antenna rule checker provided by the Magic [10] layout editing tool to check for antenna violations. Based on the reported violations, we replace some of the dummy antenna diode cells by real antenna diode cells, [page 4 col 1 paragraph 2 lines 13-18]); and enabling the parameterized diode with the parameterized diode value (modifying the netlist: "Steps like CTS, DFT and antenna diode insertion modify the mapped netlist produced by the synthesis step", [page 4 col 1 paragraph 3 lines 1-2]).
Shalan does not teach wherein a parameterized diode is scaled to protect a gate.
However, Shin teaches wherein a parameterized diode is scaled to protect a gate (This work presents a quantitative model to predict the impact of plasma charging and protection diodes on future scaled thin oxide, [page 467 paragraph 1 lines 3-6]; where the model is shown in FIGS. 8-12, [page 470]; with the following summation: “Therefore the protection diode is effective only when the antenna to diode area ratio is less than 23 or about 10 times less than this value if the diode is shielded by metal from plasma illumination”, [page 468 col 1 paragraph 4 lines 5-8]; meaning as the antenna size is scaled down, the diode size is also be scaled down so the ratio requirements are still met).
It would have been obvious to one skilled in the art before the effective filing date to combine Shalan with Shin because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Shalan discloses a system and method that teaches all of the claimed features except for sizing the diode. Shallan first paragraph is about Moore’s law and how devices are expected to scale to smaller and smaller sizes, where the scaling has led to development of IP libraries, which is the motivation for the invention, (see Shalan [Abstract] and [page 1 col 1 paragraph 1 line 1]-[page 1 col 2 paragraph 1 line 7]). Shin teaches “This work presents a quantitative model to predict the impact of plasma charging and protection diodes on future scaled thin oxide”, (Shin [page 467 paragraph 1 lines 3-6]). The model relates the antenna area to charging current as shown in FIG. 8, (Shin [page 470]) and reverse leakage current of the protection diode shown in FIG. 12 (Shin [page 470]). Essentially, a person having skill in the art can parameterize the design the of the protective diodes based on the current derived using eq’s. (1) and (2), (Shin [page 467]), and a ratio between the antenna area and the diode area, (Shin [page 468 col 1 paragraph 4 lines 5-8]). A person having skill in the art would have a reasonable expectation of successfully calculating the required diode area, which shrinks relative to the antenna area, in the system and method of Shallan by modifying Shallan with the model of Shin. Therefore, it would have been obvious to combine Shallan with Shin to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 2, Shalan teaches all of the limitations of claim 1, as noted above. Shalan further teaches placing a placeholder parameterized diode for each input pin (in FIG. 2, this is step labeled "fake ant. diodes insertion script", [page 3]; where "antenna diode cell next to every cell input pin", [page 4 col 1 paragraph 2 line 3]; except the diode cell in this case is a “dummy”, [page 4 col 1 paragraph 2 line 1]; note this is at the cell level of the chip layout).
With respect to claim 3, Shalan teaches all of the limitations of claim 1, as noted above. Shalan further teaches for each IP, converting the IP into a parameterized IP (extracting IP blocks as “black boxes”: “These cells may also be extracted as "black-box" entries for the purpose of simplifying the LVS by ignoring internal components of library IP that has already been validated”, [page 4 col 2 paragraph 2 lines 9-12]).
With respect to claim 4, Shalan teaches all of the limitations of claim 1, as noted above. Shalan further teaches upon a determination of no antenna violation, disabling the parameterized diode (in FIG. 2, the process is repeated multiple times in order to fully perform design exploration as shown in FIG. 3, [page 3]; each iteration has “fake ant. diode insertion” and “fake ant. diodes swapping” as shown, which results in different violations and different swapping for the same design RTL. Disabling occurs when a pin that had a real diode in the first iteration is replaced with one that is a dummy in a future iteration).
With respect to claim 5, Shalan teaches all of the limitations of claim 1, as noted above. Shalan further teaches wherein the determination is made for each input pin at an IP level (in FIG. 2, includes both steps "fake ant. diodes insertion script" and "Fake ant. diodes swapping script", [page 3]; where "antenna diode cell next to every cell input pin", [page 4 col 1 paragraph 2 line 3]; except the diode cell in this case is a “dummy”, [page 4 col 1 paragraph 2 line 1]; note this is at the cell level of the chip layout, “cell” specifically includes cells in IP standard cell libraries, see [Abstract] line 4 and line 9; determining the value refers to one of the values of the real diode defined in the standard cell library, which is used to calculate aggregate values during the exploration step "(e.g., minimum area, delay, or power)", [page 3 col 1 paragraph 1 lines 10-11]; Once the detailed routing is performed we run the antenna rule checker provided by the Magic [10] layout editing tool to check for antenna violations. Based on the reported violations, we replace some of the dummy antenna diode cells by real antenna diode cells, [page 4 col 1 paragraph 2 lines 13-18]).
With respect to claim 6, Shalan teaches all of the limitations of claim 1, as noted above. Shalan does not teach wherein the parameterized diode value is scaled to be less than full sized.
However, Shin teaches wherein the parameterized diode value is scaled to be less than full sized (This work presents a quantitative model to predict the impact of plasma charging and protection diodes on future scaled thin oxide, [page 467 paragraph 1 lines 3-6]; where the model is shown in FIGS. 8-12, [page 470]; with the following summation: “Therefore the protection diode is effective only when the antenna to diode area ratio is less than 23 or about 10 times less than this value if the diode is shielded by metal from plasma illumination”, [page 468 col 1 paragraph 4 lines 5-8]; meaning as the antenna size is scaled down, the diode size is also be scaled down so the ratio requirements are still met).
It would have been obvious to one skilled in the art before the effective filing date to combine Shalan with Shin because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Shalan discloses a system and method that teaches all of the claimed features except for sizing the diode. Shallan first paragraph is about Moore’s law and how devices are expected to scale to smaller and smaller sizes, where the scaling has led to development of IP libraries, which is the motivation for the invention, (see Shalan [Abstract] and [page 1 col 1 paragraph 1 line 1]-[page 1 col 2 paragraph 1 line 7]). Shin teaches “This work presents a quantitative model to predict the impact of plasma charging and protection diodes on future scaled thin oxide”, (Shin [page 467 paragraph 1 lines 3-6]). The model relates the antenna area to charging current as shown in FIG. 8, (Shin [page 470]) and reverse leakage current of the protection diode shown in FIG. 12 (Shin [page 470]). Essentially, a person having skill in the art can parameterize the design the of the protective diodes based on the current derived using eq’s. (1) and (2), (Shin [page 467]), and a ratio between the antenna area and the diode area, (Shin [page 468 col 1 paragraph 4 lines 5-8]). A person having skill in the art would have a reasonable expectation of successfully calculating the required diode area, which shrinks relative to the antenna area, in the system and method of Shallan by modifying Shallan with the model of Shin. Therefore, it would have been obvious to combine Shallan with Shin to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 7, Shalan teaches An apparatus for providing a parameterized IP algorithm for power reduction across a chip hierarchy (see FIG. 2, [page 3]; where designer is optimizing for power, "(e.g., minimum area, delay, or power)", [page 3 col 1 paragraph 1 lines 10-11]; example chip hierarchy is shown in FIG. 1, [page 2]), the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of (“OpenLane”, [Title], which is a flow using “open-source tools, [Abstract] line 2, is referencing open-source software, which is a software running on a computer having a processor and memory; Table 2 shows all of the software tools used, [page 2] and FIG. 2 shows how those tools are integrated, [page 2]).
Regarding the rest of claim 7, incorporating the rejection of claim 1, claim 7 is rejected for a substantially similar rationale.
With respect to claim 8, incorporating the rejection of claim 7 and claim 2, claim 8 is rejected for a substantially similar rationale.
With respect to claim 9, incorporating the rejection of claim 7 and claim 3, claim 9 is rejected for a substantially similar rationale.
With respect to claim 10, incorporating the rejection of claim 7 and claim 4, claim 10 is rejected for a substantially similar rationale.
With respect to claim 11, incorporating the rejection of claim 7 and claim 5, claim 1 is rejected for a substantially similar rationale.
With respect to claim 12, incorporating the rejection of claim 7 and claim 6, claim 12 is rejected for a substantially similar rationale.
With respect to claim 13, Shalan teaches A computer program product for providing a parameterized IP algorithm for power reduction across a chip hierarchy (product is the flow in FIG. 2, [page 3]; where designer is optimizing for power, "(e.g., minimum area, delay, or power)", [page 3 col 1 paragraph 1 lines 10-11]; example chip hierarchy is shown in FIG. 1, [page 2]), the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of (“OpenLane”, [Title], which is a flow using “open-source tools, [Abstract] line 2, is referencing open-source software, which is a software running on a computer having a processor and memory; Table 2 shows all of the software tools used, [page 2] and FIG. 2 shows how those tools are integrated, [page 2]).
Regarding the rest of claim 13, incorporating the rejection of claim 1, claim 13 is rejected for a substantially similar rationale.
With respect to claim 14, incorporating the rejection of claim 13 and claim 2, claim 14 is rejected for a substantially similar rationale.
With respect to claim 15, incorporating the rejection of claim 13 and claim 3, claim 14 is rejected for a substantially similar rationale.
With respect to claim 16, incorporating the rejection of claim 13 and claim 4, claim 16 is rejected for a substantially similar rationale.
With respect to claim 17, incorporating the rejection of claim 13 and claim 5, claim 17 is rejected for a substantially similar rationale.
With respect to claim 18, incorporating the rejection of claim 13 and claim 6, claim 118 is rejected for a substantially similar rationale.
With respect to claim 19, Shalan teaches all of the limitations of claim 13, as noted above. Shalan further teaches wherein the computer readable medium comprises a storage medium (in FIG. 2, the cylinder shaped box storing “sky130 PDK” is a storage medium, [page 3]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 6862723 B1 (Wang) - A method to route a metal line in the layout of an integrated circuit device comprising: providing a layout for an integrated circuit device comprising an array of placed standard cells; placing polygons of a contact/via layer for coupling said standard cells; routing a line in a metal layer intersection said polygons; calculating an antenna effect value for said line using parameters previously determined from the layout of each said standard cell wherein said parameters comprise gate area, diode area, metal area, and contact/via area coupled to said line wherein said gate area, said diode area, said metal area, and said contact/via area are segregated by metal level; and repeating said steps of routing and calculating if said antenna effect value exceeds a specified value, [claim 1].
US 7,302,663 B1 (Gan) - In one particular embodiment of the invention, the antenna diodes are instantiated for every primary input of the embedded block design, [col 4 ln 62-64]; Even though each primary input of the embedded block is coupled to an antenna diode, additional antenna rule violations may exist. For example, additional antenna diodes may be required if the metal connected to an affected transistor gate is long enough to build up more charge than a single diode can dissipate, [col 5 ln 21-26].
“Radiation Hard ASICs and Opto-Electronics for the ATLAS Experiment” (2013-Smith) - Through employing the flow described in the next section, and illustrated in Figure 5.1, we were able to successfully reuse many legacy cells by performing a vertical port from the 0.25 µm to the 0.13 µm process, [page 92 paragraph 1 lines 10-13]; An additional complication was discovered in preparing the DAC IP for use in the VDC12. In the final stages of the DRC process, checks are performed to test the layout for susceptibility to the antenna effect, or plasma induced gate oxide damage [89]. Surprisingly, the DAC had several such antenna rule violations that required correction. To complete these corrections, the original layout had to be further modified in order to allow room for the addition of n-well and gate tie down diodes, [page 102 paragraph 2].
“Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion” (2000-Chen) - This paper describes three ways to fix antenna problems: (1) diode dropping, (2) jumper insertion, and (3) diode dropping with extension wires. Basic principles of these methods are compared and results are presented. Diode structures, SPIC simulation, and diode slicing are also discussed in this paper, [Abstract].
“CMOS Scaling for High Performance and Low Power-The Next Ten Years” (1995-Davari) – The basic idea of scaling, shown in Fig. 1, is to reduce the dimensions of the MOS transistors and the wires connecting them in integrated circuits. Thus the arrangement on the right is scaled down in size from that on the left by reducing all dimensions by a factor α. The MOS transistor works on the principle of modifying the electric field in the silicon substrate underneath the gate in such a way as to control the flow of current between the source and drain electrodes. Scaling achieves the same electric-field patterns in the smaller transistor by reducing the applied voltage along with all the key dimensions, including the thickness, t_ox of the insulating oxide layer between the gate and the silicon substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL MILLER whose telephone number is (408) 918-7548. The examiner can normally be reached on Monday-Friday from 11am to 5pm (PT). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang, can be reached at telephone number 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.M./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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