Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Application
In response to the Office action mailed on October 24th, 2025, Applicant has amended claims 1, 3-8, and 11-14. Claims 1 and 3-20 are currently pending. Claim 2 has been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 11, 12-14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani in view of Min et al., US Patent Pub. No. 20090097320A1, hereinafter “Min”, Lin et al., US Patent Pub. No. 20220028893A1, hereinafter “Lin,” Yasuda et al., US Patent Pub. No. 20080237688A1, hereinafter “Yasuda,” and Lai et al., US Patent Pub. No. 20090039416A1, hereinafter “Lai.”
Regarding claim 1, Sharangpani teaches a vertical non-volatile memory device (FIG. 15M) comprising:
a pillar (dielectric core #62);
a channel layer (vertical semiconductor channel #60) surrounding a side surface of the pillar (vertical semiconductor channel #60 surrounding a side surface of the dielectric core #62 which is a pillar);
a charge tunneling layer (charge tunnel dielectric layer #56) surrounding a side surface of the channel layer (charge tunnel dielectric layer #56 surrounding a side surface of the vertical semiconductor channel #60 which is a channel layer);
a charge trap layer (charge storage layer #54) surrounding a side surface of the charge tunneling layer (charge storage layer #54 surrounding a side surface of the charge tunnel dielectric layer #56) and comprising an amorphous oxynitride (the charge storage layer #54 is silicon nitride in para [0107] and the tunneling dielectric layer #56 is of “silicon oxynitride” in para [0108] and both are dielectric material with lacking crystalline order);
a charge blocking layer (blocking dielectric layer #52) surrounding a side surface of the charge trap layer (blocking dielectric layer #52 surrounding a side surface of the charge storage layer #54); and
a plurality of separation layers (insulating layers #132) and a plurality of gate electrodes (sacrificial layers #142 which are later replaced with electrically conductive layer #146 which is a gate electrode in para [0151]) surrounding a side surface of the charge blocking layer (the insulating layers #132 and the electrically conductive layer #146 are surrounding the side surface of blocking dielectric layer #52) and alternately arranged along the side surface of the charge blocking layer (insulating layer #132 and electrically conductive layer #146 is an “alternating stack” in para [0161] and along the side surface of blocking dielectric layer #52).
Sharangpani does not explicitly teach wherein the charge trap layer includes AxByOzN (1-x-y-z) (A and B are different elements, and at least one of A or B is a metal element, O is oxygen, N is nitrogen, x≥0.3, 0<y≤0.1, z≥x).
However, Min teaches wherein the charge trap layer (blocking dielectric #28 in FIG. 3 & 4) includes AxByOzN (1-x-y-z) (A and B are different elements, and at least one of A or B is a metal element, O is oxygen, N is nitrogen) (block dielectric #28 in FIG. 3 & 4 and in para [0080] lists SiAlON, AlHfON, SiTaON where Si and Al or Al and Hf or Si and Ta are different metal elements with oxygen and nitrogen).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to consider providing a non-volatile memory with a charge trap layer by Sharangpani and include includes compositions such as AxByOzN as taught by Min. A person of ordinary skill in the art would know to implement an oxynitride compound to provide a deep-level trap state, enhanced memory retention, and improved thermal and chemical stability for reliable non-volatile memory operation. Thus, Min cures the deficiencies of Sharangpani.
Sharangpani and Min do not explicitly teach the stoichiometry x≥0.3, 0<y≤0.1, z≥x.
However, Lin teaches z≥x (hafnium zirconium oxide Hf1-xZrxO, hafnium erbium oxide Hf1-xErxO, hafnium lanthanum oxide Hf1-xLaxO, hafnium yttrium oxide Hf1-xYxO, hafnium gadolinium oxide Hf1-xGdxO where the subscript for oxygen is 1 representing “z” in the claim and the subscript for hafnium which is 1-x is less than 1 which is “x” in the claim with “z” which is 1 being greater than x in para [0024]). Moreover, Yasuda teaches a hafnium oxynitride film is expressed by (HfO2)y(Hf3N4)1-y, (0<y<1) where Hf has a subscript of 3 and 3 is greater than 0.3 which teaches the claim limitation x≥0.3. Lastly, Lai teaches “The Al-doped silicon oxide is the preferred material for top dielectric because Al-doped silicon oxide has a large barrier height (the barrier height is does not fall significantly with the increase of Al dopant) and can be tuned to have a suitable dielectric constant.. the preferred range is about 1 to 10 atomic % aluminum” which proves that the stoichiometry 0<y≤0.1 proves that a metal B such as Al as cited in Lai is a small fraction relative to the host material A and has a small dopant concentration that falls in the range of 0<y≤0.1 where 1-10% coresponds to 0.01-0.1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sharangpani, Min, Lin, Lai, and Yasuda to arrive at the claimed invention. Sharangpani teaches the use of blocking layers, separation layers, electrodes, and charge trap layers in non-volatile memory devices to enhance charge retention and device reliability. Min further discloses charge trapping materials that include oxynitride type compounds with elements A and B such as AlHfON, demonstrating that combining oxygen and nitrogen within the trap layer with two metallic elements improves the dielectric and charge trapping properties. Lin teaches z≥x. Moreover, Yasuda teaches a hafnium oxynitride film is expressed by (HfO2)y(Hf3N4)1-y, (0<y<1) where Hf has a subscript of 3 and 3 is greater than 0.3 which teaches the claim limitation x≥0.3, and Lai teaches 0<y≤0.1. Particularly, that element A and element B exist in proportions defined by 1-x and x, respectively, while oxygen has a subscript of 1, thereby indicating that the oxygen content is greater than that of element B. A person of ordinary skill in the art would have found it obvious to apply the composition relationships disclosed by Lin, Lai, and Yasuda to the oxynitride-type trapping materials of Min, since both references are directed toward optimizing dielectric and use of similar materials used in memory devices. Furthermore, composition limits such as element A being less than or equal to 0.3, element B being equal to or less than 0.1 but greater than 0, and oxygen being greater than element B, would have provided a routine parameter for adjusting the stoichiometry of the oxynitride compounds taught by Min. Thus, it would have been obvious to combine the structures features taught by Sharangpani with the oxynitride materials of Min and the compositional relationships of Lin, Lai, and Yasuda to achieve the claimed memory device with improved performance and stable charge trapping characteristics.
Regarding claim 3, Sharangpani in view of Min and further in view of Lin, Lai, and Yasuda teach the vertical non-volatile memory device of claim 1, wherein the A element is any one of aluminum (Al), hafnium (Hf), zirconium (Zr), and silicon (Si) (Min, blocking dielectric #28 in FIG. 3 & 4 and in para [0080] lists SiAlON, AlHfON, SiTaON, and ZrSiON include any of silicon, aluminum, hafnium, and zirconium).
Regarding claim 11, Sharangpani in view of Min and further in view of Lin, Lai, and Yasuda teach the vertical non-volatile memory device of claim 1, wherein a density of the A element changes in a thickness direction of the charge trap layer (Min, density and trapping energy of charge trapping material differs in para [0038]. Any apparent variation in the density of the charge trapping material is considered equivalent to a variation in the density of the charge-trapping elements along the thickness direction, as both result in the same local modulation of charge storage within the layer).
Regarding claim 12, Sharangpani in view of Min and further in view of Lin, Lai, and Yasuda teach the vertical non-volatile memory device of claim 11, wherein the charge trap layer (charge trapping zones) includes a region in which a density of the B element (Min, second population density) is greater than or equal to the density of the A element (Min, first population density) in the thickness direction of the charge trap layer (Min, a first population density of a charge-trapping zone and a second population density of a charge-trapping zone differing by 10% shows the same local charge-trapping behavior is equivalent to the density of the element B being greater than or equal to that of element A along the thickness direction of the charge trapping layer).
Regarding claim 13, Sharangpani in view of Min and further in view of Lin, Lai, and Yasuda teach the vertical non-volatile memory device of claim 1, wherein a density of the A element is greater than a density of B element (Min, a first population density of a charge-trapping zone and a second population density of a charge-trapping zone differing by 10% shows the same local charge-trapping behavior is equivalent to the density of the element B being greater than to that of element A) at an interface of the charge trap layer in contact with the charge tunneling layer (Sharangpani, charge storage layer #54 in contact with the charge tunnel dielectric layer #56).
Regarding claim 14, Sharangpani in view of Min and further in view of Lin, Lai, and Yasuda teach the vertical non-volatile memory device of claim 1, wherein a density of the A element is greater than a density of B element (Min, a first population density of a charge-trapping zone and a second population density of a charge-trapping zone differing by 10% shows the same local charge-trapping behavior is equivalent to the density of the element B being greater than to that of element A) at an interface of the charge trap layer in contact with the charge blocking layer (Sharangpanj, charge storage layer #54 in contact with the blocking dielectric layer #52).
Regarding claim 17, Sharangpani in view of Min and further in view of Lin, Lai, and Yasuda teaches the vertical non-volatile memory device of claim 1. Both Min and Lin teach wherein a dielectric constant of the charge trap layer (Min, blocking dielectric #28) is equal to or greater than 9 (Min, blocking dielectric #28 in FIG. 3 & 4 and in para [0080] lists SiAlON, AlHfON, SiTaON, and ZrSiON include which are equal to or greater than a dielectric constant of 9 as a person of ordinary skill in the art would know at the time of filing that a dielectric constant of aluminum oxide is 9 and the dielectric constant of hafnium oxide is 20-25, thus, the dielectric constant of AlHfON falling between 9 and 25 would make it greater than or equal to 9. Additionally, para [0030] cites the use of a “high-k” dielectric material for the charge-trapping zones. Also, Lin teaches a high-k materials such as hafnium zirconium oxide Hf1-xZrxO, hafnium erbium oxide Hf1-xErxO, hafnium lanthanum oxide Hf1-xLaxO, hafnium yttrium oxide Hf1-xYxO, hafnium gadolinium oxide Hf1-xGdxO).
Claim 4 is rejected under 35 U.S.C. § 103 as being unpatentable over Sharangpani in view of Min, Lin, Lai, and Yasuda as applied to claim 1, 3, 11, 12-14, and 17 above, and further in view of further in view of Hayne et. al., US Patent Pub. No. 20170352767A1, hereinafter “Hayne” and Joo et. al., US Patent Pub. No. 20080157185A1, hereinafter “Joo.”
Regarding claim 4 Sharangpani in view of Min and further in view of Lin, Lai, and Yasuda teach the vertical non-volatile memory device of claim 1, wherein the B element is any one of aluminum (Al), hafnium (Hf), zirconium (Zr), silicon (Si) (Min, blocking dielectric #28 in FIG. 3 & 4 and in para [0080] lists SiAlON, AlHfON, SiTaON, and ZrSiON include any of silicon, aluminum, hafnium, and zirconium). Sharangpani, Min, Lin, Lai, and Yasuda do not teach the element boron (B) as cited in claim 4.
However, Joo teaches the element boron implemented as a charge trapping layer in its memory device (“charge trapping layer #220 comprises of or consist of…a silicon-boron-nitride (SiBN) layer #222…” in para [0019]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the non-volatile memory device having a charge tunneling layer, charge trap layer, and amorphous oxynitride dielectric structure and composition as taught by Sharangpani, Min, Lin, Lai, and Yasuda to include boron for the charge trapping layer as taught by Joo. Moreover, Sharangpani, Min, Lai, and Yasuda teach the overall memory device structure and function of charge storage through a charge trap layer, while Joo teaches that incorporating of boron within the trap layer materials improves charge retention, uniformity, and programming characteristics. A person of ordinary skill in the art would have been motivated to apply boron in the teachings of Joo and Hayne to the structure of Sharangpani and Min to get improvements to charge trapping and memory retention improvements. Thus, the combination represents a variation of known elements according to their established functions, and the resulting device would have been obvious under 35 U.S.C. § 103.
Sharangpani, Min, Lin, Lai, Yasuda, and Joo do not teach the element gallium (Ga) as cited in claim 4.
However, Hayne teaches the element gallium implemented as a charge trapping layer in its memory device (“charge trapping barrier may comprise…gallium antimonide GaSb” in para [0041]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the non-volatile memory device having a charge tunneling layer, charge trap layer, and amorphous oxynitride dielectric structure and composition as taught by Sharangpani, Min, and Lin, to include gallium elements as part of the charge trapping layer as taught by Hayne. Moreover, Sharangpani, Min, Lin, Lai, and Yasuda teach the overall memory device structure and function of charge storage through a charge trap layer, while Hayne teaches that incorporating gallium within the trap layer materials improves charge retention, uniformity, and programming characteristics. A person of ordinary skill in the art would have been motivated to apply gallium in the teachings of Hayne to the structure of Sharangpani, Min, Lin, Lai, and Yasuda to get improvements to charge trapping and memory retention improvements. Thus, the combination represents a variation of known elements according to their established functions, and the resulting device would have been obvious under 35 U.S.C. § 103.
Claims 5-7 are rejected under 35 U.S.C. § 103 as being unpatentable over Sharangpani in view of Min, Lin, Lai, and Yasuda as applied to claim 1, 3, 11, 12-14, and 17 above, and further in view of Seol et. al., US Patent Pub. No. 20080131710A1, hereinafter “Seol.”
Regarding claim 5, Sharangpani in view of Min, Min, Lin, Lai, and Yasuda teach the vertical non-volatile memory device of claim 1. Sharangpani, Min, Lin, Lai, and Yasuda do not teach wherein a content of the A element in the charge trap layer is about 40 at % or less.
However, Seol teaches wherein a content of the A element in the charge trap layer is about 40 at % or less (aluminum in aluminum (III) oxide which is a charge trap layer has a 2:3 ratio of aluminum to oxygen, thus is 40% of the aluminum element in para [0054]).
It would have been obvious to combine the devices of Sharangpani, Min, Lin, Lai, and Yasuda with Seol, since all teach non-volatile memory structures using charge trap layers. Seol’s disclosure of a charge trap layer having 40% or less atomic percentage of element “A,” a 60% or less atomic percentage of oxygen, and a charge trap layer having 6% or less atomic percentage of element “B,” would have been an obvious design choice to apply to the device of Sharangpani, Min, Lin, Lai, and Yasuda, to optimize charge storage and improve device performance. Thus, Seol cures the deficiencies of Sharangpani, Min, Lin, Lai, and Yusuda.
Regarding claim 6, Sharangpani in view of Min, Lin, Lai, Yasuda and Seol teach the vertical non-volatile memory device of claim 1, wherein a content of the oxygen element in the charge trap layer is about 60 at % or less (Seol, aluminum in aluminum (III) oxide has a 2:3 ratio of aluminum to oxygen, thus is 60% of the oxygen element in para [0054]).
Regarding claim 7, Sharangpani in view of Min, Lin, and Seol teach the vertical non-volatile memory device of claim 1, wherein a content of the B element in the charge trap layer is about 6 at % or less (Seol, Zn is doped with aluminum (III) oxide and Zn is element B and is cited as 5.1% in para [0087] which is less than 6 at %).
Claims 8-10 are rejected under 35 U.S.C. § 103 as being unpatentable over Sharangpani in view of Min, Lin, Lai, and Yasuda as applied to claim 1, 3, 11, 12-14, and 17 above, and further in view of Calka et. al., US Patent Pub. No. 20180122959A1, hereinafter “Calka.”
Regarding claim 8, Sharangpani in view of Min, Lin, Lai, and Yasuda teach the vertical non-volatile memory device of claim 1. Sharangpani and Min do not teach wherein the charge trap layer further includes carbon.
However, Calka teaches wherein the charge trap layer further includes carbon (charge trap layer #350 is citied and the carbon is “less than about 5-at%” in para [0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the devices of Sharangpani, Min, and Lin with Calka, since Calka teaches adding less than 5 atomic percent carbon, equal to the nitrogen concentration, to improve charge trap uniformity and stability. Applying Calka’s composition to the charge trap layers of Sharangpani, Min, Lin, Lai, and Yasuda would yield performance benefits.
Regarding claim 9, Sharangpani in view of Min, Lin, Lai, Yasuda, and Calka teach the vertical non-volatile memory device of claim 8, wherein a content of carbon is less than or equal to a content of nitrogen in the charge trap layer (Calka, carbon is “less than about 20 at-% and being up to less than “1 at-%”, whilst the nitrogen is up to “20 at-%” to about “60 at-%” in para [0037]).
Regarding claim 10, Sharangpani in view of Min, Lin, Lai, Yasuda, and Calka teach the vertical non-volatile memory device of claim 8, wherein a content of carbon is less than or equal to a content of nitrogen in the charge trap layer (the carbon is “less than about 5-at %” in para [0037] and nitrogen includes a range that is up to “20-at %” of nitrogen, thus, carbon is less than or equal to the nitrogen content).
Claim 15 is rejected under 35 U.S.C. § 103 as being unpatentable over Sharangpani as applied to claims 1, 3, 11, 12-14, and 17 above, in view of printed publication Andringa et. al., “Dynamics of charge carrier trapping in NO2 sensors based on ZnO field-effect transistors”, hereinafter “Andringa.”
Regarding claim 15, Sharangpani, Min, Lin, Lai, and Yasuda teaches the vertical non-volatile memory device of claim 1. Sharangpani, Min, Lin, Lai, and Yasuda do not teach wherein a trap level of the charge trap layer is about 1.2 eV or more.
However, Andringa teaches wherein a trap level of the charge trap layer is about 1.2 eV or more (“the activation energies of trapping and releasing NO2 content is…1.2 eV respectively”).
It would have been obvious to combine Sharangpani, Min, Lin, Lai, and Yasuda with Andringa since Sharangpani, Min, Lin, Lai, and Yasuda teach charge trap layers for non-volatile memory devices, and Andringa discloses a trap level of about 1.2 eV for trapping and releasing NO2. A person of ordinary skill would have recognized that using a trap level of 1.2 eV as taught in Andringa would optimize charge retention and release characteristics in the memory devices of Sharangpani.
Claim 18 is rejected under 35 U.S.C. § 103 as being unpatentable over Sharangpani, Min, Lin, Lai, and Yasuda as applied to claim 1, 3, 11, 12-14, and 17 above, further in view of printed publication Khelidj et. al., “Ge(Sn) growth on Si(001) by magnetron sputtering” hereinafter “Khelidj.”
Regarding claim 18, Sharangpani, Min, Lin, Lai, and Yasuda teaches the vertical non-volatile memory device of claim 1. Sharangpani teaches wherein the charge trap layer includes a nanocrystal of about 10 at % or less.
However, Khelidj teaches wherein the charge trap layer includes a nanocrystal of about 10 at % or less (incorporation of Sn nanocrystals is 10%).
It would have been obvious to combine Sharangpani, Min, Lin, Lai, and Yasuda with Khelidj since Sharangpani teaches charge trap layers for non-volatile memory devices, and Khelidj discloses tin nanocrystals with 10 at %. A person of ordinary skill would have recognized that using nanocrystals with an atomic percentage of 10 as taught in Khelidj would optimize charge retention and release characteristics in the memory devices of Sharangpani, Sharangpani, Min, Lin, Lai, and Yasuda.
Claim 19 is rejected under 35 U.S.C. § 103 as being unpatentable over Sharangpani as applied to claim 1, 3, 11, 12-14, and 17 above, and further in view of De Windt et. al., US Patent Pub. No. 20090239280A1 hereinafter “Windt.”
Regarding claim 19, Sharangpani, Min, Lin, Lai, and Yasuda teach the vertical non-volatile memory device of claim 18. Sharangpani does not teach wherein the nanocrystal has a diameter in a range between about 0.5 nm and about 5 nm.
However, Windt teaches wherein the nanocrystal has a diameter in a range between about 0.5 nm and about 5 nm (nanocrystal ranging between the size of 0.5 nm to about 5 nm in para [0041]).
It would have been obvious to combine Sharangpani, Min, Lin, Lai, and Yasuda with Windt since Sharangpani, Min, Lin, Lai, and Yasuda teach charge trap layers for non-volatile memory devices, and Windt discloses nanocrystal ranging between the size of 0.5 nm to about 5 nm. A person of ordinary skill would have recognized that using a nanocrystal ranging between the size of 0.5 nm to about 5 nm as taught in Windt would be an optimal range and size of nanocrystals for charge retention and release characteristics in the memory devices of Sharangpani, Min, Lin, Lai, and Yasuda .
Claim 20 is rejected under 35 U.S.C. § 103 as being unpatentable over Sharangpani as applied to claim 1, 3, 11, 12-14, and 17 above, and further in view of Ganguly et. al., US Patent Pub. No. 20110281429A1 hereinafter “Ganguly.”
Regarding claim 20, Sharangpani, Min, Lin, Lai, and Yasuda teaches the vertical non-volatile memory device of claim 1. Sharangpani, Min, Lin, Lai, and Yasuda do not teach wherein a thickness of the charge trap layer is in a range between about 5 nm and about 30 nm.
However, Ganguly teaches wherein a thickness of the charge trap layer is in a range between about 5 nm and about 30 nm (charge trapping layer is in the range of 1 nm to 20 nm in para [0023]).
It would have been obvious to combine Sharangpani, Min, Lin, Lai, and Yasuda with Ganguly since Sharangpani, Min, Lin, Lai, and Yasuda teach charge trap layers for non-volatile memory devices, and Ganguly discloses the charge trapping layer having a thickness in the range of 1 nm to 20 nm. A person of ordinary skill would have recognized that using a charge trapping layer with a thickness is in the range of 1 nm to 20 nm overlaps the claimed range of 5-30 nm and extends only slightly beyond the range taught by Ganguly. In accordance with MPEP § 2144.05, the discovery of an optimum or workable range by routine experimentation within a known range is considered obvious absent a showing of criticality or unexpected results. Since no evidence of criticality for the claim 5-30 nm range has been provided, selecting such a thickness in the combined device of Sharangpani would have been obvious matter of routine optimization to achieve faster device performance.
Allowable Subject Matter
Claim 16 contains allowable subject matter.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not explicitly disclose a trap density of the charge trap layer is in a range between about 18×10¹⁸/cm² and about 30×10¹⁸/cm². Specifically, while the closest prior art of record, Sharangpani, discloses a memory device with a pillar, channel layer surrounding the pillar, a charge tunneling layer surrounding the channel layer, a charge trap layer with an amorphous oxynitride surrounding the tunneling layer, a charge blocking layer, separation layers and gate electrode arranged along the side surface of the blocking layer, Sharangpani, Min, Lin, Lai, and Yasuda do not teach or suggest the claim area density in a range between 18×10¹⁸/cm² and about 30×10¹⁸/cm². In addition, there is no clear motivation to add this specific areal density for the charge trapping layer into the original memory structure in Sharangpani, Min, Lin, Lai, and Yasuda absent hindsight reasoning. Sharangpani, Min, Lin, Lai, and Yasuda focus on device structure and does not suggest controlling or optimizing charge density by indicating that such a range would provide improvement. In addition, although Andringa describes “a trapped charge density of 6 × 10¹⁴ charges per cm²”, the value is several magnitudes lower than the claimed range.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments have been considered but they are not persuasive.
Applicant argues in substance:
“With regard to original claim 2 (the features of which have been incorporated into
claim 1 as amended), the Examiner alleges that Min teaches a charge trap layer
(blocking dielectric 28 in FIGS. 3 & 4) including AxByOzN because par. 80 of Min lists
SiAlON, AlHfON, SiTaON, where Si and Al or Al and Hf or Si and Ta are different metal
elements with oxygen and nitrogen. Applicants respectfully disagree.
Applicants note that original claim 2 specifically requires AxByOzN (1-x-y-z) (A
and B are different elements, and at least one of A or B is a metal element, 0 is oxygen,
N is nitrogen). However, the cited portion (e.g., par. 80) of Min
merely teaches elements included in the layer (e.g., a chemical formula of the layer) and
fails to specifically disclose or fairly teach the claimed specific stoichiometry (e.g., the
claimed species).”
The argument is not persuasive. As noted in the claim mapping above, Sharangpani, Min, Lin, Lai, and Yasuda teaches the new limitation of claim 1. A person of ordinary skill in the art would know to combine Sharangpani, Min, Lin, Lai, and Yasuda Min and know the combination of these arts discloses charge trapping materials that include oxynitride type compounds with elements A and B such as AlHfON, demonstrating that combining oxygen and nitrogen within the trap layer with two metallic elements improves the dielectric and charge trapping properties. Lin teaches z≥x because hafnium zirconium oxide Hf1-xZrxO, hafnium erbium oxide Hf1-xErxO, hafnium lanthanum oxide Hf1-xLaxO, hafnium yttrium oxide Hf1-xYxO, hafnium gadolinium oxide Hf1-xGdxO show that the subscript for oxygen is 1 representing “z” in the claim and the subscript for hafnium which is 1-x is less than 1 which is “x” in the claim with “z” which is 1 being greater than x in para [0024]. Furthermore, Yasuda discloses a hafnium oxynitride film is expressed by (HfO2)y(Hf3N4)1-y, (0<y<1) where Hf has a subscript of 3 and 3 is greater than 0.3 which teaches the claim limitation x≥0.3, and Lai teaches 0<y≤0.1. Specifically, that element A and element B exist in proportions defined by 1-x and x, respectively, while oxygen has a subscript of 1, thereby indicating that the oxygen content is greater than that of element B. A person of ordinary skill in the art know to obviously apply the composition relationships disclosed by Lin, Lai, and Yasuda to the oxynitride-type trapping materials of Min, since both references are directed toward optimizing dielectric and use of similar materials used in memory devices. Furthermore, composition limits such as element A being less than or equal to 0.3, element B being equal to or less than 0.1 but greater than 0, and oxygen being greater than element B, would have provided a routine parameter for adjusting the stoichiometry of the oxynitride compounds taught by Min. Additionally, it is well known to a person of ordinary skill in the art that in a charge trapping memory oxynitride layer, the second metal element “B” is doped and has a lower concentration and percentage of atoms in relation to the rest of the compound. Thus, it would have been obvious to combine the structures features taught by Sharangpani with the oxynitride materials of Min and the compositional relationships of Lin, Lai, and Yasuda to achieve the claimed memory device with improved performance and stable charge trapping characteristics It would be apparent to a person of ordinary skill in the art that the prior arts teach this stoichiometry.
.
Examiner would suggest in the interest of compact prosecution that the Applicant align the claim limitations in a manner to overcome the prior art. The new claim limitations that were amended in claim 1 are taught by a combination of Sharangpani, Min, Lin, Lai, and Yasuda since Sharangpani, Min, Lin, Lai, and Yasuda do not particularly teach or suggest the claim area density in a range between 18×10¹⁸/cm² and about 30×10¹⁸/cm². In addition, the Applicant is encouraged to amend the claims to clearly include the allowable subject matter in a manner that differs from the prior arts. Examiner is available for an interview to discuss any rejections or claim amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/MEHEK AHMED/Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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