DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted was filed after the mailing date. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-6, 9-10, 16-17, 20-21, 24-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by He et al. (“He”) (WO 2020228126 A1, citing from provided English translation).
Regarding claims 1-2, 5-6, 9, see similar rejections for claim 16-17, 20-21, 24 respectively which teach the physical structure performing the corresponding step.
Regarding claim 10, see similar rejection for claim 25 which teaches the physical structure performing the corresponding step.
Regarding claim 16, He teaches:
A data transmission apparatus, wherein the apparatus comprises: a non-transitory memory storing instructions; and a processor coupled to the non-transitory memory; wherein the instructions, when executed by the processor, cause the apparatus to be configured [¶0241, 101 figure 1] to: obtain first data, wherein the first data is produced through coding data using a first forward error correction (FEC) code type [¶0131, Figure 2, 201, “Chip 1 receives a first data stream sent by chip 2; the first data stream is a data stream encoded with a first forward error correction FEC code pattern.”]; determine a second FEC code type [¶0137 Figure 2, 202, “The chip 1 encodes the first data stream at least once to obtain a second data stream; wherein, the second data stream is encoded using at least the first FEC code type and the second FEC code type The cascaded FEC code stream”] based on a reference clock frequency of a first chip and an output rate corresponding to the first FEC code type [ ¶0265-270 See figure 17-18, second circuit producing encoded data (corresponding to first FEC code type) is RS code type with 400GbE, 400 Gb/s interface (corresponding to output rate corresponding to first FEC code type), and Figure 17-18 ¶0266 wherein device includes clock with timing thus based on clock frequency. Regarding the first circuit which receives the first FEC-coded data from the second circuit in Figure 18, “The first circuit includes an optical module or a clock and data recovery (Clock and Data Recovery, CDR). The CDR may be a circuit, and the industry also refers to the CDR as a retiming circuit (retimer).”]; code the first data based on the second FEC code type [¶0137 Figure 2, 202 “The chip 1 encodes the first data stream at least once to obtain a second data stream; wherein, the second data stream is encoded using at least the first FEC code type and the second FEC code type The cascaded FEC code stream””] to produce second data; and transmit the second data [¶0150-152, Figure 2, 203 “The chip 1 sends the second data stream to the chip 3.”].
Regarding claim 17, He teaches:
The apparatus according to claim 16, wherein the reference clock frequency of the first chip [Figure 17 shows second encoder, being the taught first circuit corresponding to the first chip, including a clock ¶0266], the output rate corresponding to the first FEC code type [¶0266, output of first encoder, being second circuit corresponding to first FEC code type, being 400 GbE thus output rate of 400 Gb/s], a codeword length of the second data [¶0267 codeword length of BCH(360,340) of first circuit forming second data codeword of 360 bits], and an information length in a codeword of the second data meet an overhead proportional relationship [¶0267 codeword length of BCH(360,340) of first circuit with 340 bits of information, Examiner noting that the claim does not specify the “overhead proportional relationship” thus since these are the parameters of the two encoders in Figure 18 ¶0266, these satisfy the overhead relationship of the cascaded encoders]; and the determining of the second FEC code type is based on the reference clock frequency of the first chip, the output rate corresponding to the first FEC code type, and the overhead proportional relationship [¶0266-267 output code based on the claimed parameters, e.g. clock frequency of incoming data encoded stream, output rate 400 GbE RS of previous encoder, and information / code length of BCH encoder corresponding to overhead proportional relationship].
Regarding claim 20, He teaches:
The apparatus according to claim 16, wherein the instructions, when executed by the processor, further cause the apparatus to be configured to: distribute the first data to produce a plurality of pieces of first subdata [Figure 18 shows data split into subdata before CDR via PMA from second RS encoder before BCH encoders (this being first data), over n physical paths ¶0266], separately code the plurality of pieces of first subdata based on the second FEC code type to produce a plurality of pieces of second subdata [Figure 18, ¶0266, BCH encoder for each path in CDR]; and transmit the plurality of pieces of second subdata [¶0266, Figure 18, transmitting plurality of subdata to MUX ¶0266].
Regarding claim 21, He teaches:
The apparatus according to claim 20, wherein the instructions, when executed by the processor, further cause the apparatus to be configured to: distribute the first data through a physical coding sublayer (PCS) channel to produce the plurality of pieces of first subdata; or distribute the first data through a physical medium attachment sublayer (PMA) to obtain produce the plurality of pieces of first subdata [Figure 18, ¶0266 shows PMA].
Regarding claim 24, He teaches:
The apparatus according to claim 16, wherein the first data is inside the first chip, or the first data is data that is received by the first chip and that is sent by a second chip [¶0266 Figure 18 shows components with first data received at BCH encoders corresponding to chip, see chip components within 101 of Figure 1].
Regarding claim 25, He teaches:
A data transmission apparatus, wherein the apparatus comprises: a non-transitory memory storing instructions; and a processor coupled to the non-transitory memory; wherein the instructions, when executed by the processor, cause the apparatus to be configured [Figure 2, ¶0241] to: receive second data [¶0153, chip 1 sends second data stream to chip 3], wherein the second data is data produced by coding first data by using a second forward error correction (FEC) code type [¶0137 Figure 2, 202 “The chip 1 encodes the first data stream at least once to obtain a second data stream; wherein, the second data stream is encoded using at least the first FEC code type and the second FEC code type The cascaded FEC code stream””], and the first data is produced through coding data using a first FEC code type [¶0131, Figure 2, 201, “Chip 1 receives a first data stream sent by chip 2; the first data stream is a data stream encoded with a first forward error correction FEC code pattern.”]; and decode the second data based on the second FEC code type, to produce decoded data [¶0153].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11-13, 26-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (“He”) (WO 2020228126 A1, citing from provided English translation) in view of Li et al. (“Li”) (WO 2016015288 A1).
Regarding claims 11-13 see similar rejections for claim 26-28 respectively which teach the physical structure performing the corresponding step.
Regarding claim 26, He teaches:
The apparatus according to claim 25.
He teaches decoding but not soft decision.
Li teaches:
wherein the instructions, when executed by the processor, further cause the apparatus to be configured to: perform soft-decision decoding on the second data based on the second FEC code type [page 11-12 “ S203. Perform soft decision decoding on each codeword according to all test sequences generated for each codeword, to obtain at least one hard output result of each codeword.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement soft decoding as this improves the performance of the transmission system higher than hard decision see page 1-2.
Regarding claim 27, He-Li teaches:
The apparatus according to claim 26, wherein the instructions, when executed by the processor, further cause the apparatus to be configured to:
calculate a confidence of each bit in a received codeword based on received quantized soft- decision information to produce a confidence sequence [Li “S203, soft decision decoding “The soft information of each codeword refers to the soft information of each bit of each codeword, including the confidence of the value,” page 11-14];
select M least reliable bit locations from the confidence sequence, and in the M least reliable bit locations, successively attempting to perform bitwise inversion on all combinations of 0, 1, 2, ..., and N (N
PNG
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11
8
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Greyscale
M) bit locations to produce a plurality of test codewords [Li page 11-14 “The core idea of the above soft decision BCH algorithm is to try to estimate and correct codeword errors through a limited amount of test error patterns. […] the absolute value of the soft information of a certain bit can indicate the reliability of the bit, and the smaller the absolute value, the less reliable the value of the bit is, and the probability of being the wrong bit […] Therefore, for a codeword, first select the P bits with the smallest absolute value of the soft information on the codeword, and consider the error of the codeword. It is most likely to appear in the P positions (P is an integer greater than zero, and the value of P can be set as needed, which is not limited here). Then, 2 .sup.P test sequences (Test Sequence, TS) are constructed based on the P positions.” See example where number of unreliable bits is P=2 figure 4, these bits are flipped to produce all combinations 2 bits, all combinations of bits are inverted to produce test codewords];
perform hard-decision decoding error correction on each of the plurality of test codewords to produce a plurality of corrected test codewords [ Li page 11-14 “S203. Perform soft decision decoding on each codeword according to all test sequences generated for each codeword, to obtain at least one hard output result of each codeword.”]; calculate Euclidean distances between the confidence sequence and the plurality of corrected test codewords [Li page 11-14 “First, obtaining an Euclidean distance between the hard-coded result of the codeword and the soft information of the codeword, which may be based on the value of each bit of each hard output result of the codeword”]; and select a corrected test codeword from the plurality of corrected test codewords corresponding to a smallest distance as a final corrected codeword output [Li page 11-14 “According to the above algorithm, K Euclidean distances can be obtained according to the κ hard output results, and then the hard output result corresponding to the smallest Euclidean distance is selected as the optimal hard output result as the first decoding result” see rationale for combination as in claim 11 for each limitation as these are part of the soft-decision process in the modification of claim 26].
Regarding claim 28, He-Li teaches: the apparatus according to claim 27.
He teaches decoding but not hard decoding when there are no errors.
Li teaches wherein the instructions, when executed by the processor, further cause the apparatus to be configured to: if there is no correctable codeword in the plurality of test codewords, use a hard-decision result corresponding to the received codeword as an output codeword [Li page 11-15 “S211 The total number of codewords of the decoding result of S204, that is, whether the hard decision decoding is not error. For example, if the decoding result of S204 is 256 code words and the error is 0, it is confirmed that all 256 code words are correctly decoded and can be jumped out […] after performing at least one soft decision decoding on multiple codewords, determining whether the decoding result of the soft decision decoding meets the switching condition of switching to hard decision decoding” thus when there are no correctable code words just use the hard decoding].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement hard decoding in this scenario to avoid too much power consumption dedicated to soft decoding see Li page 1-2.
Claim(s) 14-15, 29-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (“He”) (WO 2020228126 A1, citing from provided English translation) in view of Landau et al. (“Landau”) (US 20190044839 A1).
Regarding claims 14-15 see similar rejections for claim 29-30 respectively which teach the physical structure performing the corresponding step.
Regarding claim 29, He teaches:
The apparatus according to claim 25.
He teaches decoding but not re-coding.
Landau teaches wherein the instructions, when executed by the processor, further cause the apparatus to be configured to: re-code the decoded data based on a third FEC code type to produce re-coded data; and transmit the re-coded data [¶0047, data in 66b/64b received and decoded, then re-encode outgoing data with 66b/64b encoding].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to specify re-encoding after decoding as in Landau in order that incoming and outgoing bit streams may be error corrected without casing variable delay ¶0028.
Regarding claim 30, He teaches:
The apparatus according to claim 29, wherein the third FEC code type is the second FEC code type [Landau ¶0047 encoding is consistently 66b/64b Reed-Solomon see rationale for combination as in claim 29].
Claim(s) 4, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (“He”) (WO 2020228126 A1, citing from provided English translation) in view of Gustlin et al. (“Gustlin”) (US 20080138075 A1).
Regarding claims 4 see similar rejections for claim 19 which teaches the physical structure performing the corresponding step.
Regarding claim 19, He teaches:
The apparatus according to claim 17.
He teaches distributing the codeword but not on logical channels wherein the length of the data is an integer multiple with the quantity.
Gustlin teaches wherein the codeword length of the second data is in an integer multiple relationship with a quantity of logical channels through which the second data is distributed [¶0024, codeword of size 64/66B transported out of two virtual lanes, 66 being integer multiple of two].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to specify the integer multiple relationship between codeword and logical channels as in Gustlin who teaches this relationship in distributing codewords allows for greater transition density ¶0023-24.
Claim(s) 7, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (“He”) (WO 2020228126 A1, citing from provided English translation) in view of Zhong et al. (“Zhong”) (WO 2017005121 A1).
Regarding claims 7 see similar rejections for claim 22 which teaches the physical structure performing the corresponding step.
Regarding claim 22, He teaches:
The apparatus according to claim 16, wherein the instructions, when executed by the processor, further cause the apparatus to be configured to: distribute the second data to produce a plurality of pieces of third subdata [¶0266, Figure 18, data output from BCH encoder as second data in plurality of paths corresponding to plurality of pieces of third subdata].
Zhong teaches and send the plurality of pieces of third subdata through a plurality of logical channels [page 1-2 “The 100GE Ethernet interface is usually divided into 20 virtual channels, so that 20 virtual channels can be compatible with different combinations of the above 10 channels, 5 channels, 4 channels, and 2 channels. The transmitting side of the 100GE Ethernet system encodes the data into 64B/66B and distributes it to the 20 virtual channels using the 64B/66B coded block as the unit particle”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to specify the use of logical channels as in Zhong for distributing the codewords of He, Zhong teaching this allows for exceeding physical carrying capacity see page 102.
Claim(s) 8, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (“He”) (WO 2020228126 A1, citing from provided English translation) in view of Wang et al. (“Wang”) (US 20140122976 A1).
Regarding claims 8 see similar rejections for claim 23 which teaches the physical structure performing the corresponding step.
Regarding claim 23, He teaches:
The apparatus according to claim 16, wherein
the apparatus determines the second FEC code type based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type [[¶0266-267 output code based on the claimed parameters, e.g. clock frequency, output rate 400 GbE RS encoder, and information / code length of BCH encoder corresponding to overhead proportional relationship].
He teaches determining the second FEC code type but not in response to auto-negotiation.
Wang teaches wherein the instructions, when executed by the processor, further cause the apparatus to be configured to: perform auto-negotiation with a third chip that is adapted to receive the second data sent by the first chip, wherein in response to an auto-negotiation result indicating that concatenated coding is required, the apparatus determines the second FEC code type based on the reference clock frequency of the first chip and the output rate corresponding to the first FEC code type [¶0056, auto-negotiation for determining best possible mode, ¶0064 determine concatenating code].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to specify in the setup of the channel in He performing the auto-negotiating process for determining the coding method as in Wang who teaches this allows to negotiate the best possible shared mode of operation ¶0056.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20150162937 A1.
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/JAY L VOGEL/Primary Examiner, Art Unit 2478