DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17, claims “an input for receiving a user selection…” and a “a control output applied to the controlled electrical loads…”. It is unclear to the examiner what “an input for receiving” and “a control output applied to the controlled electrical loads” are. These limitations are claimed as part of a “sequencer” and can therefore be interpreted as software, however no memory or process is claimed to store or execute said software. Currently these limitations are unclear.
Claim 17 claims, “determine and implement a desired wait time” and “generate the control output to be applied to the controlled electrical loads to achieve the desired electrical load behavior after the desired wait time;”. It is unclear to the examiner what step the “desired wait time” is waiting for. Is after a program run flag or after an input for receiving a user selection indicating a desired electrical load or some other trigger/event. Currently as claimed it is unclear how the wait time is implemented and therefore the claim is rejected for being unclear.
Claim 17, claims “a control output applied to the controlled electrical load” and “generate the control output to be applied to the controlled electrical loads”. It is unclear to the examiner how the limitation “a control output applied to the controlled electrical load” is performed prior to the generation of the control output. The claim further claims “repeat the generation step”. If the generation of the controlled output is repeatedly being performed, each generated control output should be applied for each iteration. However, as currently claimed these limitations are unclear.
Claims 18-24 are rejected for being dependent on rejected claim 17.
Claims 25-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 25, claims “an input for receiving a user selection…” and a “a control output applied to the controlled electrical loads…”. It is unclear to the examiner what “an input for receiving” and “a control output applied to the controlled electrical loads” are. These limitations are claimed as part of a “sequencer” and can therefore be interpreted as software, however no memory or process is claimed to store or execute said software. Currently these limitations are unclear.
Claim 25, claims “a control output applied to the controlled electrical loads” and “generate the control output to be applied to the controlled electrical loads”. It is unclear to the examiner how the limitation “a control output applied to the controlled electrical load” is performed prior to the generation of the control output. The claim further claims “repeat the generation step”. If the generation of the controlled output is repeatedly being performed, each generated control output should be applied for each iteration. However, as currently claimed these limitations are unclear.
Claims 26-30 are rejected for being dependent on rejected claim 25.
Claim 31 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 31, claims “applying a control output to the controlled electrical loads” and “generate the control output to be applied to the controlled electrical loads”. It is unclear to the examiner how the limitation “applying a control output to the controlled electrical loads” is performed prior to the generation of the control output. The claim further claims “repeat the generation step”. If the generation of the controlled output is repeatedly being performed, each generated control output should be applied for each iteration. However, as currently claimed these limitations are unclear.
Claim 31 claims, “determine and implement a desired wait time” and “generate the control output to be applied to the controlled electrical loads to achieve the desired electrical load behavior after the desired wait time;”. It is unclear to the examiner what step the “desired wait time” is waiting for. Is after a program run flag or after an input for receiving a user selection indicating a desired electrical load or some other trigger/event. Currently as claimed it is unclear how the wait time is implemented and therefore the claim is rejected for being unclear.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 17-18, 20, 22 and 24 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 1 recites, “determine a state of a program run flag”, “determine and implement a desired wait time”, “generate the control output to be applied to the controlled electrical loads…” and “repeat the generating step based on a desired number of repeat sequences”. The limitations of “determine”, “determine”, “generate” and “repeat” as drafted are functions that, under their broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and /or opinion, or even with the aid of pen and paper. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The claim recites the following additional elements “an input for receiving a user selection…” and “a control output applied to the controlled electrical loads…”. The additional elements are insignificant pre solution activities, they are recited at a high level of generality and thus are insignificant extra-solution activities. See MPEP 2106.05(g). Further, the limitations “a processor and a memory” are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using generic computer, and/or mere computer components, MPEP 2106.05(f). Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a processor and memory” amounts to no more than mere instructions, or generic computer/computer components to carry out the exception, for the limitations of “an input for receiving a user selection…” and “a control output applied to the controlled electrical loads…”, they are identified as well-understood, routine, conventional activities (2106.05(d)). The recitation of generic computer instruction and computer components to apply the judicial exception, and the well-understood, routine, conventional activities do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, claim 1 is not patent eligible under 35 USC 101.
Claim 18, further defines what the controlled electrical loads include and the output applied to the electronic switch. The additional elements are neither a practical application under prong 2, nor an inventive concept under step 2B.
Claim 20, further defines the controlled electrical load. The additional elements are neither a practical application under prong 2, nor an inventive concept under step 2B.
Claim 22 further defines the repeating the generation step. The additional elements are neither a practical application under prong 2, nor an inventive concept under step 2B.
Claim 24, further defines the activation and deactivation of the switch. The additional elements are neither a practical application under prong 2, nor an inventive concept under step 2B.
Claims 25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 1 recites, “determine a state of a program run flag”, “determine and implement a desired wait time”, “determining whether an infinite loop condition is present”, “changing the sate of the program fun flag to false”, “generate the control output to be applied to the controlled electrical loads…” and “repeat the generating step based on a desired number of repeat sequences”. The limitations of “determine”, “determine”, “determine”, “changing”, “generate” and “repeat” as drafted are functions that, under their broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and /or opinion, or even with the aid of pen and paper. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The claim recites the following additional elements “an input for receiving a user selection…” and “a control output applied to the controlled electrical loads…”. The additional elements are insignificant pre solution activities, they are recited at a high level of generality and thus are insignificant extra-solution activities. See MPEP 2106.05(g). Further, the limitations “a processor and a memory” are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using generic computer, and/or mere computer components, MPEP 2106.05(f). Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a processor and memory” amounts to no more than mere instructions, or generic computer/computer components to carry out the exception, for the limitation of “an input for receiving a user selection…” and “a control output applied to the controlled electrical loads…”are identified as well-understood, routine, conventional activities (2106.05(d)). The recitation of generic computer instruction and computer components to apply the judicial exception, and the well-understood, routine, conventional activities do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, claim 1 is not patent eligible under 35 USC 101.
Claim 26, further defines the controlled electrical loads. The claim further claims “determine whether an instruction to be executed in an on command or an off command…” and “the selected electronic switch is identified and the selected electronic switch is deactivated”. These steps are interpreted as additional limitations of the abstract idea “Mental Process”. Nothing in the claimed limitations prevent these limitations from being performed in the mind. The additional limitations are neither a practical application under prong 2, nor an inventive concept under step 2B.
Claim 27, further defines the controlled electrical loads. The claim further claims “determine whether the electronic switches are a coordinated set of electronic switches. These steps are interpreted as additional limitations of the abstract idea “Mental Process”. Nothing in the claimed limitations prevent these limitations from being performed in the mind. The additional limitations are neither a practical application under prong 2, nor an inventive concept under step 2B.
Claim 28, further defines the controlled electrical loads. The claim further claims “determine whether an instruction to be executed is a WAIT command…”. This step is interpreted as additional limitations of the abstract idea “Mental Process”. Nothing in the claimed limitations prevents these limitations from being performed in the mind. The claims further claims an additional limitation of “retrieving from memory a predetermined wait time to be executed”. The courts have identified mere data gathering is also well-understood, routine and conventional activity. See MPEP 2106.05(d) and MPEP 2106.05(f). The additional limitations are neither a practical application under prong 2, nor an inventive concept under step 2B.
Claims 29 claims, “execute the wait command…” and “setting the Run flag to FALSE”. The steps of “execute” and “setting” are additional limitations of the abstract idea “Mental Process”. Nothing in the claimed limitations prevent these limitations from being performed in the mind.
Claim 30, further defines the controlled electrical loads. The claim further claims “determine whether an instruction to be executed is a repeat command…” and “the repeat command is executed in accordance with a loop count variable”. These steps are interpreted as additional limitations of the abstract idea “Mental Process”. Nothing in the claimed limitations prevents these limitations from being performed in the mind. The additional limitations are neither a practical application under prong 2, nor an inventive concept under step 2B.
Claim 31 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 1 recites, “applying the control output to the controlled electrical loads”, “determining a state of a program run flag”, “determining and implement a desired wait time”, “generating the control output to be applied to the controlled electrical loads…” and “repeating the generating step based on a desired number of repeat sequences”. The limitations of “applying”, “determining”, “determining”, “generating” and “repeating” as drafted are functions that, under their broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and /or opinion, or even with the aid of pen and paper. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The claim recites the following additional element “receiving a user selection indicating a desired electrical load behavior”. The additional element is a insignificant pre solution activities, it is recited at a high level of generality and thus is a insignificant extra-solution activity. See MPEP 2106.05(g). Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “receiving a user selection indicating a desired electrical load behavior” is identified as well-understood, routine, conventional activities (2106.05(d)). The recitation of generic computer instruction and computer components to apply the judicial exception, and the well-understood, routine, conventional activities do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, claim 1 is not patent eligible under 35 USC 101.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-19, 21-24 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Lair et al. (US 5,110,616) and further in view of Noritaka (JPH02267602A).
As per claim 17, Lair et al. teaches the invention as claimed including, “A sequencer for implementing time-dependent behavior of controlled electrical loads, comprising:” Lair et al. teaches a sequence controller is a self contained, microprocessor based unit which provides a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 2, lines 35-47).
“an input for receiving a user selection indicating a desired electrical load behavior;”
Front panel switchers allow the operator to control three main parameters of the sequence: DELAY TIME, REPEAT TIME, and NUMBER OF PULSES (column 7, lines 60 – column 8, lines 1-28).
“a control output applied to the controlled electrical loads to achieve the desired electrical load behavior;”
The controller provides (output) a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 7, lines 45-59 and Column 9, lines 1-5).
“a processor and a memory containing instructions, which when executed by the processor cause the processor to:”
Column 8, lines 48-56 and column 9, lines 5-21.
“determine and implement a desired wait time;”
A user can manually control a DELAY TIME parameter (column 8, lines 3-19). Also see column 11, lines 36-43.
“generate the control output to be applied to the controlled electrical loads to achieve the desired electrical load behavior after the desired wait time; and”
When the total delay time has been executed, the program checks the number of pulses and if its not zero then the first spray is triggered (Column 11, lines 36 – column 12, lines 1-10.
“repeat the generating step based on a desired number of repeat sequences to be performed.”
After each spray trigger has been produced the program determines if the correct NUMBER of SPRAYS has been triggered. IF so, the program loops back to its beginning and reads the BCD switch again (column 12, lines 3-21). Also see column 8, lines 19-28.
Lair et al. does not explicitly appear to teach, “determine a state of a program run flag;”
Noritaka teaches a sequence controller comprising a RUN flag that controls the execution/stopping of a sequence table (page 7). Also see page 9.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lair et al. with Noritaka because both teach a sequence controller. Incorporating the execution-state RUN flag into Lair’s sequence controller would allow the controller to control the executing/stopping of the sequence /output of the controller using a well-known method and would have been obvious to try.
As per claim 18, Lair et al. further teaches, “The sequencer of claim 17, wherein the controlled electrical loads include at least one electronic switch and the output applied to the electronic switch causes the switch to selectively activate and deactivate.”
Lair et al. teaches each pulse produced by the sequence controller is about eight milliseconds long. The output is provided by an optically coupled, open collector NPN, transistor which sinks current to DC ground. It is normally “off” and switches “on” during each pulse interval (column 9, lines 1-5).
As per claim 19, Lair et al. further teaches, “The sequencer of claim 18, further comprising the step of determining whether the electronic switch is an element of a coordinated set of electrical loads, and if the electronic switch is an element of a coordinated set of electrical loads, then generating and applying the control output to all elements of the coordinated set of electrical loads to selectively activate and deactivate the set of electrical loads in like manner.”
The sequence controller is a self contained, micro-processor based unit which provide a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 2, lines 40-54). Figure 2 shows both a pan sensor output and a valve driver signal. Also see column 7, lines 45-60.
As per claim 21, Lair et al. further teaches, “The sequencer of claim 17, wherein each step of repeating the generating step selectively activates the electrical load for a predetermined amount of time.”
The output is provided by an optically coupled, open collector NPN, transistor which sinks current to DC ground. It is normally “off” and switches “on” during each pulse interval (column 9, lines 1-5). Also see column 11, lines 42 – column 12, lines 1-21 and figure 2.
As per claim 22, Lair et al. further teaches, “The sequencer of claim 17, wherein the step of repeating the generating step continues until an off command is received.
Lair et al. teaches the sequence controller allows the operation to manually trigger a pulse sequence, stop a pulse sequence which is in progress, bypass the controller with the sensor signal, or turn off the controller output (column 8, lines 27-53). Also see column 12, lines 1-21.
As per claim 23, Lair et al. further teaches, “The sequencer of claim 22, further comprising a step of deactivating the electrical load based on receiving an off command.”
Lair et al. teaches the sequence controller allows the operation to manually trigger a pulse sequence, stop a pulse sequence which is in progress, bypass the controller with the sensor signal, or turn off the controller output (column 8, lines 27-53). Also see column 8, lines 37-47.
As per claim 24, Lair et al. further teaches, “The sequencer of claim 18, wherein the activation and deactivation of the switch includes proportional control whereby the switch is partially activated and deactivated in a range from 0 to 100%.”
The sequence controller provides a user programmable sequence of electronic pulses (column 2, lines 41-45). Also see figure 2.
As per claim 31, claim 31 contains similar limitations to claim 1 and is therefore rejected for the same reasons.
Claims 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lair et al. (US 5,110,616) and Naritaka (JPH02267602A) as applied to claim 14 above, and further in view of Farrington et al. (US 5,821,876).
As per claim 20, Lair et al. further teaches, “The sequencer of claim 17, wherein the controlled electrical loads include an electronic circuit breaker unit and the step of generating the control output selectively activates and deactivates a primary breaker of the electronic circuit breaker unit.”
The sequence controller is a self contained, micro-processor based unit which provides a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 2, lines 40-54). Lair et al. teaches each pulse produced by the sequence controller is about eight milliseconds long. The output is provided by an optically coupled, open collector NPN, transistor which sinks current to DC ground. It is normally “off” and switches “on” during each pulse interval (column 9, lines 1-5). Also see figure 2.
However, Lair et al. does not explicitly teach a electronic circuit breaker.
Farrington et al. teaches a electronic circuit breaker that can receive signals from a controller (column 2, lines 59 – column 2, lines 1-8).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lair et al. with Farrington et al. because both teach a sequence controller. Lair et al. the sequence controller is a self contained, micro-processor based unit which provides a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 2, lines 40-54). Substituting a electronic circuit breaker for the valves, relays, solenoids and timers of Lair et al. would be nothing more than a design choice and would have been obvious to try.
Claims 25-30 are rejected under 35 U.S.C. 103 as being unpatentable over Lair et al. (US 5,110,616) and further in view of Noritaka (JPH02267602A) and Brewer (US 2023/0027534 A1).
As per claim 25, Lair et al. teaches the invention as claimed including, “A sequencer for implementing time-dependent behavior of controlled electrical loads, comprising:”
Lair et al. teaches a sequence controller is a self contained, microprocessor based unit which provides a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 2, lines 35-47).
“an input for receiving a user selection indicating a desired electrical load behavior;”
Front panel switchers allow the operator to control three main parameters of the sequence: DELAY TIME, REPEAT TIME, and NUMBER OF PULSES (column 7, lines 60 – column 8, lines 1-28).
“a control output applied to the controlled electrical loads to provide selective activation and deactivation of the electrical loads to achieve the desired electrical load behavior;” The controller provides (output) a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 7, lines 45-59 and Column 9, lines 1-5). Lair et al. teaches each pulse produced by the sequence controller is about eight milliseconds long. The output is provided by an optically coupled, open collector NPN, transistor which sinks current to DC ground. It is normally “off” and switches “on” during each pulse interval (column 9, lines 1-5).
“a processor and a memory containing instructions, which when executed by the processor cause the processor to:”
Column 8, lines 48-56 and column 9, lines 5-21.
Lair et al. does not explicitly appear to teach, “determine a state of a program run flag;”
Noritaka teaches a sequence controller comprising a RUN flag that controls the execution/stopping of a sequence table (page 7). Also see page 9.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lair et al. with Noritaka because both teach a sequence controller. Incorporating the execution-state RUN flag into Lair’s sequence controller would allow the controller to control the executing/stopping of the sequence /output of the controller using a well-known method and would have been obvious to try.
“determine and implement a desired wait time based on a status of a predetermined wait time counter;” Lair et al. teaches, a user can manually control a DELAY TIME parameter (column 8, lines 3-19). Also see column 11, lines 36-43.
Lair et al. does not explicitly appear to teach, “determining whether an infinite loop condition is present and if so, then changing the state of the program run flag to false and ceasing any further operation;”
Brewer et al. teaches a method to detect and terminate programmable atomic transactions that are stuck in an infinite loop. If an instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used may be treed, and a response may be sent to a calling processor (Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lair et al. and Noritaka et al. with Brewer et al. Lair et al. teaches a sequence controller is a self contained, microprocessor based unit which provides a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 2, lines 35-47). Noritaka et al. teaches a sequence controller comprising a RUN flag that controls the execution/stopping of a sequence table (page 7). Therefore, together they teach a sequence controller that can start and stop a sequence using a run flag. Brewer et al. teaches determine If there is a infinite loop and ending the program to break the loop. This will improve Lair et al. allowing it to also determine if there is a infinite loop and end its sequence. An infinite loop would have the system stuck performing the same actions and use valuable resources. The examiner further states that as stated above the Run flag as taught by Noritaka et al. controls execution and stopping of the sequence so if the executing is stopped for a infinite loop as taught in Brewer et al. it would have been inherent for the Run Flag to be false since the execution has stopped.
“if an infinite loop condition is determined to be not present, then generate the control output to be applied to the controlled electrical loads to achieve the desired electrical load behavior after the desired wait time; and”
When the total delay time has been executed, the program checks the number of pulses and if its not zero then the first spray is triggered (Column 11, lines 36 – column 12, lines 1-10.
“repeat the generating step based on a desired number of repeat sequences to be performed.”
After each spray trigger has been produced the program determines if the correct NUMBER of SPRAYS has been triggered. IF so, the program loops back to its beginning and reads the BCD switch again (column 12, lines 3-21). Also see column 8, lines 19-28.
As per claim 26, Lair et al. further teaches, “The sequencer of claim 25, wherein the controlled electrical loads include a plurality of electronic switches and the output applied to the electronic switches causes the electronic switches to selectively activate and deactivate, and the processor is further programmed to:
determine whether an instruction to be executed is an ON command or an OFF command with respect to a selected electronic switch; and
if the instruction is determined to be an OFF command, then the selected electronic switch is identified and the selected electronic switch is deactivated.”
Lair et al. teaches each pulse produced by the sequence controller is about eight milliseconds long. The output is provided by an optically coupled, open collector NPN, transistor which sinks current to DC ground. It is normally “off” and switches “on” during each pulse interval (column 9, lines 1-5). Also see column 11, lines 42 – column 12, lines 1-21 and figure 2. The sequence controller is a self contained, micro-processor based unit which provide a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 2, lines 40-54). Figure 2 shows both a pan sensor output and a valve driver signal. Also see column 7, lines 45-60.
As per claim 27, Lair et al. further teaches, “The sequencer of claim 25, wherein the controlled electrical loads include a plurality of electronic switches and the output applied to the electronic switches causes the electronic switches to selectively activate and deactivate, and the processor is further programmed to:
determine whether the electronic switches are a coordinated set of electronic switches, and if so, then the coordinated set of electronic switches are selectively activated and deactivated in like manner.”
The sequence controller is a self contained, micro-processor based unit which provide a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 2, lines 40-54). Figure 2 shows both a pan sensor output and a valve driver signal. Also see column 7, lines 45-60.
As per claim 28, Lair et al. further teaches, “The sequencer of claim 25, wherein the controlled electrical loads include a plurality of electronic switches and the output applied to the electronic switches causes the electronic switches to selectively activate and deactivate, and the processor is further programmed to:
determine whether an instruction to be executed is a WAIT command with respect to a selected electronic switch; if the instruction is determined to be a WAIT command, then retrieving from memory a predetermined wait time to be executed.”
The sequence controller is a self contained, micro-processor based unit which provide a user programmable sequence of electronic pulses for the control or synchronization of valves, relays, solenoids, and timers (column 2, lines 40-54). Figure 2 shows both a pan sensor output and a valve driver signal. Also see column 7, lines 45-60.
A user can manually control a DELAY TIME parameter (column 8, lines 3-19). Also see column 11, lines 36-43. When the total delay time has been executed, the program checks the number of pulses and if its not zero then the first spray is triggered (Column 11, lines 36 – column 12, lines 1-10).
As per claim 29, Lair et al. further teaches, “The sequencer of claim 28, wherein the processor is further programmed to:
execute the wait command in accordance with the predetermined wait time, and”
A user can manually control a DELAY TIME parameter (column 8, lines 3-19). Also see column 11, lines 36-43. When the total delay time has been executed, the program checks the number of pulses and if its not zero then the first spray is triggered (Column 11, lines 36 – column 12, lines 1-10).
“then setting the run flag to FALSE to thereby cease further operation.”
Lair et al. teaches the sequence controller allows the operation to manually trigger a pulse sequence, stop a pulse sequence which is in progress, bypass the controller with the sensor signal, or turn off the controller output (column 8, lines 27-53). Also see column 8, lines 37-47.
Noritaka teaches a sequence controller comprising a RUN flag that controls the execution/stopping of a sequence table (page 7). Also see page 9. The examiner states that if the execution is stopped then it would be inherent for the run flag to be false.
As per claim 30, Lair et al. further teaches, “The sequencer of claim 25, wherein the controlled electrical loads include a plurality of electronic switches and the output applied to the electronic switches causes the electronic switches to selectively activate and deactivate, and the processor is further programmed to:
determine whether an instruction to be executed is a repeat command with respect to a selected electronic switch;
if the instruction is determined to be a repeat command, then the repeat command is executed in accordance with a loop count variable maintained by the processor.”
After each spray trigger has been produced the program determines if the correct NUMBER of SPRAYS has been triggered. IF so, the program loops back to its beginning and reads the BCD switch again (column 12, lines 3-21). Also see column 8, lines 19-28.
Response to Arguments
Applicant's arguments filed 4/2/2026 have been fully considered but they moot due to amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK A GOORAY whose telephone number is (571)270-7805. The examiner can normally be reached Monday - Friday 10:00am - 6:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock can be reached at 571-272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARK A GOORAY/ Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/ Supervisory Patent Examiner, Art Unit 2199
