DETAILED ACTION
This office action is in response to amendment filed on 2/18/2026.
Claims 1, 12 and 17 are amended.
Claims 1 – 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 8, 11 – 14 and 16 – 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breternitz et al (US 20120291040, hereinafter Breternitz), in view of Hum et al (US 20090222654, hereinafter Hum), and further in view of Watanabe et al (US 20140040532, hereinafter Watanabe).
As per claim 1, Breternitz discloses: A storage device comprising: a circuit board; a memory disposed on the circuit board and including a plurality of memory cells configured to store data;
and an internal processor coupled to be in communication with the memory, the internal processor being located inside or adjacent to the memory and configured to perform an operation on the data stored in the memory, (Breternitz figure 1, general-purpose processor core 112 (mapped to the claimed external processor), shared cache memory subsystem 118, and SIMD/GPU core 172 (mapped to the claimed internal processor).)
wherein the command is extracted based on an operational intensity of the operation to be performed in response to the command, in a process in which a compiler generates an instruction according to a program executed by an external processor that is disposed outside the storage device. (Breternitz figure 8 and [0062]: “In block 802, a software program or subroutine may be located and analyzed… In one embodiment, the source code is statically compiled.”; [0063]: “In block 804, the compiler may read one or more instructions of the kernel and analyze them.”; [0064]: “If a memory access instruction is identified (conditional block 810), then in block 812, a corresponding access pattern may be determined. Memory accesses may be sequential, stride, direct, indirect, gather in groups, scattered and so forth.”; [0069]: “If a relatively high number of memory access instructions perform accesses of memory locations in a sequential manner or a stride manner, then the corresponding work units may be scheduled on the SIMD core 172. If a relatively high number of memory access instructions perform accesses of memory locations in a scattered or indirect manner, then the corresponding work units may be scheduled on the general-purpose core 112. At run time the OpenCL.TM. compiler may generate multiple versions of kernels for each OpenCL.TM. device type, such as the general-purpose core 112 and the SIMD core 172. In one example, the scheduler 424 may schedule the first 256 work units of a given kernel to execute on the SIMD core 172.”. Examiner notes that the high number of memory access in sequential manner is mapped to the claimed operational intensity, also the high number of memory access in scattered manner can also be mapped to the claimed operational intensity.)
Breternitz did not explicitly disclose:
wherein the internal processor performs the operation upon receipt of a command from an external device located outside the storage device;
However, Hum teaches:
wherein the internal processor performs the operation upon receipt of a command from an external device; (Hum [0028]: “At operation 505, an event (e.g., yield, exception, etc.) occurs in the main core to cause state from the core to be saved and copied to a lower power/performance core. In one embodiment, a handler program is invoked in response to the event to cause the main core state to be transferred from the main core to a lower power/performance core. At operation 510, the transferred thread/process/task is restarted or resumed on the lower power/performance core.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hum into that of Breternitz in order to have the internal processor performs the operation upon receipt of a command from an external device. Hum has shown that the claimed limitation is merely a commonly known technique for processing optimization of parallel hardware, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
Watanabe teaches:
wherein the external device is located outside the storage device; (Watanabe figure 1: external processor device 102.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Watanabe into that of Breternitz and Hum in order to have the external device is located outside the storage device. Although Hum and Breternitz and Hum used preferred embodiments of moving tasks between big little core environment to optimize the performance of the task and the processing efficiency. However, oner of ordinary skill in the art can easily be applied to other form of heterogeneous processing architectures as well to enjoy the improved execution efficiency of the system, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results of improved processing efficiency in heterogeneous processing environment and is therefore rejected under 35 USC 103.
As per claim 2, the combination of Breternitz, Hum and Watanabe further teach:
The storage device according to claim 1, wherein the compiler that runs on the external processor includes a command extraction function configured to distinguish a command to be performed by the internal processor from a command to be performed by the external processor depending on the operational intensity of the operation to be performed in response to the command. (Breternitz [0069]: “If a relatively high number of memory access instructions perform accesses of memory locations in a sequential manner or a stride manner, then the corresponding work units may be scheduled on the SIMD core 172. If a relatively high number of memory access instructions perform accesses of memory locations in a scattered or indirect manner, then the corresponding work units may be scheduled on the general-purpose core 112. At run time the OpenCL.TM. compiler may generate multiple versions of kernels for each OpenCL.TM. device type, such as the general-purpose core 112 and the SIMD core 172”.)
As per claim 3, the combination of Breternitz, Hum and Watanabe further teach:
The storage device according to claim 2, wherein the command to be performed by the internal processor and the command to be performed by the external processor are generated through a same application framework or generated using a same library. (Breternitz [0069]: “If a relatively high number of memory access instructions perform accesses of memory locations in a sequential manner or a stride manner, then the corresponding work units may be scheduled on the SIMD core 172. If a relatively high number of memory access instructions perform accesses of memory locations in a scattered or indirect manner, then the corresponding work units may be scheduled on the general-purpose core 112. At run time the OpenCL.TM. compiler may generate multiple versions of kernels for each OpenCL.TM. device type, such as the general-purpose core 112 and the SIMD core 172”; [0062]: DLL.)
As per claim 4, the combination of Breternitz, Hum and Watanabe further teach:
The storage device according to claim 1, wherein, in a case that the operational intensity of the operation to be performed in response to the command is less than a preset reference value, the command is transmitted to the internal processor, and the operation is performed by the internal processor. (Breternitz [0069]: “If a relatively high number of memory access instructions perform accesses of memory locations in a sequential manner or a stride manner, then the corresponding work units may be scheduled on the SIMD core 172. If a relatively high number of memory access instructions perform accesses of memory locations in a scattered or indirect manner, then the corresponding work units may be scheduled on the general-purpose core 112. At run time the OpenCL.TM”.)
As per claim 5, the combination of Breternitz, Hum and Watanabe further teach:
The storage device according to claim 1, wherein, in a case that the operational intensity of the operation to be performed in response to the command is equal to or greater than a preset reference value, the command is not transmitted to the internal processor. (Breternitz [0069] and [0075])
As per claim 6, the combination of Breternitz, Hum and Watanabe further teach:
The storage device according to claim 1, wherein, in a case that the operational intensity of the operation to be performed according to the command is equal to or greater than a preset reference value, the operation is performed by the external processor. (Breternitz [0069] and [0075])
As per claim 7, the combination of Breternitz, Hum and Watanabe further teach:
The storage device according to claim 1, wherein the operational intensity of the operation to be performed by the internal processor in response to the command is less than the operational intensity of the operation according to a command to be performed by the external processor. (Breternitz [0069] and [0075])
As per claim 8, the combination of Breternitz, Hum and Watanabe further teach:
The storage device according to claim 1, wherein the operational intensity of the operation to be performed in response to the command is compared with a reference value to determine whether to perform the operation by the internal processor, wherein the reference value is adjusted based on a total amount of operations to be performed by the internal processor. (Breternitz [0072] – [0075])
As per claim 11, the combination of Breternitz, Hum and Watanabe further teach:
The storage device according to claim 1, the internal processor is separate from the memory and is on the circuit board that is shared with the memory. (Breternitz figure 1.)
As per claim 12, Breternitz discloses: An electronic device comprising:
a first processor configured to perform a first operation on data stored in a memory; and a second processor configured to perform a second operation on data stored in the memory, the second processor being located inside or adjacent to the memory, (Breternitz figure 1, general-purpose processor core 112 (mapped to the claimed external processor), shared cache memory subsystem 118, and SIMD/GPU core 172 (mapped to the claimed internal processor).)
wherein the command is extracted based on an operational intensity of an operation to be performed in response to the command, in a process in which a compiler generates an instruction according to a program executed by the first processor. (Breternitz figure 8 and [0062]: “In block 802, a software program or subroutine may be located and analyzed… In one embodiment, the source code is statically compiled.”; [0063]: “In block 804, the compiler may read one or more instructions of the kernel and analyze them.”; [0064]: “If a memory access instruction is identified (conditional block 810), then in block 812, a corresponding access pattern may be determined. Memory accesses may be sequential, stride, direct, indirect, gather in groups, scattered and so forth.”; [0069]: “If a relatively high number of memory access instructions perform accesses of memory locations in a sequential manner or a stride manner, then the corresponding work units may be scheduled on the SIMD core 172. If a relatively high number of memory access instructions perform accesses of memory locations in a scattered or indirect manner, then the corresponding work units may be scheduled on the general-purpose core 112. At run time the OpenCL.TM. compiler may generate multiple versions of kernels for each OpenCL.TM. device type, such as the general-purpose core 112 and the SIMD core 172. In one example, the scheduler 424 may schedule the first 256 work units of a given kernel to execute on the SIMD core 172.”. Examiner notes that the high number of memory access in sequential manner is mapped to the claimed operational intensity, also the high number of memory access in scattered manner can also be mapped to the claimed operational intensity.)
Breternitz did not explicitly disclose:
wherein the second processor performs the second operation in response to a command received from the first processor;
wherein the first device is located outside the memory;
However, Hum teaches:
wherein the internal processor performs the second operation in response to a command received from the first processor; (Hum [0028]: “At operation 505, an event (e.g., yield, exception, etc.) occurs in the main core to cause state from the core to be saved and copied to a lower power/performance core. In one embodiment, a handler program is invoked in response to the event to cause the main core state to be transferred from the main core to a lower power/performance core. At operation 510, the transferred thread/process/task is restarted or resumed on the lower power/performance core.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hum into that of Breternitz in order to have the internal processor performs the operation upon receipt of a command from an external device. Hum has shown that the claimed limitation is merely a commonly known technique for processing optimization of parallel hardware, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
Watanabe teaches:
wherein the first device is located outside the memory; (Watanabe figure 1: external processor device 102.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Watanabe into that of Breternitz and Hum in order to have the external device is located outside the storage device. Although Hum and Breternitz and Hum used preferred embodiments of moving tasks between big little core environment to optimize the performance of the task and the processing efficiency. However, oner of ordinary skill in the art can easily be applied to other form of heterogeneous processing architectures as well to enjoy the improved execution efficiency of the system, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results of improved processing efficiency in heterogeneous processing environment and is therefore rejected under 35 USC 103.
As per claim 13, the combination of Breternitz, Hum and Watanabe further teach:
The electronic device according to claim 12, wherein the compiler includes a command extraction function configured to compare the operational intensity of the operation to be performed in response to the command with a preset reference value and transmits the command to the first processor or the second processor based on a comparison result between the operational intensity of the operation to be performed in response to the command and the preset reference value. (Breternitz [0069] and [0075])
As per claim 14, the combination of Breternitz, Hum and Watanabe further teach:
The electronic device according to claim 12, wherein a command for an operation to be performed by the first processor and a command for an operation to be performed by the second processor are generated using a same application framework and library. (Breternitz [0069] and [0075])
As per claim 16, the combination of Breternitz, Hum and Watanabe further teach:
The electronic device according to claim 12, wherein a length of a communication channel between the second processor and the memory is shorter than a length of a communication channel between the first processor and the memory. (Breternitz figure 1.)
As per claim 17, Breternitz discloses: A method for operating an electronic device, comprising:
comparing an operational intensity of an operation to be performed in response to a command with a preset reference value, in a process in which a compiler generates an instruction according to the program; and in a case that the operational intensity of the operation to be performed in response to the command is less than the preset reference value, processing the command by a second processor located outside the first processor and located inside or adjacent to the memory, or in a case that the operational intensity of the operation to be performed in response to the command is equal to or greater than the preset reference value, processing the command by the first processor. (Breternitz figure 8 and [0062]: “In block 802, a software program or subroutine may be located and analyzed… In one embodiment, the source code is statically compiled.”; [0063]: “In block 804, the compiler may read one or more instructions of the kernel and analyze them.”; [0064]: “If a memory access instruction is identified (conditional block 810), then in block 812, a corresponding access pattern may be determined. Memory accesses may be sequential, stride, direct, indirect, gather in groups, scattered and so forth.”; [0069]: “If a relatively high number of memory access instructions perform accesses of memory locations in a sequential manner or a stride manner, then the corresponding work units may be scheduled on the SIMD core 172. If a relatively high number of memory access instructions perform accesses of memory locations in a scattered or indirect manner, then the corresponding work units may be scheduled on the general-purpose core 112. At run time the OpenCL.TM. compiler may generate multiple versions of kernels for each OpenCL.TM. device type, such as the general-purpose core 112 and the SIMD core 172. In one example, the scheduler 424 may schedule the first 256 work units of a given kernel to execute on the SIMD core 172.”. Examiner notes that the high number of memory access in sequential manner is mapped to the claimed operational intensity, also the high number of memory access in scattered manner can also be mapped to the claimed operational intensity, SIMD core 172 is mapped to the claimed second processor, and general-purpose core is mapped to the claimed first processor.)
Breternitz did not explicitly disclose:
executing a program by a first processor;
wherein the first device is located outside the memory;
However, Hum teaches:
executing a program by a first processor; (Hum [0028]: “At operation 505, an event (e.g., yield, exception, etc.) occurs in the main core to cause state from the core to be saved and copied to a lower power/performance core. In one embodiment, a handler program is invoked in response to the event to cause the main core state to be transferred from the main core to a lower power/performance core. At operation 510, the transferred thread/process/task is restarted or resumed on the lower power/performance core.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hum into that of Breternitz in order to have the internal processor performs the operation upon receipt of a command from an external device. Hum has shown that the claimed limitation is merely a commonly known technique for processing optimization of parallel hardware, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
Watanabe teaches:
wherein the first device is located outside the memory; (Watanabe figure 1: external processor device 102.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Watanabe into that of Breternitz and Hum in order to have the external device is located outside the storage device. Although Hum and Breternitz and Hum used preferred embodiments of moving tasks between big little core environment to optimize the performance of the task and the processing efficiency. However, oner of ordinary skill in the art can easily be applied to other form of heterogeneous processing architectures as well to enjoy the improved execution efficiency of the system, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results of improved processing efficiency in heterogeneous processing environment and is therefore rejected under 35 USC 103.
As per claim 18, the combination of Breternitz, Hum and Watanabe further teach:
The method according to claim 17, wherein a command to be processed by the first processor and a command to be processed by the second processor are generated using a same application framework and library. (Breternitz [0069])
As per claim 19, the combination of Breternitz, Hum and Watanabe further teach:
The method according to claim 17, wherein the first processor and the second processor are configured to perform operations on data stored in a memory, and the second processor is located closer to the memory than the first processor. (Breternitz figure 1.)
As per claim 20, the combination of Breternitz, Hum and Watanabe further teach:
The method according to claim 17, wherein a length of a communication channel between the second processor and a memory is shorter than a length of a communication channel between the first processor and the memory. (Breternitz figure 1.)
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breternitz, Hum and Watanabe, and further in view of Bernat et al (US 20200073464, hereinafter Bernat).
As per claim 9, the combination of Breternitz, Hum and Watanabe did not teach:
The storage device according to claim 8, wherein the reference value is adjusted to be inversely proportional to a total amount of operations to be performed by the internal processor.
However, Bernat teaches:
The storage device according to claim 8, wherein the reference value is adjusted to be inversely proportional to a total amount of operations to be performed by the internal processor. (Bernat [0081])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Bernat into that of Breternitz, Hum and Watanabe in order to have the reference value is adjusted to be inversely proportional to a total amount of operations to be performed by the internal processor. Bernat has shown that the claimed limitation is merely commonly known methods for determining the right offload threshold in real time, applicant have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
Claim(s) 10 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breternitz, Hum and Watanabe, and further in view of Kannan et al (US 20200054111, hereinafter Kannan).
As per claim 10, the combination of Breternitz, Hum and Watanabe did not teach:
The storage device according to claim 1, the internal processor is located inside the memory.
However, Kannan teaches:
The storage device according to claim 1, the internal processor is located inside the memory. (Kannan figure 1: controllers within storage array.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kannan into that of Breternitz, Hum and Watanabe in order to have the internal processor is located inside the memory. Breternitz has taught the internal core being a SIMD core, however, one of ordinary skill in the art can easily recognize that other types of specialized processor, such as memory controller can be used here as well. Thus applicant have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
As per claim 15, the combination of Breternitz, Hum and Watanabe did not teach:
The electronic device according to claim 12, wherein the second processor is located closer to the memory than the first processor.
However, Kannan teaches:
The electronic device according to claim 12, wherein the second processor is located closer to the memory than the first processor. (Kannan figure 1: controllers within storage array.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kannan into that of Breternitz, Hum and Watanabe in order to have the internal processor is located inside the memory. Breternitz has taught the internal core being a SIMD core, however, one of ordinary skill in the art can easily recognize that other types of specialized processor, such as memory controller can be used here as well. Thus applicant have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 – 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM.
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/CHARLES M SWIFT/Primary Examiner, Art Unit 2196