Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “PROCESSING CIRCUIT FOR SEQUENTIALLY CALCULATING DATA OVER MULTIPLE CALCULATION STAGES”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
2. Claims 1, 2, and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
3. Per Claims 1, 2, and 9, each of these claims comprises the limitation, “a calculation circuit that is sequentially connected,”, without including limitations describing what the calculation circuit is sequentially connected to. According to the Specification and Drawings, it appears that the invention comprises a plurality of calculation circuits (see Fig. 2, calculation circuits 6-1, 6-2, and 6-3), however, only a single calculation circuit is ever claimed.
Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
- Therefore, for examination purposes, the “sequentially connected” limitation is not given patentable weight until a plurality of calculation circuits are introduced into the claim for the calculation circuit to be sequentially connected thereto.
4. Claims 1 (and Claim 9) further recites “the calculation circuit of a preceding stage” and “the calculation circuit of a succeeding stage”. There is insufficient antecedent basis for each of these calculation circuits since no “stages” were previously introduced in the claim. The claim introduces a “calculation circuit” in line 2, however, it is unclear if the following recitations to “the calculation circuit” are to represent another instance of the initially introduced “calculation circuit”. The “stages” need to be properly introduced in the claim with respect to how they are to be interconnected because as recited, it is unclear if there are three “stages” with an unintroduced “second stage” representing a middle stage between the “preceding stage” and the “succeeding stage”, or if two stages exist.
- For examination purposes, the claimed “stages” will be interpreted as there being at least two calculation circuit stages.
5. Claim 1 (and Claims 2 and 9) further recites, see lines 10-11, “the calculation circuit of the succeeding stage performs the predetermined calculation”. It is unclear if this predetermined calculation is the same calculation as the predetermined calculation introduced in line 5 as the claims do not properly distinguish the calculation circuits, predetermined calculations, or the “stages”.
6. Claim 1 (and Claim 9) further comprises a plurality of different recitations of “data” that make each recitation indistinguishable from the other, see at least: line 3, “a plurality of pieces of data for each piece of data”, line 10, “on any piece of data”, and lines 11-12, “another piece of data different from the data”.
7. Claim 2 introduces “a data holding unit” in lines 2-3 and then further recites, “the data holding unit of the same number as the number of pieces of data input simultaneously” and “other calculation circuits each include one data holding unit”. It is unclear how many “data holding units” are to be represented within the claim. Figure 5 of the Drawings discloses two data holding units 4-1A and 4-1B within calculation circuit 6-1, and a single data holding unit 4-2 within calculation circuit 6-2. However, this representation is not properly claimed as claim 2 is currently recited because the initially introduced calculation circuit can’t simultaneously comprise a data holding unit and then also comprise multiple data holding units. The Examiner suggests amending lines 2-3 to read “the calculation circuit including at least one data holding unit”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1, 2, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harada et al. U.S. PGPUB No. 2010/0245914.
9. Per Claim 1, Harada discloses:
a processing circuit (data processing device 1) comprising:
a calculation circuit that is sequentially connected (Note: The calculation circuit is described in the Specification and Drawings using numeral 6, which is a dashed line encompassing both the data holding unit 4 and the data calculation unit 5. The calculation circuit is not presented as a singular “circuit” and therefore will be interpreted as a collection of components. Fig. 4 (reproduced below); Collection of RAM 3 and Image processing circuit 16.),
the calculation circuit including a plurality of data holding units that hold a plurality of pieces of data for each piece of data (Fig. 4; RAM 3 comprises first/second band memories 3a1-2 for image data and first/second band memories 3b1-2 for attribute data.)
and one data calculation unit that is common to each of the data holding units and performs a predetermined calculation on each piece of data held in the data holding unit (Paragraph 50, Fig. 4; image processing circuit 16),
wherein a calculation result of the calculation circuit of a preceding stage is input to the data holding unit in the calculation circuit of a succeeding stage associated with data which is a calculation target in the calculation circuit of the preceding stage (Paragraphs 50 and 67, Figure 4; Image processing circuit 16 executes predetermined processing on the band data and stores the processed band data into the RAM 3 of a subsequent stage.),
and while the calculation circuit of the preceding stage performs the predetermined calculation on any piece of data, the calculation circuit of the succeeding stage performs the predetermined calculation on a calculation result obtained from another piece of data different from the data, which is the calculation target in the calculation circuit of the preceding stage, to perform the predetermined calculation on each piece of data (Paragraph 52; SRLE codec 18 reads the attribute band data stored in RAM 3 memories 3c1-2 and 3d1-2, compresses the band data by encoding the band data in SRLE format, and stores the band data into the HDD 4. Fig. 5 Also discloses how the data is sequentially passed through the memories and processing circuits.).
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10. Per Claim 2, Harada discloses:
a processing circuit (data processing device 1) comprising:
a calculation circuit that is sequentially connected (Note: The calculation circuit is described in the Specification and Drawings using numeral 6, which is a dashed line encompassing both the data holding unit 4 and the data calculation unit 5. The calculation circuit is not presented as a singular “circuit” and therefore will be interpreted as a collection of components. Fig. 4 (reproduced below); Collection of RAM 3 and Image processing circuit 16.),
the calculation circuit including a data holding unit that holds data (Fig. 4; RAM 3) and a data calculation unit that performs a predetermined calculation on the data held in the data holding unit (Paragraph 50, Fig. 4; image processing circuit 16),
wherein the calculation circuit of a first stage to which data is first input includes the data holding unit of the same number as the number of pieces of data input simultaneously and other calculation circuits each include one data holding unit (See above 112(b) rejection as clarification is required with respect to the “data holding unit”. Figure 4; RAM 3 can be interpreted as a data holding unit individually or each of the memories 3a1-2, 3b1-2, 3c1-2, and 3d1-2 can be considered data holding units.),
and each of the calculation circuits performs processing of taking out, before next data is input to the data holding unit, the data held in the data holding unit, performing the predetermined calculation on the taken out data, and storing a calculation result in the data holding unit of the calculation circuit of a succeeding stage (Paragraphs 50 and 67, Figure 4; Image processing circuit 16 executes predetermined processing on the band data and stores the processed band data into the RAM 3 of a subsequent stage. Paragraph 52; SRLE codec 18 reads the attribute band data stored in RAM 3 memories 3c1-2 and 3d1-2, compresses the band data by encoding the band data in SRLE format, and stores the band data into the HDD 4. Fig. 5 Also discloses how the data is sequentially passed through the memories and processing circuits.).
11. Per Claim 9, please refer to the above rejection of claim 1 as the limitations are substantially similar and the mapping of the limitations to Harada are equally applicable. Additionally, Harada teaches a non-transitory computer readable medium embodiment (Paragraphs 28 and 38; Non-transitory storage device 8 stores a program, which when executed by main controller 2 performs that operations of claim 9.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
12. Claims 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Harada et al. U.S. PGPUB No. 2010/0245914 in view of Sasaki, U.S. PGPUB No. 2013/0039602.
13. Per Claims 3 and 4, Harada discloses (see Fig. 5) performing operations on data at various time stages, but does not specifically discuss a clock.
However, Sasaki similarly teaches an image processing device 100 that supports double sided copying/scanning (Paragraphs 27-29) and further teaches, according to claim 1, wherein the calculation circuit is a synchronization circuit that synchronizes with a clock, and the calculation circuit is divided such that the calculation in the data calculation unit ends within one clock (Paragraphs 35-39, Figures 2, 9, and 10; Image processing unit 1060 similarly comprises data holding unit(s) 1061a-b and “scan_clk” denotes a transfer clock for the front side and back side data. “Specifically, the access control unit 1061c writes the image data of one line "scan_data" to the LINE_FIFO.sub.A 1061a or the LINE_FIFO.sub.B 1061b in synchronization with the transfer clock "scan_clk", by using the fall of the line data synchronous signal "slsync_n" transmitted by the image/buffer controller 1040 as a trigger.”).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the clock-sourced synchronization techniques of Sasaki within the multi-band (multi-stage) data processing device of Harada because it improves data transfer efficiency in the transmission of image data when the images accumulated in a memory are subjected to image processing prior to storage/transmission (Sasaki, Paragraph 73).
14. Per Claims 5 and 6, similar to claims 3 and 4, Harada does not specifically teach the clock limitations.
However, Sasaki teaches wherein each piece of data is input to the data holding unit of the calculation circuit of a/the first stage to which data is first input, at the same timing in synchronization with the clock (Figures 3 and 10, Paragraphs 35-39; During period A, the pull of the slsync_n signal low triggers the writing of scan data into the first line_fifo A data holding unit.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the clock-sourced synchronization techniques of Sasaki within the multi-band (multi-stage) data processing device of Harada because it improves data transfer efficiency in the transmission of image data when the images accumulated in a memory are subjected to image processing prior to storage/transmission (Sasaki, Paragraph 73).
15. Per Claims 7 and 8, similar to claims 3-6, Harada does not specifically teach the clock limitations.
However, Sasaki teaches wherein the number of pieces of data is limited to the number of clocks or less, which corresponds to an input interval of the data input to the calculation circuit of a first stage (Figures 3 and 10, Paragraphs 35-39; During period A, the pull of the slsync_n signal low triggers the writing of scan data into the first line_fifo A data holding unit. One FIFO buffer is written to per the one slsync_n signal.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the clock-sourced synchronization techniques of Sasaki within the multi-band (multi-stage) data processing device of Harada because it improves data transfer efficiency in the transmission of image data when the images accumulated in a memory are subjected to image processing prior to storage/transmission (Sasaki, Paragraph 73).
Prior Art
16. The prior art made of record but not relied upon in the Examiner’s rejections is provided below along with the reasoning for considering it pertinent to the applicant’s disclosure.
U.S. PGPUB No. 2002/0041401 teaches ping-pong buffers 255/257 for receiving CCD/CIS data (Fig. 2).
U.S. PGPUB No. 2016/0052317 is from a common Assignee and field of endeavor and teaches a double-sided printing method and apparatus. Figure 12 teaches a sequential path for data to traverse through different processing sections.
U.S. Patent No. 8,792,144 teaches a scanner performing two-sided reading of a document using a CCD 201 and CIS 202 and featuring multiple stages of processing for the image data (Fig. 3 and 7).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889 - (Direct Fax: 571-273-0889). The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175