Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Response to Arguments
Applicant’s amendment to the title has overcome the previous Specification objection.
Applicant’s amendment to the claims has overcome the previous 112(b) rejection.
Applicant's arguments with respect to claims 1 and 9 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Each of claims 3-8 recite “the calculation circuit”. However, independent claims 1 and 2 have been amended to recite “a plurality of calculation circuits”. Therefore, it is unclear which “calculation circuit” these claims are referring to. For examination purposes, the Examiner will interpret “the calculation circuit” to represent a single calculation circuit of one stage of the multi-stage pipeline process.
Claims 5-8 inherit the indefinite subject matter of claims 3 and 4 respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sarusi, U.S. Patent No. 10,680,977.
Per Claim 1, Sarusi discloses:
a processing circuit (Column 3 lines 40-55 and Column 5 lines 4-5; “multi-stage pipeline 200 in an example network processor”; Figure 1, provided below) comprising:
a plurality of calculation circuits that are sequentially connected to form a plurality of stages including a preceding stage and a succeeding stage, wherein each of the calculation circuits including a plurality of data holding units that respectively hold a plurality of pieces of data including a first piece of data and a second piece of data (Col. 3 lines 40-55 and Column 5 lines 4-47, Figures 1 and 2; Each of stages 0-5 (numerals 110-160 and 210-260) represent “calculation circuits” as they perform a specific operation/function on the data received. “Each stage includes a buffer 112-162 (not shown in Fig. 2) to temporarily store data passed from the previous stage.” Buffers inherently comprise a “plurality of data holding units” referred to as registers or cells for storing data.),
and one calculation unit that is common to each of the data holding units and performs a predetermined calculation on each piece of data held in each of the data holding units (Col. 5 lines 14-47 describe the various calculations/operations performed at each stage of the pipeline.),
wherein the plurality of calculation circuits includes a first calculation circuit corresponding to the preceding stage that performs a first predetermined calculation on each piece of data, and a second calculation circuit corresponding to the succeeding stage that performs a second predetermined calculation on each piece of data (See Figures 1 and 2 as any two stages can be considered the preceding and succeeding stages.),
wherein a calculation result obtained by performing the first predetermined calculation on the first piece of data of the first calculation circuit of the preceding stage is input to the data holding unit in the second calculation circuit of the succeeding stage associated with the first piece of data which is a calculation target in the first calculation circuit of the preceding stage (Col. 5 lines 10-13; “Each stage includes a buffer (not shown in Fig. 2) to temporarily store data passed from the previous stage.”);
and while the first calculation circuit of the preceding stage performs the first predetermined calculation on the second piece of data, the second calculation circuit of the succeeding stage performs the second predetermined calculation on the calculation result obtained from the first piece of data different from the second piece of data (Col. 3 lines 10-22; “In a processing system with a multi-stage pipeline architecture, simultaneous execution of more than one instruction or operation may take place. Each stage of the pipeline may perform different operations on a set of data, and the multiple stages may, in combination, perform all desired operations on the set of data (e.g., a network transport unit, such as a network packet, a frame, a message, or an encapsulated segment of data). Thus, each stage of the pipeline may operate sequentially on a same set of data, and may operate concurrently on different sets of data in the pipeline, rather than waiting for the processing of one set of data to complete before starting to process a different set of data.” Note on Claim Interpretation: The first piece of data and second piece of data are not required to be present in their respective data holding units of the first calculation circuit (i.e. the claimed preceding stage calculation circuit) at the same time. The claim only requires that each calculation circuit includes data holding units that hold a first piece and a second piece of data. The respective pieces of data can be written to their respective data holding units at different times, i.e. different cycles of the pipeline processing.).
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Per Claim 3, Sarusi discloses the processing circuit according to claim 1, wherein the calculation circuit is a synchronization circuit that synchronizes with a clock, and the calculation circuit is divided such that the calculation in the data calculation unit ends within one clock (Column 8 lines 61-65; “FIG. 4 illustrates an example processing system 400 using a dual-path synchronous pipeline architecture, according to certain embodiments. In processing system 400, all circuits may operate based on a common reference clock and thus are synchronized.” Column 3 lines 56-63; “In processing system 100 shown in FIG. 1, all data received at the input end of the pipeline may be propagated through the pipeline. In one example, the data may be a network packet that may include a payload X and a header Z. In order to transport the data between stages in a short period of time (e.g., one or more clock cycles), a bus 114 with a high aggregated bandwidth may be used to transfer the buffered data in buffer 112 to stage 1 (120).”).
Per Claim 9, please refer to the above rejection of claim 1 as the limitations are substantially similar and the mapping of the limitations to Sarusi are equally applicable. Additionally, Sarusi teaches a non-transitory computer readable medium embodiment (Column 21, lines 49-61).
Allowable Subject Matter
Claim 2 is allowed.
Claims 4, 6, and 8 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112, 2nd paragraph, set forth in this Office action.
Claim 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112, 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim (claim 1) and any intervening claims (claim 3).
- The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, Sarusi is considered to be the closest related prior art (see the rejection of claim 1 for details) but no combination of Sarusi and the prior art specifically teaches the same number of data holding units in the first calculation circuit as the number of pieces of data input simultaneously while the other calculation circuits each include only one data holding unit, when considered in combination with the other limitations of the claim. Sarusi discloses a buffer within each stage of the pipeline process (see Figure 1 included above) and does not teach or suggest there being differing numbers of data holding units between different stages within the pipeline process as claimed.
With respect to claim 5, Sarusi does not teach or suggest writing both of the first and second pieces of data into the data holding unit of a first stage calculation circuit at the same time in synchronization with a clock.
Claims 4, 6, and 8 inherit the allowable subject matter of claim 2.
Claim 7 inherit the allowable subject matter of claim 5.
- Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889. The examiner can normally be reached on M-F: 8-4:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175
Prosecution Insights