DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-10 in the reply filed on October 14, 2025 is acknowledged.
Claim Objections
Claim 28 is objected to because of the following informalities: In claim 28, the examiner believes “and resistor” is supposed to be “and the resistor”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schat (U.S. Patent No. 10823781). Schat teaches a built-in self-tester (BIST) of a semiconductor device comprising: an input/output (I/O) circuit (440) including an output buffer (444) and an input buffer (446), an output of the output buffer being coupled at a I/O terminal to an input of the input buffer (see fig. 4A), the I/O terminal being configured to receive or provide an external I/O signal (inherent to I/O line, fig. 4A has I/O line);one or more resistive-network cell regions (448-450) arranged to affect a reference current received at the I/O terminal; and a switching arrangement (455/456) configured to selectively couple the one or more resistive-network cell regions alternatively to a first reference voltage (pull up voltage for 448 or pull down voltage for 450) during a first phase or a second reference voltage (0V output when pull up/down resistor is activated., see col. 11, lines 64 through col. 12, line 7.) during a second phase, the switching arrangement being further configured to determine electrostatic discharge (ESD) damage (col. 5, lines 24-25 and col. 14, lines 15-17 teach damage is due to ESD) included in the semiconductor device based on (1) phase (second phase) and (2) an output signal of the input buffer (ZI, see tables 1, 2 and 4). The claim language to metal-oxide-semiconductor (MOS) transistors is considered an intended use and is not being given patentable weight.
Regarding claim 6, Schat teaches operating a built-in self-tester (BIST) of a semiconductor device,the BIST including an input/output (I/O) circuit 441 and one or more resistive-network cell regions 448/450, the I/O circuit including an output buffer 444 and an input buffer 446, an output of the output buffer being coupled at a I/O terminal to an input of the input buffer (fig. 4A), the I/O terminal being configured to receive or provide an external I/O signal (inherent to I/O line, fig. 4A has I/O line), and the one or more resistive-network cell regions being arranged to affect a reference current received at the I/O terminal, and the method comprising: selectively coupling the one or more resistive-network cell regions alternatively to a first reference voltage during a first phase or a second reference voltage during a first second phase (col. 11, lines 65-67 “first charging the (parasitic) I/O capacitance by setting the driver 444 to 0, then charging it by activating the pull-up resistor 448”); and determining electrostatic discharge (ESD) damage (col. 5, lines 24-25 and col. 14, lines 15-17 teach damage is due to ESD) included in the semiconductor device based on (1) phase and (2) an output signal generated by the input buffer (ZI, see tables 1, 2 and 4). The claim language to metal-oxide-semiconductor (MOS) transistors is considered an intended use and is not being given patentable weight.
Allowable Subject Matter
Claims 2-5, 7-10, 21-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 28-30 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Motika (U.S. Publication No. 2021/0156911) teaches a built in self test which controls/observes logic network resistance to pseudo-random fault detection.
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/CHRISTOPHER E MAHONEY/Primary Examiner, Art Unit 2852