DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 7, and 15, teach the limitation “a memory structure including stored weights associated with a machine learning (ML) model,” it is unclear and indefinite what data is associated with the ml model and with what the association is.
Claims that depend on the above rejected claims are also rejected under 35 U.S.C. 112(b) or 35
U.S.C. 112 (pre-AIA ), second paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to
an abstract idea without significantly more.
With respect to claim 1, the limitations,
“and a classification engine to retrieve the stored weights from the memory structure and adjust the readings from the plurality of digital temperature sensors based on the weights and electrical parameters associated with the chip.”
are directed to abstract ideas and would fall within the “Mental Process” grouping of abstract
ideas. Adjusting readings from temperature sensors based on weights and electrical parameters can be done in the human mind using evaluation, judgment, and opinion. MPEP 2106.04 teaches “The courts consider a mental process (thinking) that "can be performed in the human mind, or by a human using a pen and paper" to be an abstract idea. CyberSource Corp. v. Retail Decisions, Inc., 654 F.3d 1366, 1372, 99 USPQ2d 1690, 1695 (Fed. Cir. 2011). As the Federal Circuit explained, "methods which can be performed mentally, or which are the equivalent of human mental work, are unpatentable abstract ideas the ‘basic tools of scientific and technological work’ that are open to all.’" 654 F.3d at 1371, 99 USPQ2d at 1694 (citing Gottschalk v. Benson, 409 U.S. 63, 175 USPQ 673 (1972)). See also Mayo Collaborative Servs. v. Prometheus Labs. Inc., 566 U.S. 66, 71, 101 USPQ2d 1961, 1965 (2012) ("‘[M]ental processes [] and abstract intellectual concepts are not patentable, as they are the basic tools of scientific and technological work’" (quoting Benson, 409 U.S. at 67, 175 USPQ at 675)); Parker v. Flook, 437 U.S. 584, 589, 198 USPQ 193, 197 (1978) (same). Accordingly, the "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions.”
This judicial exception is not integrated into a practical application. In particular, the claim
recites the additional elements –
“A computing system comprising: a network controller; and a chip comprising logic coupled to one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic including: a memory structure including stored weights associated with a machine learning (ML) model, a plurality of digital temperature sensors to generate readings,”
Examiner views these limitations amount to generally linking the use of the judicial exception to
a particular technological environment or field of use – see MPEP 2106.05(h).
As such Examiner does NOT view that the claims
-Improve the functioning of a computer, or to any other technology or technical field
-Apply the judicial exception with, or by use of, a particular machine - see MPEP 2106.05(b)
-Effect a transformation or reduction of a particular article to a different state or thing -see MPEP 2106.05(c)
-Apply or use the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception - see MPEP 2106.05(e) and Vanda Memo.
Moreover, Examiner views the claims to be merely generally linking the use of the judicial exception to a well-known computing system.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a computing system comprising: a network controller; and a chip comprising logic coupled to one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic including: a memory structure including stored weights associated with a machine learning (ML) model, a plurality of digital temperature sensors to generate readings,” amount to using a computer as a tool to perform an abstract idea and mere data gathering.
Examiner further notes that such additional elements are viewed to be well known routine and
conventional as evidenced by
De (US 20230153597 A1)
Diamant (US 12210940 B1)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. Considering the claim as a whole, one of ordinary skill in the art would
not know the practical application of the present invention since the claims do not apply or use the
judicial exception in some meaningful way. As currently claimed, Examiner views that the additional
elements do not apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit
on the judicial exception, because the claims fail to recite clearly how the judicial exception is applied in
a manner that does not monopolize the exception because the limitations regarding “a computing system comprising: a network controller; and a chip comprising logic coupled to one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic including: a memory structure including stored weights associated with a machine learning (ML) model, a plurality of digital temperature sensors to generate readings,” can be viewed as tying the claim to a computer system.
With respect to claim 7, the limitations,
“and a classification engine to retrieve the stored weights from the memory structure and adjust the readings from the plurality of digital temperature sensors based on the weights and electrical parameters associated with the chip.”
are directed to abstract ideas and would fall within the “Mental Process” grouping of abstract
ideas. Adjusting readings from temperature sensors based on weights and electrical parameters can be done in the human mind using evaluation, judgment, and opinion. MPEP 2106.04 teaches “The courts consider a mental process (thinking) that "can be performed in the human mind, or by a human using a pen and paper" to be an abstract idea. CyberSource Corp. v. Retail Decisions, Inc., 654 F.3d 1366, 1372, 99 USPQ2d 1690, 1695 (Fed. Cir. 2011). As the Federal Circuit explained, "methods which can be performed mentally, or which are the equivalent of human mental work, are unpatentable abstract ideas the ‘basic tools of scientific and technological work’ that are open to all.’" 654 F.3d at 1371, 99 USPQ2d at 1694 (citing Gottschalk v. Benson, 409 U.S. 63, 175 USPQ 673 (1972)). See also Mayo Collaborative Servs. v. Prometheus Labs. Inc., 566 U.S. 66, 71, 101 USPQ2d 1961, 1965 (2012) ("‘[M]ental processes [] and abstract intellectual concepts are not patentable, as they are the basic tools of scientific and technological work’" (quoting Benson, 409 U.S. at 67, 175 USPQ at 675)); Parker v. Flook, 437 U.S. 584, 589, 198 USPQ 193, 197 (1978) (same). Accordingly, the "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions.”
This judicial exception is not integrated into a practical application. In particular, the claim
recites the additional elements –
“A semiconductor apparatus comprising: one or more substrates; and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic including: a memory structure including stored weights associated with a machine learning (ML) model, a plurality of digital temperature sensors to generate readings,”
Examiner views these limitations amount to generally linking the use of the judicial exception to
a particular technological environment or field of use – see MPEP 2106.05(h).
As such Examiner does NOT view that the claims
-Improve the functioning of a computer, or to any other technology or technical field
-Apply the judicial exception with, or by use of, a particular machine - see MPEP 2106.05(b)
-Effect a transformation or reduction of a particular article to a different state or thing -see MPEP 2106.05(c)
-Apply or use the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception - see MPEP 2106.05(e) and Vanda Memo.
Moreover, Examiner views the claims to be merely generally linking the use of the judicial exception to a well-known computing system.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “A semiconductor apparatus comprising: one or more substrates; and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic including: a memory structure including stored weights associated with a machine learning (ML) model, a plurality of digital temperature sensors to generate readings,” amount to using a computer as a tool to perform an abstract idea and mere data gathering.
Examiner further notes that such additional elements are viewed to be well known routine and
conventional as evidenced by
De (US 20230153597 A1)
Diamant (US 12210940 B1)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. Considering the claim as a whole, one of ordinary skill in the art would
not know the practical application of the present invention since the claims do not apply or use the
judicial exception in some meaningful way. As currently claimed, Examiner views that the additional
elements do not apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit
on the judicial exception, because the claims fail to recite clearly how the judicial exception is applied in
a manner that does not monopolize the exception because the limitations regarding “A semiconductor apparatus comprising: one or more substrates; and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic including: a memory structure including stored weights associated with a machine learning (ML) model, a plurality of digital temperature sensors to generate readings,” can be viewed as tying the claim to a computer system.
With respect to claim 15, the limitations,
“A method comprising: adjusting, by the classification engine, the readings from the plurality of digital temperature sensors based on the weights and electrical parameters associated with the chip.”
are directed to abstract ideas and would fall within the “Mental Process” grouping of abstract
ideas. Adjusting readings from temperature sensors based on weights and electrical parameters can be done in the human mind using evaluation, judgment, and opinion. MPEP 2106.04 teaches “The courts consider a mental process (thinking) that "can be performed in the human mind, or by a human using a pen and paper" to be an abstract idea. CyberSource Corp. v. Retail Decisions, Inc., 654 F.3d 1366, 1372, 99 USPQ2d 1690, 1695 (Fed. Cir. 2011). As the Federal Circuit explained, "methods which can be performed mentally, or which are the equivalent of human mental work, are unpatentable abstract ideas the ‘basic tools of scientific and technological work’ that are open to all.’" 654 F.3d at 1371, 99 USPQ2d at 1694 (citing Gottschalk v. Benson, 409 U.S. 63, 175 USPQ 673 (1972)). See also Mayo Collaborative Servs. v. Prometheus Labs. Inc., 566 U.S. 66, 71, 101 USPQ2d 1961, 1965 (2012) ("‘[M]ental processes [] and abstract intellectual concepts are not patentable, as they are the basic tools of scientific and technological work’" (quoting Benson, 409 U.S. at 67, 175 USPQ at 675)); Parker v. Flook, 437 U.S. 584, 589, 198 USPQ 193, 197 (1978) (same). Accordingly, the "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions.”
This judicial exception is not integrated into a practical application. In particular, the claim
recites the additional elements –
“generating, by a plurality of digital temperature sensors in a chip, readings; retrieving, by a classification engine in the chip, stored weights associated with a machine learning (ML) model from a memory structure in the chip;”
Examiner views these limitations amount to generally linking the use of the judicial exception to
a particular technological environment or field of use – see MPEP 2106.05(h).
As such Examiner does NOT view that the claims
-Improve the functioning of a computer, or to any other technology or technical field
-Apply the judicial exception with, or by use of, a particular machine - see MPEP 2106.05(b)
-Effect a transformation or reduction of a particular article to a different state or thing -see MPEP 2106.05(c)
-Apply or use the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception - see MPEP 2106.05(e) and Vanda Memo.
Moreover, Examiner views the claims to be merely generally linking the use of the judicial exception to a well-known computing system.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “generating, by a plurality of digital temperature sensors in a chip, readings; retrieving, by a classification engine in the chip, stored weights associated with a machine learning (ML) model from a memory structure in the chip;” amount to using a computer as a tool to perform an abstract idea and mere data gathering.
Examiner further notes that such additional elements are viewed to be well known routine and
conventional as evidenced by
De (US 20230153597 A1)
Diamant (US 12210940 B1)
The claim does not include additional elements that are sufficient to amount to significantly
more than the judicial exception. Considering the claim as a whole, one of ordinary skill in the art would
not know the practical application of the present invention since the claims do not apply or use the
judicial exception in some meaningful way. As currently claimed, Examiner views that the additional
elements do not apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit
on the judicial exception, because the claims fail to recite clearly how the judicial exception is applied in
a manner that does not monopolize the exception because the limitations regarding “generating, by a plurality of digital temperature sensors in a chip, readings; retrieving, by a classification engine in the chip, stored weights associated with a machine learning (ML) model from a memory structure in the chip;” can be viewed as tying the claim to a computer system.
Dependent claims 2-6, 8-14, and 16-21 when analyzed as a whole are held to be patent ineligible under 35 U.S.C. 101 because the additional recited limitation(s) fail(s) to establish that the
claims are not directed to an abstract idea, as detailed below:
They amount to further limiting the well-known computing system with well-known components. This is further seen as adding insignificant extra-solution activity to the judicial exception - see MPEP 2106.05(g). There are no additional element(s) in the dependent claims that adds a meaningful limitation to the abstract idea to make the claim significantly more than the judicial exception (abstract idea).
Dependent claims 2-6, 8-14, and 16-21 further limit the abstract idea with an abstract idea
and thus, the claims are still directed to an abstract idea without significantly more.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7, 11, 13-15, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by De (US 20230153597 A1).
With respect to claim 7,
De teaches,
A semiconductor apparatus comprising: one or more substrates; and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic including: (See figures 2,3, and 4 silicon chips. Where the components on the chip are either configurable or have certain functionalities for example the memory.)
a memory structure including stored weights associated with a machine learning (ML) model, (Tuning memory 206, Abstract teaches “(c) a tuning memory embedded with a machine learning (ML) model of the analog circuit and (d) an artificial intelligence (AI) engine configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory.” Para. [0038] teaches “In some embodiments, the method includes providing a change control register configured to store the plurality of change control bits via connections to the plurality of tunable components.”)
a plurality of digital temperature sensors to generate readings, (Para. [0024] teaches “The Process, Voltage Temperature (PVT) characteristics monitor includes a plurality of PVT sensors. The tuning memory is embedded with a machine learning (ML) model of the analog circuit. The AI engine is configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory.”)
and a classification engine to retrieve the stored weights from the memory structure and adjust the readings from the plurality of digital temperature sensors based on the weights and electrical parameters associated with the chip. (Para. [0024] generate a plurality of change control bits from the predictions based on the ML model, where the plurality of change control bits activates one or more digital switches to retune the analog circuit. Para. [0072] teaches “An on-chip temperature sensor 414 provides the (T) in PVT by measuring the on-the-fly operating temperature that tunable analog circuit 406 is experiencing. The T-measurement is taken in by the inference calculating micro-computer 410. An executable AI-program 416 run by the inference calculating micro-computer 410 uses tuning memory 418 to calculate digital control bits from the PVT being measured on-the-fly. A digital change control register 420 holds these so the inference calculating micro-computer 410 can go back to sleep or do other tasks. Each digital control bit is connected to a tunable component 422, 424 within the tunable analog circuit 406.” Para. [0073] teaches “An ML model that was built, trained, and tested in circuit design simulations has been distilled into its essence, coded, and stored as tuning memory 418. Such machine learning model is used by the inference calculating micro-computer 410 to predict and generate the correct digital control bits predicted to be needed to put tunable analog circuit 406 back in-tune, given the instant on-the-fly PVT. The predicted necessary tuning that results is not tested on-the-fly as it was already tested in circuit design simulations for each possible PVT.”
With respect to claim 11,
De further teaches,
The computing system of claim 7, wherein the classification engine is further to: train the ML model to obtain the weights; and store the weights to the memory structure. (Para. [0015] teaches “But the development, training, and testing of respective ML models are done on the analog circuit design platforms based on the results of simulations of the analog circuits over the specified ranges in PVT values.” Para. [0030] teaches “the IC includes a change control register configured to store the plurality of change control bits through connections to the plurality of tunable components.” Para. [0034] teaches “the ML model is trained and tested with a plurality of results of a series of design simulations of the analog circuit, where the ML model is stored as a tuning model which represents a correlation between the signal inputs and an output target control variable based on which the AI engine calculates the plurality of analog circuit target control inferences and predictions.” Para. [0058] teaches “These relationships either in the form of equations or as regression tree (depending on the statistical process) in 110 are stored as ML tuning memory 122 on the chip 120.”)
With respect to claim 13,
De further teaches,
The semiconductor apparatus of claim 7, wherein the memory structure includes a read-only memory. (Para. [0066] teaches “The ML model could also be stored in a read-only or a writeable lookup table from which the AI engine calculates a plurality of analog circuit target control predictions and inferences.”)
With respect to claim 14,
De further teaches,
The semiconductor apparatus of claim 7, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates. (Para. [0076] teaches “The performance of the current reference depends on the characteristics and variations in its MOS transistors and a resistor R over PVT conditions. R was pinned as a tunable component 422, 424. Freq1 is the oscillation frequency of Process Monitor 1 which consists of inverters made from NMOS and PMOS transistors. The variations of Freq1 over PVT are dominated by the variations of the electrical characteristics of both NMOS and PMOS transistors. Freq2 is the oscillation frequency of Process Monitor 2 which consists of inverters made from NMOS, PMOS transistors and resistors.”)
With respect to claim 15,
De teaches,
A method comprising: generating, by a plurality of digital temperature sensors in a chip, readings; (Para. [0024] teaches “The Process, Voltage Temperature (PVT) characteristics monitor includes a plurality of PVT sensors. The tuning memory is embedded with a machine learning (ML) model of the analog circuit. The AI engine is configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory.”)
retrieving, by a classification engine in the chip, stored weights associated with a machine learning (ML) model from a memory structure in the chip; and adjusting, by the classification engine, the readings from the plurality of digital temperature sensors based on the weights and electrical parameters associated with the chip. (Para. [0024] generate a plurality of change control bits from the predictions based on the ML model, where the plurality of change control bits activates one or more digital switches to retune the analog circuit. Para. [0072] teaches “An on-chip temperature sensor 414 provides the (T) in PVT by measuring the on-the-fly operating temperature that tunable analog circuit 406 is experiencing. The T-measurement is taken in by the inference calculating micro-computer 410. An executable AI-program 416 run by the inference calculating micro-computer 410 uses tuning memory 418 to calculate digital control bits from the PVT being measured on-the-fly. A digital change control register 420 holds these so the inference calculating micro-computer 410 can go back to sleep or do other tasks. Each digital control bit is connected to a tunable component 422, 424 within the tunable analog circuit 406.” Para. [0073] teaches “An ML model that was built, trained, and tested in circuit design simulations has been distilled into its essence, coded, and stored as tuning memory 418. Such machine learning model is used by the inference calculating micro-computer 410 to predict and generate the correct digital control bits predicted to be needed to put tunable analog circuit 406 back in-tune, given the instant on-the-fly PVT. The predicted necessary tuning that results is not tested on-the-fly as it was already tested in circuit design simulations for each possible PVT.” Tuning memory 206, Abstract teaches “(c) a tuning memory embedded with a machine learning (ML) model of the analog circuit and (d) an artificial intelligence (AI) engine configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory.” Para. [0038] teaches “In some embodiments, the method includes providing a change control register configured to store the plurality of change control bits via connections to the plurality of tunable components.”)
With respect to claim 19,
De further teaches,
The method of claim 15, further including: training, by the classification engine, the ML model to obtain the weights; and storing, by the classification engine, the weights to the memory structure. (Para. [0015] teaches “But the development, training, and testing of respective ML models are done on the analog circuit design platforms based on the results of simulations of the analog circuits over the specified ranges in PVT values.” Para. [0030] teaches “the IC includes a change control register configured to store the plurality of change control bits through connections to the plurality of tunable components.” Para. [0034] teaches “the ML model is trained and tested with a plurality of results of a series of design simulations of the analog circuit, where the ML model is stored as a tuning model which represents a correlation between the signal inputs and an output target control variable based on which the AI engine calculates the plurality of analog circuit target control inferences and predictions.” Para. [0058] teaches “These relationships either in the form of equations or as regression tree (depending on the statistical process) in 110 are stored as ML tuning memory 122 on the chip 120.”)
With respect to claim 20,
De further teaches,
The method of claim 15, wherein the memory structure includes one or more of fuses or a read-only memory. (Para. [0066] teaches “The ML model could also be stored in a read-only or a writeable lookup table from which the AI engine calculates a plurality of analog circuit target control predictions and inferences.”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over De (US 20230153597 A1) as modified by Diamant (US 12210940 B1).
With respect to claim 1,
De teaches,
and a chip comprising logic coupled to one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic including: (See figures 2,3, and 4 silicon chips. Where the components on the chip are either configurable or have certain functionalities for example the memory.)
a memory structure including stored weights associated with a machine learning (ML) model, (Tuning memory 206, Abstract teaches “(c) a tuning memory embedded with a machine learning (ML) model of the analog circuit and (d) an artificial intelligence (AI) engine configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory.”)
a plurality of digital temperature sensors to generate readings, (Para. [0024] teaches “The Process, Voltage Temperature (PVT) characteristics monitor includes a plurality of PVT sensors. The tuning memory is embedded with a machine learning (ML) model of the analog circuit. The AI engine is configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory.”)
and a classification engine to retrieve the stored weights from the memory structure and adjust the readings from the plurality of digital temperature sensors based on the weights and electrical parameters associated with the chip. (Para. [0024] generate a plurality of change control bits from the predictions based on the ML model, where the plurality of change control bits activates one or more digital switches to retune the analog circuit. Para. [0072] teaches “An on-chip temperature sensor 414 provides the (T) in PVT by measuring the on-the-fly operating temperature that tunable analog circuit 406 is experiencing. The T-measurement is taken in by the inference calculating micro-computer 410. An executable AI-program 416 run by the inference calculating micro-computer 410 uses tuning memory 418 to calculate digital control bits from the PVT being measured on-the-fly. A digital change control register 420 holds these so the inference calculating micro-computer 410 can go back to sleep or do other tasks. Each digital control bit is connected to a tunable component 422, 424 within the tunable analog circuit 406.” Para. [0073] teaches “An ML model that was built, trained, and tested in circuit design simulations has been distilled into its essence, coded, and stored as tuning memory 418. Such machine learning model is used by the inference calculating micro-computer 410 to predict and generate the correct digital control bits predicted to be needed to put tunable analog circuit 406 back in-tune, given the instant on-the-fly PVT. The predicted necessary tuning that results is not tested on-the-fly as it was already tested in circuit design simulations for each possible PVT.”
De does not explicitly teach,
A computing system comprising: a network controller;
Diamant teaches,
A computing system comprising: a network controller; (Col. 27 Ln. [32] teaches “Computer system 2000 further includes a network interface 2040”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify De with a computing system comprising: a network controller such as that of Diamant.
One of ordinary skill would have been motivated to modify De, because it would allow information to be transmitted in the network as seen in (Col. 28 Ln(s). [35-41 & 62-65]) of Diamant.
With respect to claim 5,
De further teaches,
The computing system of claim 1, wherein the classification engine is further to: train the ML model to obtain the weights; and store the weights to the memory structure. (Para. [0015] teaches “But the development, training, and testing of respective ML models are done on the analog circuit design platforms based on the results of simulations of the analog circuits over the specified ranges in PVT values.” Para. [0030] teaches “the IC includes a change control register configured to store the plurality of change control bits through connections to the plurality of tunable components.” Para. [0034] teaches “the ML model is trained and tested with a plurality of results of a series of design simulations of the analog circuit, where the ML model is stored as a tuning model which represents a correlation between the signal inputs and an output target control variable based on which the AI engine calculates the plurality of analog circuit target control inferences and predictions.” Para. [0058] teaches “These relationships either in the form of equations or as regression tree (depending on the statistical process) in 110 are stored as ML tuning memory 122 on the chip 120.”)
With respect to claim 6,
De teaches,
The computing system of claim 1,
wherein the memory structure includes one or more of fuses or a read-only memory. (Para. [0066] teaches “The ML model could also be stored in a read-only or a writeable lookup table from which the AI engine calculates a plurality of analog circuit target control predictions and inferences.”)
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over De (US 20230153597 A1) and Diamant (US 12210940 B1) as applied to claim 1 above, and further in view of Cader (US 20220404235 A1).
With respect to claim 2,
The combination of De and Diamant does not explicitly teach,
The computing system of claim 1, wherein the electrical parameters and the plurality of digital temperature sensors are to be uncalibrated.
Cader teaches,
The computing system of claim 1, wherein the electrical parameters and the plurality of digital temperature sensors are to be uncalibrated. (Para. [0056] teaches “This model takes uncalibrated measurements of low-cost device and current environment parameters”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of De and Diamant wherein the electrical parameters and the plurality of digital temperature sensors are to be uncalibrated such as that of Cader.
One of ordinary skill would have been motivated to modify the combination of De and Diamant, because as seen in Para. [0027] of Cader “The anomalous data may indicate certain characteristics of sensors or measured attributes of the data center such as a sensor becoming uncalibrated, a sensor malfunctioning, etc. In another example, the sensor data may be identified by the ML model as producing frequency data that is unusual for the particular sensor.”
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over De (US 20230153597 A1) and Diamant (US 12210940 B1) as applied to claim 1 above, and further in view of Cheng (US 20160087918 A1).
With respect to claim 3,
The combination of De and Diamant does not explicitly teach,
The computing system of claim 1, wherein the logic further includes a plurality of intra-die variation (IDV) probes to generate one or more of the electrical parameters.
Cheng teaches,
wherein the logic further includes a plurality of intra-die variation (IDV) probes to generate one or more of the electrical parameters. (Para. [0034] teaches “provide IDV (In-die variation) data to be consumed by a circuit requiring three settings to span the entire PVT range of operation. In some embodiments, an IDV circuit may be implemented as a ring oscillator.” Also see Figure 4.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of De and Diamant wherein the logic further includes a plurality of intra-die variation (IDV) probes to generate one or more of the electrical parameters such as that of Cheng.
One of ordinary skill would have been motivated to modify the combination of De and Diamant, because as seen in Para. [0018] of Cheng “there may be many sensors in various locations of the die to support location specific sensing to compensate for within-die variations.” Furthermore, Para. [0062] teaches “One advantage of converged compensation scheme 300 is that it can speed adoption of this scheme to existing compensation scheme, while maintaining reuse of existing circuits. Another reason for implementing converged compensation scheme 300 is to take advantage of the adaptive PVT scheme, but on a smaller scale such as the PHY (Physical) level.”
With respect to claim 4,
The combination of De and Diamant does not explicitly teach,
The computing system of claim 3, wherein one or more of the plurality of IDV probes are positioned adjacent to one or more of the plurality of digital temperature sensors.
Cheng teaches,
wherein one or more of the plurality of IDV probes are positioned adjacent to one or more of the plurality of digital temperature sensors. (Para. [0065] teaches “Referring back to FIG. 4, in this example, the multiple IDV sensors (e.g., IDVA, IDVB, and IDVC) and temperature sensor (i.e., Temp Sensor) are connected to PCU 401 via individual or arbitrated digital sensor bus 405.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of De and Diamant wherein one or more of the plurality of IDV probes are positioned adjacent to one or more of the plurality of digital temperature sensors such as that of Cheng.
One of ordinary skill would have been motivated to modify the combination of De and Diamant, because as seen in Para. [0018] of Cheng “there may be many sensors in various locations of the die to support location specific sensing to compensate for within-die variations.” Furthermore, Para. [0062] teaches “One advantage of converged compensation scheme 300 is that it can speed adoption of this scheme to existing compensation scheme, while maintaining reuse of existing circuits. Another reason for implementing converged compensation scheme 300 is to take advantage of the adaptive PVT scheme, but on a smaller scale such as the PHY (Physical) level.”)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over De (US 20230153597 A1) as applied to claim 7 above, and further in view of Cader (US 20220404235 A1).
With respect to claim 8,
The combination of De and Diamant does not explicitly teach,
The semiconductor apparatus of claim 7, wherein the electrical parameters and the plurality of digital temperature sensors are to be uncalibrated.
Cader teaches,
wherein the electrical parameters and the plurality of digital temperature sensors are to be uncalibrated. (Para. [0056] teaches “This model takes uncalibrated measurements of low-cost device and current environment parameters”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of De and Diamant wherein the electrical parameters and the plurality of digital temperature sensors are to be uncalibrated such as that of Cader.
One of ordinary skill would have been motivated to modify the combination of De and Diamant, because as seen in Para. [0027] of Cader “The anomalous data may indicate certain characteristics of sensors or measured attributes of the data center such as a sensor becoming uncalibrated, a sensor malfunctioning, etc. In another example, the sensor data may be identified by the ML model as producing frequency data that is unusual for the particular sensor.”
Claims 9, 10, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over De (US 20230153597 A1) as applied to claims 7 and 15 above, and further in view of Cheng (US 20160087918 A1).
With respect to claim 9,
De does not explicitly teach,
The semiconductor apparatus of claim 7, wherein the logic further includes a plurality of intra-die variation (IDV) probes to generate one or more of the electrical parameters.
Cheng teaches,
wherein the logic further includes a plurality of intra-die variation (IDV) probes to generate one or more of the electrical parameters. (Para. [0034] teaches “provide IDV (In-die variation) data to be consumed by a circuit requiring three settings to span the entire PVT range of operation. In some embodiments, an IDV circuit may be implemented as a ring oscillator.” Also see Figure 4.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify De wherein the logic further includes a plurality of intra-die variation (IDV) probes to generate one or more of the electrical parameters such as that of Cheng.
One of ordinary skill would have been motivated to modify De, because as seen in Para. [0018] of Cheng “there may be many sensors in various locations of the die to support location specific sensing to compensate for within-die variations.” Furthermore, Para. [0062] teaches “One advantage of converged compensation scheme 300 is that it can speed adoption of this scheme to existing compensation scheme, while maintaining reuse of existing circuits. Another reason for implementing converged compensation scheme 300 is to take advantage of the adaptive PVT scheme, but on a smaller scale such as the PHY (Physical) level.”
With respect to claim 10,
De does not explicitly teach,
The semiconductor apparatus of claim 9, wherein one or more of the plurality of IDV probes are positioned adjacent to one or more of the plurality of digital temperature sensors.
Cheng teaches,
wherein one or more of the plurality of IDV probes are positioned adjacent to one or more of the plurality of digital temperature sensors. (Para. [0065] teaches “Referring back to FIG. 4, in this example, the multiple IDV sensors (e.g., IDVA, IDVB, and IDVC) and temperature sensor (i.e., Temp Sensor) are connected to PCU 401 via individual or arbitrated digital sensor bus 405.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify De wherein one or more of the plurality of IDV probes are positioned adjacent to one or more of the plurality of digital temperature sensors such as that of Cheng.
One of ordinary skill would have been motivated to modify De, because as seen in Para. [0018] of Cheng “there may be many sensors in various locations of the die to support location specific sensing to compensate for within-die variations.” Furthermore, Para. [0062] teaches “One advantage of converged compensation scheme 300 is that it can speed adoption of this scheme to existing compensation scheme, while maintaining reuse of existing circuits. Another reason for implementing converged compensation scheme 300 is to take advantage of the adaptive PVT scheme, but on a smaller scale such as the PHY (Physical) level.”)
With respect to claim 17,
De does not explicitly teach,
The method of claim 15, further including generating, by a plurality of intra-die variation (IDV) probes, one or more of the electrical parameters.
Cheng teaches,
further including generating, by a plurality of intra-die variation (IDV) probes, one or more of the electrical parameters. (Para. [0034] teaches “provide IDV (In-die variation) data to be consumed by a circuit requiring three settings to span the entire PVT range of operation. In some embodiments, an IDV circuit may be implemented as a ring oscillator.” Also see Figure 4.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify De further including generating, by a plurality of intra-die variation (IDV) probes, one or more of the electrical parameters such as that of Cheng.
One of ordinary skill would have been motivated to modify De, because as seen in Para. [0018] of Cheng “there may be many sensors in various locations of the die to support location specific sensing to compensate for within-die variations.” Furthermore, Para. [0062] teaches “One advantage of converged compensation scheme 300 is that it can speed adoption of this scheme to existing compensation scheme, while maintaining reuse of existing circuits. Another reason for implementing converged compensation scheme 300 is to take advantage of the adaptive PVT scheme, but on a smaller scale such as the PHY (Physical) level.”
With respect to claim 18,
De does not explicitly teach,
The method of claim 17, wherein one or more of the plurality of IDV probes are positioned adjacent to one or more of the plurality of digital temperature sensors.
Cheng teaches,
wherein one or more of the plurality of IDV probes are positioned adjacent to one or more of the plurality of digital temperature sensors. (Para. [0065] teaches “Referring back to FIG. 4, in this example, the multiple IDV sensors (e.g., IDVA, IDVB, and IDVC) and temperature sensor (i.e., Temp Sensor) are connected to PCU 401 via individual or arbitrated digital sensor bus 405.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify De wherein one or more of the plurality of IDV probes are positioned adjacent to one or more of the plurality of digital temperature sensors such as that of Cheng.
One of ordinary skill would have been motivated to modify De, because as seen in Para. [0018] of Cheng “there may be many sensors in various locations of the die to support location specific sensing to compensate for within-die variations.” Furthermore, Para. [0062] teaches “One advantage of converged compensation scheme 300 is that it can speed adoption of this scheme to existing compensation scheme, while maintaining reuse of existing circuits. Another reason for implementing converged compensation scheme 300 is to take advantage of the adaptive PVT scheme, but on a smaller scale such as the PHY (Physical) level.”)
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over De (US 20230153597 A1) as applied to claim 7 above, and further in view of Englekirk (US 20230273271 A1).
With respect to claim 12,
De does not explicitly teach,
The semiconductor apparatus of claim 7, wherein the memory structure includes fuses.
Englekirk teaches,
wherein the memory structure includes fuses. (Para. [0007] teaches “Embodiments provide predictable operation that is less susceptible to process/voltage/temperature (PVT) variations, allow the use of arrays of fuses that may be scaled to relatively large memory sizes (e.g., 1024 bits), uses little integrated circuit area, and do not require extra pins for operation.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify De wherein the memory structure includes fuses such as that of Englekirk.
One of ordinary skill would have been motivated to modify De, because as seen in para. [0017] of Englekirk memory structures that include fuses allow for large memory sizes and are less susceptible to voltage and temperature variations.
Conclusion
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should be directed to JOSHUA L FORRISTALL whose telephone number is (703)756-4554. The examiner
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