DETAILED ACTION
This action is responsive to communication filed 01/06/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species 1 in the reply filed on 01/06/2026 is acknowledged.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/06/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/25/2023, 04/17/2024, and 04/09/2026 are acknowledged. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale,
or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kishimoto et al. (US 20210296489 A1).
Regarding claim 1, Kishimoto et al. (see, e.g., FIG. 1 and annotated FIG 2 below) discloses a semiconductor device comprising:
a first electrode (Fig 1: 38);
a first semiconductor region (Fig. 1: 12) of a first conductivity type (paragraph [0026]: n) disposed above the first electrode;
an insulating film (Fig. 1: 52 and 72) disposed in the first semiconductor region;
a second electrode (Fig. 1: 58 and 78) disposed in the insulating film;
a second semiconductor region (Fig. 2: 24b) of a second conductivity type (paragraph [0050]: p) adjacent to the second electrode via the insulating film;
a third semiconductor region (Fig. 2: 16) of the first conductivity type (paragraph [0029]) disposed on the second semiconductor region; and
a third electrode (Fig. 2: 42) electrically coupled to a contact portion (Fig. 2: 36a, 36b, and 36c),
the contact portion being in contact with the first semiconductor region to form a Schottky junction on a first side surface (Fig. 2: 36c),
being in contact with the second semiconductor region and the third semiconductor region on a second side surface (Fig. 2: 36a and 36b) opposite to the first side surface,
and having a bottom surface (see annotated Fig. 2 below: “bottom surface”) located above a bottom surface of the second semiconductor region (see annotated Fig. 2 below: “semiconductor bottom surface”).
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Regarding claim 2, Kishimoto et al. (see, e.g., FIG. 1 and Annotated FIG. 2 above) discloses the semiconductor device according to claim 1,
wherein the first semiconductor region has a protrusion (Fig. 1: 14a, 14b and 14c) having a third side surface (see annotated Fig. 2 above: 14b contacting 36c at “region”) in contact with the first side surface of the contact portion, and
the protrusion is in contact with another contact portion (Fig. 1: 36 surrounding 42c) to form a Schottky junction on a fourth side surface opposite (Fig. 1: 14c) to the third side surface.
Regarding claim 3, Kishimoto et al. (see, e.g., Annotated FIG. 2 above) discloses the semiconductor device according to claim 1,
wherein the contact portion is in contact with the first semiconductor region in an entire (see annotated Fig. 2 above: “region”) region of the first side surface to form a Schottky junction.
Regarding claim 4, Kishimoto et al. (see, e.g., Annotated FIG. 2 above) discloses the semiconductor device according to claim 1, further comprising:
a fourth semiconductor region (24a) of the second conductivity type that is in contact with the contact portion and the second semiconductor region
and has a higher impurity concentration than the second semiconductor region (paragraph [0050]).
Regarding claim 5, Kishimoto et al. (see, e.g., Annotated FIG. 2 above) discloses the semiconductor device according to claim 4,
wherein the fourth semiconductor region is disposed between a bottom surface of the contact portion and the first semiconductor region.
Regarding claim 6, Kishimoto et al. (see, e.g., FIG. 1) discloses the semiconductor device according to claim 1, further comprising:
a fourth electrode (54 and 74) disposed below the second electrode in the first insulating film
and electrically coupled to the third electrode (paragraphs [0032]-[0033]).
Regarding claim 7, Kishimoto et al. discloses the semiconductor device according to claim 1,
wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are made of silicon including impurities (paragraph [0054]).
Regarding claim 8, Kishimoto et al. discloses the semiconductor device according to claim 7,
wherein the contact portion includes titanium (paragraph [0052]: “titanium”), cobalt, nickel, platinum, or tungsten.
Regarding claim 9, Kishimoto et al. discloses the semiconductor device according to claim 1,
wherein the insulating film is made of silicon oxide or silicon nitride (paragraph [0057]: “silicon oxide or silicon nitride”).
Regarding claim 10, Kishimoto et al. discloses the semiconductor device according to claim 1,
wherein the first conductivity type is n-type, and the second conductivity type is p-type.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shimizu et al. (US 20170077299 A1), (see, e.g., FIG. 5), discloses two contact portions (40a and 40b) between a single pair of second electrodes (18) wherein a protrusion of the first semiconductor region (24) lies between the contact portions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AIDAN D BANKLER whose telephone number is (571)272-0883. The examiner can normally be reached Monday through Thursday 7:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AIDAN D BANKLER/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 24, 2026
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