Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/23/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 43, 45-47, 50-51, and 60-62 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Beyer et al (US20140227147A1 published 08/14/2014; hereinafter Beyer).
Regarding claim 43, Beyer teaches a chip carrier comprising:
a planar frame (an encapsulation body 120 – paragraph 28 and Figs. 3-4) coupleable with a flowcell portion of a fluid adapter (the encapsulation body 120 coupled to a fluid output port 152 of a fluid pipe 153 – Figs. 3-4), the planar frame including first and second opposing sides (the encapsulation body 120 including first and second opposing sides – Figs. 3-4);
an open carrier portion (a portion of the second side of the encapsulation body 120 contacting the first main chip surface 111 – Figs. 3-4) disposed on the second opposing side of the planar frame, the open carrier portion being configured to receive and support a semiconductor diagnostic chip (“configured to receive and support a semiconductor diagnostic chip” does not positively recite the semiconductor chip and per MPEP2115 the limitation is deemed to read on a carrier capable of receiving a semiconductor chip) having electrical contacts (the portion of the second side supporting a semiconductor chip 110 having chip electrodes connected to conductor traces 202 – Figs. 3-4 and paragraph 41);
an electrical interface (an electrical redistribution structure composed of a structured metal layer (RDL) sandwiched, e.g., between two polymer layers comprising the conductor traces 202 – paragraph 42) having a plurality of electrical contacts disposed along the second opposing side of the planar frame (the conductor traces 202 are disposed along the second side of the encapsulation body 120 – Figs. 3-4 and paragraph 41), the electrical interface being configured to electrically couple with the electrical contacts of the semiconductor diagnostic chip (the conductor traces 202 are connected to the chip electrodes on the semiconductor chip 110 – Figs. 3-4 and paragraph 41); and
an electrical array having an array of contact pads so as to electrically couple with an instrument interface (a plurality of external contact elements 201 capable of electrically coupling with an instrument interface – Figs. 3-4).
Regarding claim 45, Beyer teaches the chip carrier of claim 43, wherein the open carrier portion is configured to support the semiconductor diagnostic chip in a vertical orientation (the portion of the second side of the encapsulation body 120 is capable of holding the chip 110 in a vertical orientation – paragraph 28 and Figs. 3-4).
Regarding claim 46, Beyer teaches the chip carrier of claim 43, wherein the open carrier portion is configured for receiving any of the following types of chips: CMOS, ISFET, bulk acoustic, non-bulk acoustic, piezo- acoustic and pore array sensor chips (the portion of the second side of the encapsulation body 120 is capable of holding CMOS, ISFET, bulk acoustic, non-bulk acoustic, piezo- acoustic and pore array sensor chips – paragraph 28 and Figs. 3-4).
Regarding claim 47, Beyer teaches the chip carrier of claim 43, further comprising:
a coupling feature (a microfluidic component 130 – Fig. 4) to securely couple the second opposing side of the planar frame to a planar surface of a flowcell adapter (the microfluidic component 130 coupling the second side to a planar surface of a structured layer 140 – Fig. 4) at least partly defining a flowcell chamber defined therein such that when the chip carrier carries an active element and is coupled to the flowcell adapter (an active region 115 coupled to the structured layer 140 – Fig. 4), the flowcell chamber is defined between the flowcell adapter and the active element (a flowcell chamber defined between the active region 115 and the microfluidic component 130 – Fig. 4).
Regarding claim 50, Beyer teaches the chip carrier of claim 43, wherein the electrical array (the contact elements 201 – Figs. 3-4) is arranged so as to interface with corresponding contacts of a chip control board of a module when the chip carrier is coupled within a chip carrier device and fluidically coupled with a sample processing cartridge operably coupled within the module (the contact elements 201 are capable of interfacing with corresponding contacts of a chip control board of a module when the chip carrier is coupled within a chip carrier device and fluidically coupled with a sample processing cartridge operably coupled within the module – Figs. 3-4).
Regarding claim 51, Beyer teaches the chip carrier of claim 43, wherein the electrical interface includes one or more active components configured for signal integrity, amplification, multiplexing or any combination thereof (the conductor traces 202 are connected to an integrated circuitry such as, e.g., a control logic for evaluating an electrical sensor signal indicative of a sensed microfluidic quantity – paragraph 37).
Regarding claim 60, Beyer teaches the chip carrier of claim 43, further comprising:
an alignment feature (a fluid output pin 152a – Fig. 4) to securely couple the second opposing side of the planar frame to a planar surface of a flowcell adapter at least partly defining a flowcell chamber defined therein (the fluid output pin 152a is capable of securely coupling the second side a planar surface of a structured layer 140 – Fig. 4) such that when the chip carrier carries an active element and is coupled to the flowcell adapter (the chip carrier carries an active region 115 a structured layer 140 – Fig. 4), the flowcell chamber is defined between the flowcell adapter and the active element (a flowcell chamber defined between the active region 115 and the microfluidic component 130 – Fig. 4).
Regarding claim 61, Beyer teaches the chip carrier of claim 43, further comprising:
a coupling (a microfluidic component 130 – Fig. 4) and an alignment feature (a fluid output pin 152a – Fig. 4) to securely couple the second opposing side of the planar frame to a planar surface of a flowcell adapter (the microfluidic component 130 and the fluid output pin 152a are capable of securely coupling the second side a planar surface of a structured layer 140 – Fig. 4) at least partly defining a flowcell chamber defined therein such that when the chip carrier carries an active element and is coupled to the flowcell adapter (the chip carrier carries an active region 115 a structured layer 140 – Fig. 4), the flowcell chamber is defined between the flowcell adapter and the active element (a flowcell chamber defined between the active region 115 and the microfluidic component 130 – Fig. 4).
Regarding claim 62, Beyer teaches the chip carrier of claim 43, further comprising the semiconductor diagnostic chip (the semiconductor chip 110 – Figs. 3-4 and paragraph 41).
Response to Arguments
Applicant’s arguments with respect to claim 43 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/T.C.S./Examiner, Art Unit 1796
/CHARLES CAPOZZI/Supervisory Patent Examiner, Art Unit 1798
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