Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group 1 in the reply filed on January 20th, 2026 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 20th, 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6-10, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 20200411072 A1).
Regarding claim 1; FIG. 5A, FIG. 5B, FIG. 5C, FIG. 6A, FIG. 6B, and FIG. 12A of Zhang et al. teaches a semiconductor structure, comprising:
a first field effect transistor (SG; FIG. 5A; paragraph 0130) located in a first device region of a substrate (108; FIG. 5A; paragraph 0130) and comprising first active regions (132, 134; FIG. 5A; paragraph 0130) laterally spaced from each other by a first semiconductor channel (133; FIG. 5A; paragraph 0130), a first gate dielectric (120; FIG. 5A; paragraph 0125) overlying the first semiconductor channel, a first gate electrode (126; FIG. 5A; paragraph 0125) overlying the first gate dielectric, and a first gate spacer (12; FIG. 5A; FIG. 5B; FIG. 5C; paragraph 122) having first laterally-straight outer sidewalls having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric; and
a second field effect transistor (FeFET; FIG. 6A; paragraph 0139) located in a second device region of the substrate (108; FIG. 6A; paragraph 0139) and comprising second active regions (134, 136; FIG. 6A; paragraph 0139) laterally spaced from each other by a second semiconductor channel (135; FIG. 6A; paragraph 0139), a second gate dielectric (150, 50L; FIG. 6A; FIG. 12A; paragraph 0136; paragraph 0171) overlying the second semiconductor channel (33; FIG. 12A; paragraph 170) and the second active regions (33; FIG. 12A; paragraph 0186) and including a pair of discrete gate-dielectric openings (49’; FIG. 12A; paragraph 170); therethrough that overlie a respective one of the second active regions, a second gate electrode (156; FIG. 6A; paragraph 0136) overlying the second gate dielectric, and a second gate spacer (12; FIG. 6A; FIG. 6B; paragraph 122) comprising:
a contoured portion (12; FIG. 6A; FIG. 6B; paragraph 122) that overlies a portion of a top surface of the second gate electrode and that laterally surrounds the second gate electrode; and
horizontally-extending portions (42; FIG. 12A; paragraph 170) that overlie the second active regions and including a pair of discrete gate-spacer openings (49’; FIG. 12A; paragraph 169) therethrough that overlie the pair of discrete gate-dielectric openings.
Regarding claim 2, FIG. 5A of Zhang et al. teaches the semiconductor structure of Claim 1, wherein:
the first active regions (132, 134; FIG. 5A; paragraph 0130) are laterally spaced from each other by the first semiconductor channel (134; FIG. 5A; paragraph 0130) along a first channel direction; and
the first laterally-straight outer sidewalls (12; FIG. 5A; paragraph 0122) laterally extend straight along a horizontal direction that is perpendicular to the first channel direction.
Regarding claim 6, FIG. 12A and FIG. 18A of Zhang et al. teach the semiconductor structure of Claim 1, wherein each discrete gate-dielectric opening (49’; FIG. 12A; paragraph 0170) of the pair of discrete gate-dielectric openings has a respective top periphery that coincides with a bottom periphery a of respective discrete gate-spacer opening of the pair of discrete gate-spacer openings (39; FIG. 18A; paragraph 0179) of the second gate spacer (42; FIG. 12A; paragraph 170).
Regarding claim 7, FIG. 7A and FIG, 7B of Zhang et al. teaches the semiconductor structure of Claim 1, further comprising a planarization dielectric layer (160; FIG. 7A; paragraph 0142) overlying and contacting each of the first gate spacer (12; FIG. 7B; paragraph 0122) and the second gate spacer (12; FIG. 7B; paragraph 0122).
Regarding claim 8, FIG. 5A and FIG. 7A of Zhang et al. teach the semiconductor structure of Claim 7, further comprising:
first active-region contact via structures (172, 176; FIG. 7A; paragraph 0147) contacting the planarization dielectric layer (160; FIG. 7A; paragraph 0142) and electrically connected to a respective one of the first active regions (132, 134; FIG. 5A; paragraph 0130); and
second active-region contact via structures (172, 176; FIG. 7A; paragraph 0147) contacting the planarization dielectric layer and electrically connected to a respective one of the second active regions (134, 136; FIG. 6A; paragraph 0139).
Regarding claim 9, FIG. 12A, FIG. 18A, and FIG. 19A of Zhang et al. teach the semiconductor structure of Claim 8, wherein each of the second active-region contact via structures (38V; FIG. 19A; paragraph 0180) vertically extends through a respective discrete gate-dielectric opening) of the pair of discrete gate-dielectric openings (49’; FIG. 12A; paragraph 0170), and vertically extends through a respective discrete gate-spacer opening (39; FIG. 18A; paragraph 0179) of the pair of discrete gate-spacer openings.
Regarding claim 10, FIG. 5A; FIG. 5B; FIG. 5C of Zhang et al. teach the semiconductor structure of Claim 8, further comprising:
first metal-semiconductor alloy regions (SG, 126; FIG. 5A; FIG. 5B; FIG. 5C; paragraph 0124; paragraph 130) contacting a respective one of the first active regions (132, 134; FIG. 5A; paragraph 0130), a respective one of the first laterally-straight outer sidewalls of the first gate spacer (12; FIG. 5A; FIG. 5B; FIG. 5C; paragraph 0122), and a bottom surface of a respective one of the first active-region contact via structures; and
Regarding claim 12, FIG. 7A of Zhang et al. teaches the semiconductor structure of Claim 1, further comprising:
a third metal-semiconductor alloy region (156; FIG. 7A; paragraph 0135; paragraph 0136)
located in a top portion of the second gate electrode (156; FIG. 7A; paragraph 0135; paragraph 0136)
; and
a gate contact via structure (38V, 47; FIG. 19A; paragraph 0180) extending through an opening (39; FIG. 18A; paragraph 0179) in the contoured portion of the second gate spacer ((42; FIG. 12A; paragraph 170) and contacting the third metal-semiconductor alloy region.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. in view of Chibvongodze et al. (US 20200185397 A1).
Regarding claim 3, Zhang et al. teaches the semiconductor structure of Claim 1. Zhang et al. does not describe the structure further comprising shallow trench isolation structures located in an upper portion of the substrate and comprising a first opening in the first device region and comprising a second opening in the second device region, wherein the first opening laterally surrounds the first active regions and the second opening laterally surrounds the second active regions.
FIG. 1A of Chibvongodze et al. shows shallow trench isolation structures (720; FIG. 1A; paragraph 0081) are formed in an upper portion of the substrate semiconductor layer (9; FIG. 1A; paragraph 0081), being shown as openings in the device regions and positioned around the transistor active regions (742; FIG. 1A; paragraph 0081).
Zhang et al. and Chibvongodze et al. are both analogous to the claimed invention in that they involve semiconductor structures with field effect transistors. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have altered Zhang et al. to have the shallow trench isolation structures. STI structures are known to be used in semiconductor structures (paragraph 0081).
Regarding claim 4, the combination of Zhang et al. in view of Chibvongodze et al. teach the semiconductor structure of Claim 3. Zhang et al. does not teach the structure, wherein the horizontally-extending portions of the second gate spacer extend over and contact a top surface segment of the shallow trench isolation structures.
FIG. 1A of Chibvongdoze et al. teaches a dielectric liner (762; FIG. 1A; paragraph 0082) laid over the shallow trench isolation structures (720; FIG. 1A; paragraph 0081) and extending horizontally.
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have altered Zhang et al. to have the spacers covering the shallow trench isolation structures. The spacers would block diffusion of mobile ions and/or apply appropriate stress to underlying structures (paragraph 0082).
Regarding claim 5, the combination of Zhang et al. in view of Chibvongodze et al. teach the semiconductor structure of Claim 3. Zhang et al. does not teach the structure, wherein each of the pair of discrete gate-dielectric openings is laterally offset from and does not have any areal overlap in a top-down view with the shallow trench isolation structures.
FIG. 3A of Chibvongodze et al. teaches drain select level isolation structures (72; FIG. 3A; paragraph 0106) are formed through the insulating cap layer (70; FIG. 3A; paragraph 0106) and a subset of the sacrificial material layers (42; FIG. 3A; paragraph 0106) located at drain select levels, with the isolation structures not aligned with shallow trench isolation structures (720; FIG. 1A; paragraph 0081).
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have altered Zhang et al. to have the pair of discrete gate-dielectric openings not overlap the shallow trench isolation structures. They are located far apart from each other, so they can’t overlap (FIG. 3A).
Regarding claim 13, Zhang et al. teaches the semiconductor structure of Claim 1. Zhang et al. does not teach the structure wherein each of the first gate spacer and the second gate spacer comprises a respective dielectric layer stack of a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layers in the first gate spacer and the second gate spacer have a same first thickness, and the silicon nitride layers in the first gate spacer and the second gate spacer have a same second thickness.
FIG. 3B of Chibvongodze et al. teaches an alternating stack (32, 42; FIG. 3B; paragraph 0108), where the stacks share thickness and consist of silicon nitride and silicon oxide (paragraph 0145).
Zhang et al. and Chibvongodze et al. are both analogous to the claimed invention in that they involve semiconductor structures with field effect transistors. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have altered Zhang et al. to have the spacer stacks. These are known materials used for sacrificial and insulating layers (paragraph 0145).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. in view of Nishikawa et al. (US 20160351709 A1).
Regarding claim 11, Zhang et al. teaches the semiconductor structure of Claim 10. Zhang et al. does not teach the structure further comprising shallow trench isolation structures located in an upper portion of the substrate, wherein:
the first metal-semiconductor alloy regions are in contact with the shallow trench isolation structures; and
the second metal-semiconductor alloy regions are not in contact with the shallow trench isolation structures.
FIG. 18 of Nishikawa et al. teaches two metal-semiconductor alloy regions (167, 367; FIG. 18; paragraph 0114), where one (167; FIG. 18; paragraph 0114) is in contact with shallow trench isolation structures (20; FIG. 18; paragraph 0030).
Zhang et al. and Nishikawa et al. are analogous to the claimed invention in that they involve semiconductor structures with field effect transistors. Therefore, it would have been obvious to a person with ordinary school in the art before the effective filing date of the claimed invention to have modified Zhang et al. so that one of the alloy regions is in contact with shallow trench isolation regions. This is a result of said alloy region being on the active regions (paragraph 0114).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. in view of Pachamuthu et al. (US 20200194450 A1).
Regarding claim 14, Zhang et al. teaches the semiconductor structure of Claim 1, further comprising a third field effect transistor (FeFET; FIG. 6A; paragraph 0139) located in a third device region of the substrate (108; FIG. 6A; paragraph 0139) and comprising third active regions (134, 136; FIG. 6A; paragraph 0139) laterally spaced from each other by a third semiconductor channel (135; FIG. 6A; paragraph 0139) and a third gate dielectric (150; FIG. 6A; paragraph 0136) overlying the third semiconductor channel and the third active regions. Zhang et al. does not teach the field effect transistors being low voltage, and the third gate dielectric having a smaller thickness than a thickness of the first gate dielectric and the second gate dielectric.
Pachamuthu et al. teaches a semiconductor structure including a plurality of low-voltage field effect transistors (paragraph 0053) and that multiple thicknesses can be employed for multiple gate dielectric layers (paragraph 0053).
Zhang et al. and Nishikawa et al. are analogous to the claimed invention in that they involve semiconductor structures with field effect transistors. Therefore, it would have been obvious to a person with ordinary school in the art before the effective filing date of the claimed invention to have modified Zhang et al. so that the field effect transistor was low voltage, and the third gate dielectric having a smaller thickness than the first gate dielectric. The different thicknesses for the gate dielectrics are used to form different types of field effect transistors or flash memory devices (paragraph 0053).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ando et al. (US 20150021698 A1) concerns intrinsic channels provided in a semiconductor substrate with a gate dielectric layer. Tsai et al. (US 20220254931 A1) concerns a semiconductor device including a insulating layer embedding a gate electrode, a gate dielectric stack, and an active layer overlying the gate electrode..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.A.V./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817