DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-15 without traverse in the reply filed on 12/12/2025 is acknowledged. Claims 16-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baraskar et al. (US 10804282 B2)
Regarding claim 1, Baraskar teaches,
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A memory device (FIGs. 16A-16B), comprising:
at least one alternating stack of insulating layers (32, Col. 25, l. 2) and electrically conductive layers (46);
memory stack structures (55, col. 25, l. 29) vertically extending through the at least one alternating stack,
wherein each of the memory stack structures comprises a respective vertical stack of memory elements (52, 52, 56, Col. 14, ll. 50-52) and a vertical semiconductor channel (601, Col. 14, l. 57);
an electrically conductive layer contact via structure (86, Col. 25, l. 13) vertically extending through an upper portion of the at least one alternating stack and contacting a top surface of one of the electrically conductive layers (46 as marked));
a plurality of support pillar structures (portion of 65 on the left of 86 as marked) having at least a dielectric outer sidewall (as marked) vertically extending through each layer within the at least one alternating stack and contacting a respective first sidewall segment of the layer contact via structure (left sidewall of 86 as marked);
and a plurality of dielectric spacers (portion of dielectric material 65 on the right of 86 as marked, col. 10, l. 15) vertically extending through the upper portion of the at least one alternating stack (as seen) and contacting a respective second sidewall segment of the layer contact via structure (right sidewall of 86 as marked).
Regarding claim 2, Baraskar teaches the memory device of claim 1 and further teaches wherein: the plurality of support pillar structures comprises a plurality of dielectric support pillar structures; and the plurality of dielectric support pillar structures and the plurality of dielectric spacers are azimuthally interlaced around a vertical axis passing through a center of the layer contact via structure (see FIG. 16A above, 65 on left and 65 on right are interlaced around a vertical axis passing through a center of 86).
Regarding claim 3, Baraskar teaches the memory device of claim 2 and further teaches, wherein: the plurality of dielectric support pillar structures comprises P dielectric support pillar structures; and P is an integer greater than 1 (see FIG. 16A as annotated below, there are two support pillar structures, hence P=2 and P> 1)
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Regarding claim 6, Baraskar teaches the memory device of claim 2 and further teaches, wherein: each of the plurality of dielectric support pillar structures has a respective center and a respective vertical axis passing through the respective center (vertical axis passing through the support pillar 65) ; and each of the vertical axes of the plurality of dielectric support pillar structures is laterally spaced from the vertical axis passing through the center of the layer contact via structure by a greater lateral distance than any point within the plurality of dielectric spacers is from the vertical axis passing through the center of the layer contact via structure (see FIG. 16A above, a lateral distance of a vertical axis passing through center of the support pillar 65 from the vertical axis passing through 86 is greater than a lateral distance of any point within the dielectric spacer 65 from the vertical axis passing through 86).
Regarding claim 7, Baraskar teaches the memory device of claim 1 and further teaches, wherein at least one of the plurality of dielectric support pillar structures comprises a lower portion (as marked) which is located under a bottom surface of the layer contact via structure (86 as marked).
Regarding claim 8, Baraskar teaches the memory device of claim 1 and further teaches, wherein each surface segment of the layer contact via structure (segment of 86) located above a horizontal plane including a top surface of the one of the electrically conductive layers (above top surface of 46 as marked) and below a horizontal surface including a topmost surface of the at least one alternating stack (below topmost surface of topmost 46) is in direct contact with one of plurality of support pillar structures (as marked) or with one of the plurality of dielectric spacers (as marked).
Regarding claim 12, Baraskar teaches the memory device of claim 1 and further teaches,
further comprising a contact-level dielectric layer (70, Col. 8, l. 62) that overlies the at least one alternating stack,
wherein: top surfaces of the plurality of support pillar structures (portion of 65 as marked) located within a horizontal plane including a top surface of the contact-level dielectric layer (70);
and topmost surfaces of the plurality of dielectric spacers are located within a horizontal plane including top surfaces of the at least one alternating stack (considering alternating stack including 70, top surface of the dielectric spacer 65 is located within the horizontal plane including top surface of 70 of the alternating stack).
Regarding claim 13, Baraskar teaches the memory device of claim 1 and further teaches, wherein each interface between the layer contact via structure (86) and a respective one of the plurality of support pillar structures (65 as marked) vertically extends from the one of the electrically conductive layers (46 as marked) to a horizontal plane including a topmost surface of the at least one alternating stack (topmost surface of topmost 46).
Regarding claim 14, Baraskar teaches the memory device of claim 1 and further teaches,
wherein each of the plurality of dielectric spacers (reconsidering 65 on the right of 86 as support pillar structure and 65 on left of 86 as the spacer structure instead as annotated below) comprises
at least one laterally-extending fin portion which is located at a level of a respective one of the electrically conductive layers (zigzag lower portion A-B-C-D-E-F of 65 on left as marked below, considered as fin laterally extending and located at a level A-B of 46),
has a respective horizontally-extending top surface contacting a respective overlying insulating layer within the at least one alternating stack (considering the alternating stack including 32, 46 & 70, horizontally extending top surface of 65 on left contacting overlying insulating layer 70),
and has a respective horizontally-extending bottom surface segment contacting a respective underlying insulating layer within the at least one alternating stack (horizontally extending bottom surface segment F-E contacting bottom surface of underlying insulating layer 32 as marked below).
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Regarding claim 15, Baraskar teaches the memory device of claim 1 and further teaches, further comprising: additional memory stack structures (55 as marked above) vertically extending through the at least one alternating stack, wherein the memory stack structure and the additional memory stack structures comprise a three-dimensional array of memory elements (comprising memory cells , Col. 26, ll. 50-57); and the electrically conductive layers comprise word lines (46 function as word line, Col. 22, ll. 27-28) for the three-dimensional array of memory elements.
Claims 1-3,5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LEE et al. (US 2023/0171965 A1)
Regarding claim 1, LEE teaches,
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A memory device (FIG. 2A as annotated above), comprising:
at least one alternating stack (GS_L/GS_U, para [0041])of insulating layers (30a/54a, para [0041]) and electrically conductive layers (35g/59g, para [0041]);
memory stack structures (73, para [0077]) vertically extending through the at least one alternating stack,
wherein each of the memory stack structures comprises a respective vertical stack of memory elements (data storage structure 75, para [0098]) and a vertical semiconductor channel (77, para [0098]);
an electrically conductive layer contact via structure (gate contact plugs 93g, para [0086]) vertically extending through an upper portion of the at least one alternating stack and contacting a top surface of one of the electrically conductive layers (35g/59g);
a plurality of support pillar structures (portion of insulating layer 67 on the left of 93g as marked) having at least a dielectric outer sidewall (right sidewall) vertically extending through each layer within the at least one alternating stack (as seen) and contacting a respective first sidewall segment (left sidewall) of the layer contact via structure (93g as marked);
and a plurality of dielectric spacers (portion of dielectric 67 on the right of layer contact via structure 93g as marked) vertically extending through the upper portion of the at least one alternating stack (as seen) and contacting a respective second sidewall segment (right sidewall) of the layer contact via structure (93g as marked).
Regarding claim 2, LEE teaches the memory device of claim 1 and further teaches wherein: the plurality of support pillar structures comprises a plurality of dielectric support pillar structures (see as marked above); and the plurality of dielectric support pillar structures and the plurality of dielectric spacers are azimuthally interlaced around a vertical axis passing through a center of the layer contact via structure (see FIG. 2A above, 67 on left and 67 on right of 93g are interlaced around a vertical axis passing through a center of 93g).
Regarding claim 3, LEE teaches the memory device of claim 2 and further teaches, wherein: the plurality of dielectric support pillar structures comprises P dielectric support pillar structures; and P is an integer greater than 1 (see FIG. 2A above, there are multiple support pillar structures and hence P>1).
Regarding claim 5, LEE teaches the memory device of claim 3 and further teaches, wherein: the at least one alternating stack comprises M (2) alternating stacks (GS_L and GS_U) , in which M is an integer greater than 1; the plurality of dielectric spacers comprises a total of M x P dielectric spacers (2xP, each stack GS_L /GS_U has P dielectric spacers); and the M x P dielectric spacers comprises M sets (2 sets) of P dielectric spacers that are azimuthally spaced apart around the vertical axis (see FIG. 16A above, 67/41 on left and 67/41 on right of 93g are interlaced around a vertical axis passing through a center of 93g), wherein each set of respective P dielectric spacers overlies or underlies any other set of respective P dielectric spacers (see FIG. 2A above, dielectric spaces 67 in upper stack GS_U overlies dielectric spacers 41 in the lower stack GS_L).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. (US 2023/0171965 A1)
Regarding claim 4, LEE teaches the memory device of claim 3 and further teaches, wherein each of the plurality of dielectric spacers is located within a respective azimuthal angle range around the vertical axis that has a magnitude less than 2π/P radian (93g in FIG. 2A above are tapered shape with decreasing width downwards renders lower portion of 67 on the left and right side of 93g interlaced around vertical central axis of 93g with an angle less than 90 degree (i.e. π/2 radian). Note: since there more than two dielectric spacers in FIG. 2A above , P>2 and 2π/P is less than π).
However, it is to be noted here that the claimed range of less than 2π/P radian (less than π for P>3) and the range less than π/2 taught by LEE overlaps each other. In the case where the claimed ranges “overlap or lie inside ranges teaches d by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Allowable Subject Matter
Claims 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 9-11, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
wherein each interface between the layer contact via structure and the plurality of support pillar structures has a horizontal cross-sectional profile in which a convex surface segment of the layer contact via structure is in direct contact with a concave surface segment of a respective one of the support pillar structures (claim 9).
wherein: each of the plurality of support pillar structures is in direct contact with a respective pair of dielectric spacers of the plurality of dielectric spacers; and each of the plurality of dielectric spacers is in direct contact with a respective pair of the support pillar structures (claim 10).
wherein: each of the plurality of support pillar structures is in direct contact with each insulating layer within the at least one alternating stack; and each insulating layer within the at least one alternating stack that overlies the one of the electrically conductive layers is in direct contact with at least two dielectric spacers of the plurality of dielectric spacers (claim 11).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Gauthier, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813