Prosecution Insights
Last updated: May 29, 2026
Application No. 18/358,801

DETECTING ELECTRICAL POWER LINE DISTURBANCES

Final Rejection §103
Filed
Jul 25, 2023
Priority
Dec 04, 2020 — divisional of 11/747,373
Examiner
POTHEN, FEBA
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
4 (Final)
81%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
511 granted / 630 resolved
+13.1% vs TC avg
Moderate +12% lift
Without
With
+12.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
27 currently pending
Career history
666
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
89.2%
+49.2% vs TC avg
§102
1.6%
-38.4% vs TC avg
§112
6.6%
-33.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 630 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/28/25 has been entered. Response to Arguments Applicant’s arguments with respect to claim(s) 1-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3, 8, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muccini et al., US 20170123445 in view of Cong, US 20120324269 in view of Honda et al., JP H0973322 Regarding claim 1, Muccini discloses a computing device comprising: a power supply configured to supply power to the computing device (Fig. 2; power supply unit 130A), the power supply comprising a hardware processor communicatively coupled to a bus, the hardware processor configured to (Fig. 2,6; controller 220A): detect an electrical power disturbance in the power supply (Fig. 2, 6; controller 220A detects whether PSU is defective or normal through voltage and current measurements ); and generate an indication, the indication comprising an identifier of the power supply (Fig. 2; ¶[0007],[0060]; indication of PSU 130A being defective out of other power supply units); communicate by the bus the indication of the electrical power disturbance to a monitoring device (Fig. 2; ¶[0060] “controller 220A indicates that PSU 130A is defective by transmitting a signal to MC 110 via communication bus 134”). Muccini is silent in the processor is configured to determine a first voltage range and a second voltage range for the power supply; monitor electrical power at an entry line and an exit line of the power supply to produce an entry waveform of an entry voltage and an exit waveform of an exit voltage of the power supply, wherein the electrical power disturbance in the power supply is detected when the entry voltage is below or above the first voltage range for a preset duration of time and when the exit voltage is below or above the input second voltage range for the preset duration of time. Cong teaches a processor configured to determine a first voltage range and a second voltage range for the power supply (Fig. 2; MCU 20 with setting module 210 sets an input and output voltage range; See ¶[0013]); monitor electrical power at an entry line and an exit line of the power supply (Fig. 1-3; power supply device 22 input voltage and output voltage monitored), wherein the electrical power disturbance in the power supply is detected when the entry voltage is below or above the first voltage range (¶[0020]; determines whether input voltage is outside of 110V-220V) and when the exit voltage is below or above the input second voltage range (Fig. 1-3; ¶[0020];determines whether output voltage is outside of 10V-12V). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Cong into Mussini for the benefit of determining possible faults related to an input voltage disturbance by monitoring the upper and lower thresholds of the voltage. Mussini as modified is silent in wherein the processor is configured to produce an entry waveform of an entry voltage and an exit waveform of an exit voltage of the power supply, and monitoring the exit and entry voltage for a preset duration of time. Honda teaches a processor configured to produce an entry waveform of an entry voltage and an exit waveform of an exit voltage of the power supply (Fig. 1-2; input voltage waveform detector 2 and an output voltage detector 3 stored in memory 11), and monitoring an input and output voltage for a preset duration of time (¶[0012]-[0013]; waveform recorded for a predetermined period) . It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Honda into Mussini as modified for the benefit of determining a behavior of the power supply device can in order to provide countermeasures. Regarding claim 3, Muccini is silent in wherein the electrical power disturbance in the power supply is detected when the entry waveform of the entry voltage or the exit waveform of the exit voltage deviates from a steady state waveform for the preset duration of time. Cong teaches detecting a power disturbance of a power supply when the entry voltage or the exit voltage deviates from a steady state (voltages outside of input of output range being non-steady state). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Cong into Mussini for the benefit of determining possible faults related to an input voltage disturbance by monitoring the upper and lower thresholds of the voltage. Honda teaches determining a power disturbance by monitoring an entry waveform of the entry voltage or the exit waveform of the exit voltage deviates for a preset duration of time (Fig. 1-2; ¶[0012], [0013]; input/ output waveforms recorded for a preset time). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Honda into Mussini as modified for the benefit of determining a behavior of the power supply device can in order to provide countermeasures. Regarding claim 8, Muccini discloses a method comprising: supplying, by a power supply, power to a device (Fig. 2; PSU 130A supplies power to a load); detecting, by a hardware processor of the power supply, an electrical power disturbance in the power supply (Fig. 2, 6; controller 220A detects whether PSU is defective or normal through voltage and current measurements ) ; and generating, based on the electrical disturbance, an indication comprising an identifier of the power supply (Fig. 2; ¶[0007],[0060]; indication of PSU 130A being defective out of other power supply units); communicating, by a bus of the power supply, the indication of the electrical power disturbance to a monitoring device (Fig. 2; ¶[0060] “controller 220A indicates that PSU 130A is defective by transmitting a signal to MC 110 via communication bus 134”). Muccini is silent in determining by the hardware processor, a first voltage range and a second voltage range for the power supply; monitoring by the hardware processor, electrical power at an entry line and an exit line of the power supply to produce an entry waveform of an entry voltage and an exit waveform of an exit voltage of the power supply, wherein the electrical power disturbance in the power supply is detected when the entry voltage is below or above the first voltage range for a preset duration of time and when the exit voltage is below or above the input second voltage range for the preset duration of time. Cong teaches a processor configured to determine a first voltage range and a second voltage range for the power supply (Fig. 2; MCU 20 with setting module 210 sets an input and output voltage range; See ¶[0013]); monitor electrical power at an entry line and an exit line of the power supply (Fig. 1-3; power supply device 22 input voltage and output voltage monitored), wherein the electrical power disturbance in the power supply is detected when the entry voltage is below or above the first voltage range (¶[0020]; determines whether input voltage is outside of 110V-220V) and when the exit voltage is below or above the input second voltage range (Fig. 1-3; ¶[0020];determines whether output voltage is outside of 10V-12V). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Cong into Mussini for the benefit of determining possible faults related to an input voltage disturbance by monitoring the upper and lower thresholds of the voltage. Mussini as modified is silent in wherein the processor is configured to produce an entry waveform of an entry voltage and an exit waveform of an exit voltage of the power supply, and monitoring the exit and entry voltage for a preset duration of time. Honda teaches a processor configured to produce an entry waveform of an entry voltage and an exit waveform of an exit voltage of the power supply (Fig. 1-2; input voltage waveform detector 2 and an output voltage detector 3 stored in memory 11), and monitoring an input and output voltage for a preset duration of time (¶[0012]-[0013]; waveform recorded for a predetermined period) . It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Honda into Mussini as modified for the benefit of determining a behavior of the power supply device can in order to provide countermeasures. Regarding claim 10, Muccini is silent in wherein the electrical power disturbance in the power supply is detected when the entry waveform of the entry voltage or the exit waveform of the exit voltage deviates from a steady state waveform for the preset duration of time. Cong teaches detecting a power disturbance of a power supply when the entry voltage or the exit voltage deviates from a steady state (voltages outside of input of output range being non-steady state). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Cong into Mussini for the benefit of determining possible faults related to an input voltage disturbance by monitoring the upper and lower thresholds of the voltage. Honda teaches determining a power disturbance by monitoring an entry waveform of the entry voltage or the exit waveform of the exit voltage deviates for a preset duration of time (Fig. 1-2; ¶[0012], [0013]; input/ output waveforms recorded for a preset time). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Honda into Mussini as modified for the benefit of determining a behavior of the power supply device can in order to provide countermeasures. Claim(s) 4, 5, 11, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muccini et al., US 20170123445 in view of Cong, US 20120324269 in view of Honda et al., JP H0973322 in view of Otani et al., US 20030222506 A1 Regarding claim 4, Muccini is silent in wherein the hardware processor is further configured to record a time of the electrical power disturbance. Otani teaches wherein the hardware processor is further configured to record a time of the electrical power disturbance (¶[0022]; RTC 41). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Otani into Muccini as modified for the benefit of providing time data of an abnormality so that historical patterns of the power supply can be observed and evaluated. Regarding claim 5, Muccini is silent in wherein the hardware processor is further configured to set a flag indicating that the electrical power disturbance occurred. Otani teaches wherein the hardware processor is further configured to set a flag indicating that the electrical power disturbance occurred (¶[0023]; Flag F). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Otani into Muccini as modified for the benefit of indicating that abnormality data of the power source is stored in a memory for later retrieval. Regarding claim 11, Muccini is silent in recording, by the hardware processor, a time of the electrical power disturbance. Otani teaches recording, by a processor, a time of the electrical power disturbance (¶[0022]; RTC 41). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Otani into Muccini as modified for the benefit of providing time data of an abnormality so that historical patterns of the power supply can be observed and evaluated. Regarding claim 12, Muccini is silent in setting, by the hardware processor, a flag indicating that the electrical power disturbance occurred. Otani teaches setting a flag indicating that the electrical power disturbance occurred (¶[0023]; Flag F). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Otani into Muccini as modified for the benefit of indicating that abnormality data of the power source is stored in a memory for later retrieval. Claim(s) 6, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muccini et al., US 20170123445 in view of Cong, US 20120324269 in view of Honda et al., JP H0973322 in view of Shih et al., US 20170308139 Regarding claim 6, Muccini is silent wherein the hardware processor is further configured to reboot the power supply in response to determining that the power supply crashed. Shih teaches wherein the hardware processor is further configured to reboot the power supply in response to determining that the power supply crashed. It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Shih into Muccini as modified for the benefit of operating the power supply when an abnormality is minor and does not require inactivation of the power supply. Regarding claim 13, Muccini is silent in rebooting, by the hardware processor, the power supply in response to determining that the power supply crashed. Shih teaches rebooting by a hardware processor the power supply in response to determining that the power supply crashed. It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Shih into Muccini as modified for the benefit of operating the power supply when an abnormality is minor and does not require inactivation of the power supply. Claim(s) 7, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muccini et al., US 20170123445 in view of Cong, US 20120324269 in view of Honda et al., JP H0973322 in view of Barford et al, US 20090113183 Regarding claim 7, Muccini is silent wherein the hardware processor is further configured to capture the entry waveform and the exit waveform of the power supply at a preset data rate. Barford teaches wherein the hardware processor is further configured to capture a voltage waveform of the power supply at a preset data rate (¶[0032]; testing method applicable to power supplies; voltage waveform capture based on a sampling rate). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Barford into Muccini as modified for the benefit of analyzing a voltage data of a device so that abnormalities can be detected over time. Regarding claim 14, Muccini is silent in further comprising capturing, by the hardware processor, the entry waveform and the exit waveform of the power supply at a preset data rate. Barford teaches capturing by a processor a voltage waveform of the power supply at a preset data rate (¶[0032]; testing method applicable to power supplies; voltage waveform capture based on a sampling rate). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Barford into Muccini as modified for the benefit of analyzing a voltage data of a device so that abnormalities can be detected over time. Claim(s) 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muccini et al., US 20170123445 in view of Cong, US 20120324269 in view of Honda et al., JP H0973322in view of Otani et al., US 20030222506 in view of Ives, US 20060168191 Regarding claim 15, Muccini as modified discloses the computing device of claim 4 but is silent in wherein the monitoring device generates a map of a location of the computing device or the power supply based on the indication and the time of the electrical power disturbance. Ives teaches wherein a monitoring device generates a map of a location of the computing device or the power supply based on the indication and the time of the electrical power disturbance (¶[0023]). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Ives into Muccini as modified for the benefit of providing a map so that the fault can be remedied quickly. Regarding claim 16, Muccini as modified discloses the computing device of claim 15, but is silent in wherein the computing device is one of a plurality of computing devices and the indication is one of a plurality of indications, and wherein the monitoring device determines if the electrical power disturbance is a utility event or a hardware event based on locations of each of the plurality of computing devices in the plurality of indications and a region of the locations of the plurality of indications. Ives teaches wherein the computing device is one of a plurality of computing devices and the indication is one of a plurality of indications, and wherein the monitoring device determines if the electrical power disturbance is a utility event or a hardware event based on locations of each of the plurality of computing devices in the plurality of indications and an amount of the plurality of indications (¶[0023] – [0025]). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Ives into Muccini as modified for the benefit of determining a type of fault so that the fault can be remedied quickly. Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muccini et al., US 20170123445 n view of Cong, US 20120324269 in view of Honda et al., JP H0973322 in view of Ives, US 20060168191in view of Graul, US 20210037035 Regarding claim 17, Muccini as modified discloses the computing device of claim 16, but is silent in wherein the monitoring device determines a suitable remedy for the electrical power disturbance based on if the electrical power disturbance is a utility event or a hardware event. Graul teaches wherein the monitoring device determines a suitable remedy for the electrical power disturbance based on if the electrical power disturbance is a utility event or a hardware event (¶[0002]). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Graul into Muccini as modified for the benefit of providing a type of fault so that a quick recovery to system and components can be made. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEBA POTHEN whose telephone number is (571)272-9219. The examiner can normally be reached 8:30-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEBA POTHEN/Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Show 8 earlier events
Sep 29, 2025
Response after Non-Final Action
Oct 28, 2025
Request for Continued Examination
Nov 05, 2025
Response after Non-Final Action
Dec 17, 2025
Non-Final Rejection mailed — §103
Mar 10, 2026
Examiner Interview Summary
Mar 10, 2026
Applicant Interview (Telephonic)
Mar 17, 2026
Response Filed
May 26, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
81%
Grant Probability
93%
With Interview (+12.0%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 630 resolved cases by this examiner. Grant probability derived from career allowance rate.

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