DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/26/2023 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1: Claim(s) 1, 2 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by USPN 10,958,862 B2 Yamazaki.
2: As for Claim 1, Yamazaki depicts in Figures 2, 3 and 5 and teaches on Column 4, Lines 44-51 and Column 6, Lines 44-63 an image sensor device, comprising: a first pixel located at a first row and a first column (see Figure 2) and comprising a first select transistor (25), the first pixel configured to output a first pixel signal through a first column line (multiple column lines SEL are depicted in Figure 2); and a second pixel located at a second row and the first column and comprising a second select transistor (25), the second row different from the first row, the second pixel configured to output a second pixel signal through a second column line before the first pixel signal is output (timing diagram of Figure 5 shows readout of pixels in the same column occurring at different times and subsequent to each other), wherein, during a first time period, the first select transistor is turned on and the first pixel signal is output, and wherein, during a second time period, the second select transistor is turned on, and a first voltage (voltage output from FD node and output through transistor 25) is applied to the second column line through the second select transistor (25), the second time period (time period starting at t1) including the first time period (the first time period is viewed by the examiner as the time period starting at t2).
3: As for Claim 2, Yamazaki teaches on Column 4, Lines 44-51 wherein the first voltage (voltage output to the column line) is based on a voltage level of a floating diffusion node (FD 22) which has been reset of the second pixel (reset transistor 23 resets the voltage of the FD node).
4: As for Claim 4, Yamazaki teaches in the timing diagram of Figure 5 and teaches on Column 6, Lines 44-63 wherein the second time period (viewed as the duration starting at t1 further includes a third time period and a fourth time period (the time period starting as t1 can be arbitrarily divided into multiple time periods), during the third time period, the first select transistor is turned off (signal PTX is turned low), and during the fourth time period, the first select transistor is turned on (signal PTX is turned high).
Allowable Subject Matter
Claims 12-20 are allowed.
Claims 3, 5-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach during a first time period and a second time period, the first select transistor is turned on and the first pixel signal is output, wherein, during a third time period, the second select transistor is turned on, and a first voltage is applied to the second column line through the second select transistor, the second time period including the first time period and the second time period, and wherein, during a fourth time period, the first select transistor is turned off, the third select transistor is turned on, and a second voltage is applied to the first column line through the third select transistor, the fourth time period between the first time period and the second time period when taken in combination with all the claims of the independent claim. Furthermore, the prior art does not teach performing a first readout operation based on turning on the first select transistor and starting an operation of applying a first voltage to the second column line based on turning on the second select transistor; terminating the first readout operation based on turning off the first select transistor and performing a shutter operation; terminating the shutter operation based on turning on the first select transistor and performing a second readout operation; and terminating the second readout operation based on turning off the first select transistor and terminating an operation of applying the first voltage to the second column line based on turning off the second select transistor, wherein an address of the second row is based on an address of the first row when taken in combination with all the limitations of the independent claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES M HANNETT whose telephone number is (571)272-7309. The examiner can normally be reached 8:00 AM-5:00 PM Monday thru Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at 571-272-7406 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES M HANNETT/Primary Examiner, Art Unit 2639
JMH
March 5, 2026