Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the communication filed on 3/19/2026.
Claims 1-18 have been examined.
Response to Arguments
Applicant's arguments filed 3/19/2026 have been fully considered but are moot in view of the new grounds of rejection presented below.
All objections and rejections not set forth below have been withdrawn.
Information Disclosure Statement
No IDS has been filed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 9, and 15 recite “the encryptions” which lacks antecedent basis in the claims.
All claims depending from any of the above rejected claims are also rejected by virtue of their dependence upon their respective rejected parent claim(s).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, are 4-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hassan et al. (US Patent Application Publication Number 2021/0119780), and further in view of Lee et al. (US Patent Application Publication Number 2012/0144277).
Regarding claim 1, Hassan taught a data encryption and decryption system (Hassan Fig. 1 and Paragraphs 0029-0035 for example), comprising:
a memory controlling circuit coupled to a memory unit, wherein the memory controlling circuit is configured to access the memory unit according to a write operation from a host, and the write operation comprises an initial write data and a write address (Hassan Figs. 1 and Paragraphs 0029-0035 for example), wherein the write address comprises an address field with at least one address bytes that specifies a memory address on which the write operation is executed, such that the encryptions implemented for different memory addresses are unique (Hassan Figs. 2 and Paragraph 0037 for example); and
an encryption and decryption circuit, coupled to the memory controlling circuit, wherein the encryption and decryption circuit is configured to execute an encryption algorithm on the write address to obtain first seed data, execute a first scrambling process on the initial write data according to the first seed data to generate first scrambled data, and execute a second scrambling process on the first scrambled data according to common seed data, so as to generate encrypted write data (Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example);
wherein the memory controlling circuit is configured to write the encrypted write data into the memory unit according to the write address (Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example).
Hassan did not explicitly teach that the encryption algorithm [for generating the first seed data based on the write address] is a cyclic redundancy check (CRC) algorithm, where the encryption and decryption circuit includes a CRC encoder.
Lee, in a very similar encryption environment, taught using a CRC generator on the address to produce the seed for encrypting the data to be read or written to flash memory (Lee Paragraph 0049 for example).
It would have been obvious to the person having ordinary skill in the art before the effective filing date of the invention to have employed the teachings of Lee in the data encryption system of Hassan by utilizing a CRC on the address to generate the tweak value. This would have been obvious because the person having ordinary skill in the art would have been motivated to provide more variation in the tweak values between consecutive addresses to possibly improve the life of the data in consecutive rows of the memory.
Regarding claim 9, Hassan disclosed a data encryption and decryption method, applicable to a data access system including a memory controlling circuit and a memory unit (Hassan Fig. 1 and Paragraphs 0029-0035 for example), and the data encryption and decryption method comprising:
executing a write operation, including:
receiving initial write data and a write address output by a host (Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example), wherein the write address comprises an address field with at least one address bytes that specifies a memory address on which the write operation is executed, such that the encryptions implemented for different memory addresses are unique (Hassan Figs. 2 and Paragraph 0037 for example);
executing an encryption algorithm on the write address to obtain first seed data (Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example),
executing a first scrambling process on the initial write data according to the first seed data to generate first scrambled data(Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example), and
executing a second scrambling process on the first scrambled data according to common seed data to generate encrypted write data (Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example); and
writing the encrypted write data into the memory unit according to the write address by the memory controlling circuit (Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example).
Hassan did not explicitly teach that the encryption algorithm [for generating the first seed data based on the write address] is a cyclic redundancy check (CRC) algorithm, where the encryption and decryption circuit includes a CRC encoder.
Lee, in a very similar encryption environment, taught using a CRC generator on the address to produce the seed for encrypting the data to be read or written to flash memory (Lee Paragraph 0049 for example).
It would have been obvious to the person having ordinary skill in the art before the effective filing date of the invention to have employed the teachings of Lee in the data encryption system of Hassan by utilizing a CRC on the address to generate the tweak value. This would have been obvious because the person having ordinary skill in the art would have been motivated to provide more variation in the tweak values between consecutive addresses to possibly improve the life of the data in consecutive rows of the memory.
Regarding claim 15, Hassan disclosed a data encryption and decryption method, applicable to a data access system including a memory controlling circuit and a memory unit (Hassan Fig. 1 and Paragraphs 0029-0035 for example), and the data encryption and decryption method comprising:
executing a read operation, including:
receiving a read address of the read operation output from the host (Hassan Figs. 1, , and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example), wherein the read address comprises an address field with at least one address bytes that specifies a memory address on which the read operation is executed, such that the encryptions implemented for different memory addresses are unique (Hassan Figs. 2 and Paragraph 0037 for example);
obtaining encrypted read data from the memory unit according to the read address (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example);
executing a second scrambling process on the encrypted read data according to a common seed data to generate first read data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example);
executing the encryption algorithm on the read address to obtain second seed data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example); and
executing a first scrambling process on the first read data according to the second seed data to generate decrypted read data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example); and
outputting the decrypted read data to the host (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example).
Hassan did not explicitly teach that the encryption algorithm [for generating the first seed data based on the read address] is a cyclic redundancy check (CRC) algorithm, where the encryption and decryption circuit includes a CRC encoder.
Lee, in a very similar encryption environment, taught using a CRC generator on the address to produce the seed for encrypting the data to be read or written to flash memory (Lee Paragraph 0049 for example).
It would have been obvious to the person having ordinary skill in the art before the effective filing date of the invention to have employed the teachings of Lee in the data encryption system of Hassan by utilizing a CRC on the address to generate the tweak value. This would have been obvious because the person having ordinary skill in the art would have been motivated to provide more variation in the tweak values between consecutive addresses to possibly improve the life of the data in consecutive rows of the memory.
Regarding claim 2, Hassan and Lee taught that the memory controlling circuit is configured to receive a read address of a read operation generated by the host, and obtain initial encrypted read data from the memory unit according to the read address (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example); and the encryption and decryption circuit is configured to: execute the second scrambling process on the initial encrypted read data according to the common seed data to generate first read data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example); execute the encryption algorithm on the read address to obtain second seed data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example); execute the first scrambling process on the first read data according to the second seed data to generate decrypted read data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example); and output the decrypted read data to the host (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example).
Regarding claim 4, Hassan and Lee taught that the first scrambling process is a first XOR algorithm, and the second scrambling process is a second XOR algorithm (Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example – note that AES falls under the scope of “an XOR algorithm”).
Regarding claim 5, Hassan and Lee taught that in response to the memory address indicated by the read address and the write address being the same, the decrypted read data generated in the read operation that is performed after the write operation is the same as the initial write data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example).
Regarding claim 6, Hassan and Lee taught that the host and the data encryption and decryption system are configured to jointly execute the writing operation and the reading operation according to a communication protocol and a system frequency signal (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0057, 0126-0157, and 0176-0177 for example); and wherein, the system frequency signal has a predetermined period, and the encryption algorithm, the first scrambling process and the second scrambling process are executed within the predetermined period corresponding to the system frequency signal (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0057, 0126-0157, and 0176-0177 for example).
Regarding claim 7, Hassan and Lee taught that the common seed data is unique firmware seed data (Hassan Paragraphs 0028 and 0037 for example).
Regarding claim 8, Hassan and Lee taught that the memory unit has a plurality of blocks corresponding to a plurality of memory addresses, respectively, and the plurality of memory addresses are respectively used to generate different and unique records of first seed data in the write operation, and are respectively used to generate different and unique records of the second seed data in the read operation (Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example).
Regarding claim 10, Hassan and Lee taught executing a read operation, including: receiving a read address of the read operation output from the host (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example); obtaining initial encrypted read data from the memory unit according to the read address (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example); executing the second scrambling process on the initial encrypted read data according to the common seed data to generate first read data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example), executing the encryption algorithm on the read address to obtain second seed data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example), and executing the first scrambling process on the first read data according to the second seed data to generate decrypted read data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example); and outputting the decrypted read data to the host (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example).
Regarding claim 11, Hassan and Lee taught that the first scrambling process is a first XOR algorithm, and the second scrambling process is a second XOR algorithm (Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example – note that AES falls under the scope of “an XOR algorithm”).
Regarding claim 12, Hassan and Lee taught that in response to the memory address indicated by the read address and the write address being the same, the first seed data is the same as the second seed data, the decrypted read data generated in the read operation that is performed after the write operation is the same as the initial write data (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0126-0157, and 0176-0177 for example).
Regarding claim 13, Hassan and Lee taught that the host and the data access system are configured to jointly execute the write operation and the read operation jointly according to a communication protocol and a system clock signal; wherein, the system frequency signal has a predetermined period, and the encryption algorithm, the first scrambling process and the second scrambling process are executed within the predetermined period corresponding to the system frequency signal (Hassan Figs. 1, 8, and 14 and Paragraphs 0029-0035, 0036-0038, 0057, 0126-0157, and 0176-0177 for example).
Regarding claim 14, Hassan and Lee taught that the memory unit has a plurality of storage blocks corresponding to a plurality of memory addresses, respectively, and the plurality of memory addresses are respectively used to generate different and unique records of first seed data in the write operation, and are respectively used to generate different and unique records of the second seed data in the read operation (Hassan Figs. 1, 3, and 6 and Paragraphs 0029-0035, 0036-0038, and 0083-0125 for example).
Regarding claims 16-18, Hassan did not explicitly state that the host and the memory controlling circuit operate according to a bus protocol and that the decrypted read/encrypted write data is generated that complies with a timing of the bus protocol. Hassan did very clearly show that the data being read and written from and to the memory is done so over a bus as can be seen in Fig. 1 and Paragraph 0030.
The examiner notes that in Hassan, there is no teaching of a buffer between the encrypt/decrypt accelerator device 108 and the bus 106, and as such the timing of the data being input/output from the bus must be compliant with the timing of the bus protocol or the data would not successfully traverse the bus.
Official Notice: It was well known before the effective filing date that buses operate according to bus protocols which include proper timing requirements for transmission of data over the bus to be successful. As such, it would have been obvious to the person having ordinary skill in the art before the effective filing date of the invention that the processor and the external operate according to a bus protocol for communicating over the bus and that the data traversing the bus most comply with timing of the bus protocol. This would have been obvious because the person having ordinary skill in the art would have been motivate to ensure that the data would successfully traverse the bus.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hassan and Lee, and further in view of Kloth (US Patent Application Publication Number 2021/0312057).
Regarding claim 3, while Hassan and Lee taught a generic system for protecting the contents of flash memory, they did not explicitly teach that the memory unit is a serial peripheral interface (SPI) flash memory, and the memory controlling circuit is an SPI flash memory controlling circuit coupled to the host through an advanced extensible interface (AXI).
Kloth taught that boot code can be stored in a memory unit that is a serial peripheral interface (SPI) flash memory, and a memory controlling circuit for accessing the flash memory is an SPI flash memory controlling circuit coupled to the host through an advanced extensible interface (AXI) (Kloth Paragraphs 0043, 0045, 0054. And 0455 for example).
It would have been obvious to the person having ordinary skill in the art before the effective filing date to have employed the memory encryption system of Hassan in a boot processing system similar to Kloth. This would have been obvious because the person having ordinary skill in the art would have been motivated to protect boot code stored to and read from SPI Flash Memory from illicit access or changes.
Conclusion
Claims 1-18 have been rejected.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2017/0063532 taught a system which uses AES-XTS to encrypt data written to memory in which the seed may be generated out of physical address of the memory request to provide spatial uniqueness.
US 2021/0115286 taught an encrypted flash memory system which generated a seed from the address of the write/read and used the seed to encrypt/decrypt the data.
US 2015/0169472 taught an encrypted flash memory system which generated a seed from the address of the write/read and used the seed to encrypt/decrypt the data.
US 2021/0165746 taught an encrypted flash memory system which generated a seed from the address of the write/read and used the seed to encrypt/decrypt the data.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW T HENNING whose telephone number is (571)272-3790. The examiner can normally be reached Monday-Friday 9AM-3PM EST.
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/MATTHEW T HENNING/Primary Examiner, Art Unit 2491
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