Prosecution Insights
Last updated: September 25, 2026
Application No. 18/359,068

SEMICONDUCTOR DEVICE, BATTERY PACK, METHOD OF CONTROLLING SEMICONDUCTOR DEVICE, AND CONTROL PROGRAMS

Non-Final OA §101§102§103§112
Filed
Jul 26, 2023
Priority
Aug 03, 2022 — JP 2022-123755
Examiner
INSTONE, NATHANIEL JOSEPH
Art Unit
Tech Center
Assignee
Renesas Electronics Corporation
OA Round
1 (Non-Final)
63%
Grant Probability
Moderate
1-2
OA Rounds
4m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 63% of resolved cases
63%
Career Allowance Rate
22 granted / 35 resolved
+2.9% vs TC avg
Strong +26% interview lift
Without
With
+26.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
37 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§101
3.0%
-37.0% vs TC avg
§103
61.7%
+21.7% vs TC avg
§102
24.7%
-15.3% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 35 resolved cases

Office Action

§101 §102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 5-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/1/2026. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim 16 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of the “control program for causing a computer to perform” of claim 16 encompasses signals per se. A standalone control or computer program, detached from any physical structural implementation like a computer-readable medium or specific hardware system does not qualify as a statutory process, machine, manufacture, or composition of matter. See MPEP 2106.03(I). It is suggested that claim 16 be amended to recite a “non-transitory computer readable medium”, such as it is cited in the specification, to overcome this rejection. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation “when operation mode is calibration mode of the calibration mode and normal operation mode” is unclear and confusing. The relationship between the system configuration and operational states of the machine cannot be determined. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tatsuya JP 2017067627 (hereinafter Tat). With regards to claims 1 and 14-16 Tatsuya discloses, a semiconductor device [fig 1 control device 3] comprising: a current measurement circuit [current sensor 41 and self-consumption calculation unit 33] configured to measure a current value of a first current supplied from a battery to the semiconductor device [¶12 discloses an external consumption current A2 from the battery 2 to the control device 3] that is a host device and a current value of a second current supplied from the battery to a load [¶12 discloses total current A1 from the battery 2 to the load 6]; and a computing circuit [integration calculation unit 32] configured to calculate a remaining capacity of the battery, based on an accumulation value of the first current and an accumulation value of the second current in a period from start of discharging to end of discharging in the battery [¶14 discloses remaining charge amount calculation unit 34 calculates the remaining charge amount of the battery 2]. Claims 14-16 are rejected for similar reasons as claim 1 above, a detailed discussion is avoided for brevity. With regards to claim 2 Tat discloses, the semiconductor device according to claim 1, further comprising a storage circuit configured to store information about a charge rate of the battery in accordance with an output voltage of the battery [¶13 discloses a computer program within the control device 3, which requires some form of storage and reads on the claimed storage circuit], wherein the computing circuit calculates the remaining capacity of the battery [remaining charge amount calculation unit 34], based on, in addition to the accumulation value of the first current and the accumulation value of the second current in the period from the start of discharging to the end of discharging in the battery [¶12 above], a charge rate of the battery [¶42 “remaining charge (charge rate)”] extracted from the storage circuit in accordance with an output voltage of the battery at the start of discharging in the battery [¶25 discloses the discharge process where voltage Vb of battery 2 and full charge calculation unit 31 determine the full charge amount which reasonably reads on the start of discharging] and a charge rate of the battery extracted from the storage circuit in accordance with an output voltage of the battery at the end of discharging in the battery [¶30 discloses the remaining charge amount falls below a predetermined amount which reasonably reads on the end of discharging]. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tatsuya JP 2017067627 (hereinafter Tat) in view of Ono et al. US 20220060030 further in view of Tenorio US 20220302719 (hereinafter Ten). With regards to claim 3 Tat fails to disclose, the semiconductor device according to claim 1, wherein the current measurement circuit includes: a first resistance element provided between a first external terminal to which an output voltage of the battery is supplied and a high-potential-side terminal of a power supply circuit configured to generate an operating voltage of an internal circuit of the semiconductor device. However, Ono discloses, a first resistance element provided between a first external terminal to which an output voltage of the battery is supplied and a high-potential-side terminal of a power supply circuit configured to generate an operating voltage of an internal circuit of the semiconductor device [fig 1 current measuring unit 13 and power supply system 10]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the battery management systems of Tat with Ono to include a current measuring circuit in order to measure the energy consumption of the system. Tat fails to disclose, an AD converter configured to detect a potential difference between both ends of the first resistance element, wherein a current value in accordance with a result of detection made by the AD converter is used as a result of measurement made by the current measurement circuit indicating the current value of the first current. However, Ten discloses, an AD converter configured to detect a potential difference between both ends of the first resistance element, wherein a current value in accordance with a result of detection made by the AD converter is used as a result of measurement made by the current measurement circuit indicating the current value of the first current [fig 31 and ¶288 disclose an over-current protection circuit with resistor 2104 feeding into a comparator 3108]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the battery systems of Tat with Ten to include the current sensing circuit in order to measure the energy consumption of the system. With regards to claim 13 the combination discloses, the semiconductor device according to claim 3, further comprising: a comparator circuit configured to compare potentials at both ends of the first resistance element [Ten fig 31 comparator 3108 and resistor 3104]; and a protection circuit configured to protect the semiconductor device from at least either overvoltage or overcurrent supplied from the battery when a result of comparison indicating that a potential difference between both ends of the first resistance element is equal to or larger than a threshold value is output from the comparator circuit [Ten fig 31 and ¶288 disclose the over-current protection circuit via resistor 3104 and comparator 3108 to determine when a threshold is exceeded]. Allowable Subject Matter Claim 4 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art alone or in combination fails to disclose, “a second external terminal connected to the other terminal of the first resistance element, the other terminal being different from one terminal of the first resistance element connected to the first external terminal, and also to the high-potential-side terminal of the power supply circuit, wherein the semiconductor device is configured so that a reference current flows from the first external terminal via the first resistance element to the second external terminal when operation mode is calibration mode of the calibration mode and normal operation mode”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nathaniel Instone whose telephone number is (571)272-1563. The examiner can normally be reached M-F 8-4 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julian Huffman can be reached at 571-272-2147. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHAN J INSTONE/Examiner, Art Unit 2859 /JULIAN D HUFFMAN/Supervisory Patent Examiner, Art Unit 2859
Read full office action

Prosecution Timeline

Jul 26, 2023
Application Filed
Sep 04, 2026
Non-Final Rejection mailed — §101, §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
63%
Grant Probability
89%
With Interview (+26.2%)
3y 7m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 35 resolved cases by this examiner. Grant probability derived from career allowance rate.

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