DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on June 15, 2026, has been entered. Applicant’s amendments to the specifications and drawings have overcome each and every objection and 35 USC § 112 rejection previously set forth in the Non-Final Office Action mailed March 13, 2026, hereafter referred to as the Non-Final Office Action.
Response to Arguments
Applicant's arguments filed June 15, 2026 have been fully considered but they are not persuasive.
Applicant’s first argument regard to claim 1 is that Daruwalla does not disclose the claimed first and second transistors receiving the same radio-frequency signal because transistors T1 and T’1 receive different RF signals.
This argument is not persuasive. As disclose in Daruwalla, paragraph [0050], during high-gain (HG) operation, the HG path receives an input RF signal and feeds the signal to the LNA circuit. During low-gain (LG) operation, the LG path receives the same input RF signal, routed through a different switch path, and feeds an attenuated version of that signal to LNA circuit. “during operation in the high gain mode, the HG path may take an input RF signal (e.g., one of RFM1, ...., RFMk) switched through a throw of the switch (112a) and feed unattenuated as RFNa to the LNA circuit (100a). On the other hand, during operation in the low gain mode, the LG path may take the same input RF signal (e.g., one of RFM1, ...., RFMk) switched through a different throw (not shown in FIG. 2B) of the switch (112a)”. Thus, as discussed in the office action, transistors T1 operates in the HG path and T’1 operates in the LG path, both transistors are configured to receive the same input RF signal.
Applicant’s second argument regard to claim 19 is that Aryanci's LNA's do not receive the same radio frequency signal.
This argument is not persuasive. Ayranci discloses in Fig. 2A that LNAs 203, 209, and 708 receive RF input signals at nodes 202, 204, and 206 respectively. Ayranci further teaches that input switch 241 selectively couples one of a plurality of input filters 243 to the circuit inputs (column 7, lines 1-16). Thus, the amplifying stages receive a radio-frequency input signal selectively applied from the receiver input. Accordingly, Ayranci teaches the claimed amplifying stages configured to receive the radio-frequency signal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5, 6, 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Daruwalla et al (US 20210083631 A1) in view of Kathiresan et al (US 20100321113 A1).
Regarding claim 1, Daruwalla (Fig. 11A) discloses an amplifier circuit comprising a first transistor (T1) having a gate terminal configured to receive a radio-frequency signal (RF_51), a drain terminal coupled toward an output port through a cascode transistor (T2, paragraph [0088], lines 5 and 6) and output network (Cout) and a degeneration inductor (LDEG) coupled to the source terminal of the first transistor T1.
A second input transistor (T’1) having a gate terminal configured to receive a radio-frequency signal (RF52) and having a source degeneration inductor (L’DEG) and a drain terminal.
However, Daruwalla does not disclose the configuration required by claim 1 in which the third and fourth transistors having respective source terminals coupled to the outport and a source terminal coupled to the drain terminal of the second transistor as claimed.
Kathiresan (Fig. 2) discloses a radio frequency (RF) amplifier including an RF input transistor (M1) whose drain is coupled to a common node. That common node is coupled to the source of cascode transistor M3 (paragraph [0002], lines 6 and 7) and to the source of additional transistor M5. Thus, Kathiresan teaches a configuration in which the drain of an RF input transistor is coupled to the sources of two transistors and a node may be coupled to a plurality of transistor terminals in a branching configuration (ex: transistors M3 and M5 sharing a common node).
It would have been obvious to modify Daruwalla to include Kathiresan’s transistors M3 and M5 as Daruwalla’s third and fourth transistors, having a source terminal coupled to the drain terminal of transistor T’1 and a drain terminal coupled to the upper/output portion of the amplifier circuit that goes upward toward transistor T2 in Daruwalla; as taught by Kathiresan’s branching configuration, thereby, providing multiple transistor branches coupled to the same intermediate node. This combination yields an amplifier circuit in which the drain of the second transistor is coupled to the source terminals of both the third and fourth transistors as claimed. Incorporating third and fourth transistors from
Regarding claim 5, the resultant combination of Daruwalla as modified by Kathiresan teaches the claimed invention except the second transistor and the third transistor form a first amplifying cascode.
Daruwalla teaches stacked transistors forming a cascode configuration (page 10, paragraph [0088]), and Kathiresan similarly teaches a cascode transistor M3 (page 1, paragraph [0002]). A person of ordinary skill in the art would recognize the stacked transistor arrangement forms a cascode.
It would have been further obvious to one of ordinary skill in the art to configure the second and third transistors in a cascode arrangement because cascode configurations are well known in the art to improve gain and bandwidth and to reduce Miller effect, thereby enhancing amplifier performance.
Regarding claim 6, as an obvious consequence of the above modification, the resultant combination of Daruwalla as modified by Kathiresan teaches the claimed invention further including a fifth transistor having a drain terminal coupled to the output port and a source terminal coupled to the drain terminal of the first transistor.
Daruwalla (Fig. 11A) discloses a fifth transistor (T2) having a source terminal of the first transistor (T1) and a drain terminal coupled to the output portion of the amplifier circuit, via the upper/output path including Cout and RFout, thereby meeting the claimed fifth transistor limitation. Accordingly, the combination of Daruwalla and Kathiresan teaches the claimed subject matter of claim 6.
Regarding claim 7, as an obvious consequence of the above modification, the resultant combination of Daruwalla as modified by Kathiresan teaches the claimed invention further including wherein the first transistor and the fifth transistor form a second amplifying cascode.
Daruwalla (Fig.11A) discloses that transistor T1 has it’s drain couple to the source of the upper stacked transistor (T2), and the drain of that upper transistor is coupled to the output node (RFout). This stacked transistor arrangement necessarily forms a cascode amplifier stage, thereby meeting the limitation that the first transistor and the fifth transistor form a second amplifying cascode as set forth in claim 7.
Regarding claim 10, as an obvious consequence of the above modification, the resultant combination of Daruwalla as modified by Kathiresan teaches the claimed invention further including wherein the fourth transistor has a gate terminal and the gate terminal of the first transistor, the gate terminal of the second transistor, and the gate terminal of the fourth transistor are each configured to receive a different bias voltage.
Daruwalla teaches separate biasing of stacked transistors and adjustable voltage level depending on implementation and already uses biasing (bias1, bias1’) for stacked devices. Also, separate biasing circuits (ex: 1000b, 1000b’) configured to provide respective bias voltages to the gate terminals of T1 and T’1. Kathiresan further discloses independent bias voltages applied to the gate terminals of its transistors M3 and M5, thereby meeting the claimed limitations of claim 10.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ayranci et al (US 12184248 B2) in view of Mehrjoo et al (US 20180175806 A1)
Ayranci (Fig. 7) discloses a first amplifying stage (LNA1 203) configured to receive an RF signal and provide an amplified output at node 208; a second amplifying stage (LNA2 209) configured to receive an RF signal and provide an amplified output at node 210; and a third amplifying stage (LNA3 706) configured to receive an RF signal and provide an amplified output at node 710. Ayranci further discloses an output network coupled to the third amplifying stage (ex: node 710 and output port 720), including reactive components (i.e. inductor and capacitor) thereby forming a frequency-selective network. Such a network constitutes a filter circuit coupled to the third amplifying stage, as recited.
Mehrjoo (Fig. 5) discloses a common source LNA topology 550, coupled to a low noise amplifier for suppressing intermodulation distortion (paragraphs [0006] – [0008]). Circuit 550 also generates third-order intermodulation distortion (IM3) components due to nonlinear amplification. Mehrjoo further discloses that within circuit 550, post distortion cancellation blocks 510H and 510L generate IM3 currents with opposite phase to cancel the IM3 generated by the LNA. Since IM3 is a type of intermodulation distortion, cancellation of IM3 constitutes suppression of IMD (page 5, paragraphs [0058] and [0059]).
It would have been obvious to one of ordinary skill in the art to incorporate Mehrjoo’s distortion suppression circuitry into Ayranci’s amplifier, such as coupling the suppression circuitry to the second amplifying stage (LNA2 209) at node 210 (Ayranci, column 7, line 40), because nonlinear RF amplifier stages generate intermodulation distortion in the amplified output signal. Accordingly, by placing the distortion suppression circuitry at node (210) of the amplifier output would optimal in reducing distortion and improve linearity of the multi-stage RF amplifier.
Allowable Subject Matter
Claims 2, 3, 4, 8, 9, 11 - 13, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests the second transistor is a transistor of a first type and the fourth transistor is a transistor of a second type different from the first type.
Claims 3 and 4 depend upon claim 2.
Regarding claim 8, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests a first variable capacitor having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to the source terminal of the first transistor.
Claim 9 depends upon claim 8.
Regarding claim 11, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests the first transistor forms a first amplifying stage, the second transistor and the third transistor form a second amplifying stage, and the fourth transistor forms an intermodulation distortion suppression circuit.
Regarding claim 12, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests a fifth transistor having a gate terminal configured to receive the radio- frequency signal, a drain terminal coupled to the output port, and a source terminal; and an additional degeneration inductor coupled to the source terminal of the fifth transistor.
Claim 13 depends upon claim 12.
Regarding claim 20, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests the second amplifying stage includes a first amplification transistor having a drain terminal, the intermodulation distortion suppression circuit is coupled to the drain terminal of the first amplification transistor, the third amplifying stage includes a second amplification transistor having a drain terminal, the filter circuit comprises an n-path filter, and the n-path filter is coupled to the drain terminal of the second amplification transistor.
The following is an examiner’s statement of reasons for allowance: Claims 14-18 are allowed
Regarding claim 14: None of the prior art, made of record, singularly or in combinations, teaches or fairly suggests a first transistor having a gate terminal configured to receive a radio- frequency signal, a drain terminal coupled to an output port of the amplifier circuitry, and a source terminal; a degeneration inductor coupled to the source terminal of the first transistor; a second transistor having a gate terminal configured to receive the radio- frequency signal and a drain terminal; a third transistor having a drain terminal coupled to the output port and a source terminal coupled to the drain terminal of the second transistor; and an n-path filter coupled to the drain terminal of the second transistor.
Claims 15-18 are allowed because they depend upon claim 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATASHA Y MARANO whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
NATASHA Y. MARANO
Examiner
Art Unit 2843
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