Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/26/2023 was filed and entered into the record for application examined in art unit 2843. The submission is in compliance with the provisions with 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0036], line 5, the specifications refer to “front end module 40” in Fig. 3; However, such label does not appear in Fig. 3 and thus renders such labels vague in meaning.
Paragraph [0047], line 5, and paragraph [0048], line 2, and line 5, the specifications refer to “network 54” in Fig. 4; However, such label does not appear in Fig. 4 and thus renders such labels vague in meaning.
Paragraph [0081], line 1, and paragraph [0087], line 1, the specifications refer to “circuitry 18” in Fig. 6; However, such label does not appear in Fig. 6 and thus renders such labels vague in meaning.
Paragraph [0081], line 4, and paragraph [0087], line 6, and line 9, the specifications refer to “module 40” in Fig. 6; However, such label does not appear in Fig. 6 and thus renders such labels vague in meaning.
Paragraph [0085], line 3, the specifications refer to “circuit 58” in Fig. 6; However, such label does not appear in Fig. 6 and thus renders such labels vague in meaning.
Paragraph [0087], line 2, the specifications refer to “processors 26” in Fig. 6; However, such label does not appear in Fig. 6 and thus renders such labels vague in meaning.
Paragraph [0087], line 3, the specifications refer to “circuitry 24” in Fig. 6; However, such label does not appear in Fig. 6 and thus renders such labels vague in meaning.
Paragraph [0066], line 3, the specifications refer to “amplifier 52” in Fig. 5; However, these elements are not present in Fig. 5. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Paragraph [0072], line 8, the specifications refer to “amplifier 52” in Fig. 5; However, these elements are not present in Fig. 5. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Paragraph [0073], line 1, and line 2, the specifications refer to “amplifier 52” in Fig. 5; However, these elements are not present in Fig. 5. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Paragraph [0077], line 1, line 2, and line 5, the specifications refer to “amplifier 52” in Fig. 5; However, these elements are not present in Fig. 5. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Paragraph [0078], line 3, the specifications refer to “amplifier 52” in Fig. 5; However, these elements are not present in Fig. 5. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Paragraph [0079], line 2, and in paragraph [0090], line2, line 3, and line 10-11, the specifications refer to “amplifier 52” in Figures 3 - 5; However, these elements are not present in Fig. 5. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Paragraph [0081], line, 4 and line 5, the specifications refer to “amplifier 52” in Fig. 6; However, these elements are not present in Fig. 6. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Paragraph [0083], twice in line 1, and once in line 4, and line 6, the specifications refer to “amplifier 52” in Fig. 5; However, these elements are not present in Fig 5. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Paragraph [0085], twice in line 1 and once in line 5, the specifications refer to “amplifier 52” in Fig. 5; However, these elements are not present in Fig. 5. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Paragraph [0087], line 3, twice in line 6, and twice in line 9, the specifications refer to “amplifier 52” in Fig. 5; However, these elements are not present in Fig. 5. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Paragraph [0089], twice in line 1, and once in line 4, the specifications refer to “amplifier 52” in Fig. 5; However, these elements are not present in Fig. 5. Instead, the elements are depicted in Fig. 2, 3, and 4, which needs to be correspondingly described in the detail description of the specification.
Appropriate correction is required.
Drawings
The drawing, figure 5 is objected to because figure 5 fails to have amplifier 52 properly labeled as described in the specification, such as in paragraph [0083].
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 6, 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Daruwalla et al (US 20210083631 A1) in view of Kathiresan et al (US 20100321113 A1).
Daruwalla (Fig. 11A) discloses an amplifier circuit comprising a first transistor (T1) having a gate terminal configured to receive a radio-frequency signal (RF_51), a drain terminal coupled toward an output port through a cascode transistor (T2, paragraph [0088], lines 5 and 6) and output network (Cout) and a degeneration inductor (LDEG) coupled to the source terminal of the first transistor T1.
A second input transistor (T’1) having a gate terminal configured to receive a radio-frequency signal (RF52) and having a source degeneration inductor (L’DEG) and a drain terminal.
However, Daruwalla does not disclose the configuration required by claim 1 in which the third and fourth transistors having respective source terminals coupled to the outport and a source terminal coupled to the drain terminal of the second transistor as claimed.
Kathiresan (Fig. 2) discloses a radio frequency (RF) amplifier including an RF input transistor (M1) whose drain is coupled to a common node. That common node is coupled to the source of cascode transistor M3 (paragraph [0002], lines 6 and 7) and to the source of additional transistor M5. Thus, Kathiresan teaches a configuration in which the drain of an RF input transistor is coupled to the sources of two transistors and a node may be coupled to a plurality of transistor terminals in a branching configuration (ex: transistors M3 and M5 sharing a common node).
It would have been obvious to modify Daruwalla to include Kathiresan’s transistors M3 and M5 as Daruwalla’s third and fourth transistors, having a source terminal coupled to the drain terminal of transistor T’1 and a drain terminal coupled to the upper/output portion of the amplifier circuit that goes upward toward transistor T2 in Daruwalla; as taught by Kathiresan’s branching configuration, thereby, providing multiple transistor branches coupled to the same intermediate node. This combination yields an amplifier circuit in which the drain of the second transistor is coupled to the source terminals of both the third and fourth transistors as claimed. Incorporating third and fourth transistors from a known RF amplifier configuration to obtain predictable gain, linearity, and biasing performance known to one of ordinary skill in the art.
Regarding claim 5, the resultant combination of Daruwalla as modified by Kathiresan teaches the claimed invention except the second transistor and the third transistor form a first amplifying cascode.
Daruwalla teaches stacked transistors forming a cascode configuration (page 10, paragraph [0088]), and Kathiresan similarly teaches a cascode transistor M3 (page 1, paragraph [0002]). A person of ordinary skill in the art would recognize the stacked transistor arrangement forms a cascode.
It would have been further obvious to one of ordinary skill in the art to configure the second and third transistors in a cascode arrangement because cascode configurations are well known in the art to improve gain and bandwidth and to reduce Miller effect, thereby enhancing amplifier performance.
Regarding claim 6, as an obvious consequence of the above modification, the resultant combination of Daruwalla as modified by Kathiresan teaches the claimed invention further including a fifth transistor having a drain terminal coupled to the output port and a source terminal coupled to the drain terminal of the first transistor.
Daruwalla (Fig. 11A) discloses a fifth transistor (T2) having a source terminal of the first transistor (T1) and a drain terminal coupled to the output portion of the amplifier circuit, via the upper/output path including Cout and RFout, thereby meeting the claimed fifth transistor limitation. Accordingly, the combination of Daruwalla and Kathiresan teaches the claimed subject matter of claim 6.
Regarding claim 7, as an obvious consequence of the above modification, the resultant combination of Daruwalla as modified by Kathiresan teaches the claimed invention further including wherein the first transistor and the fifth transistor form a second amplifying cascode.
Daruwalla (Fig.11A) discloses that transistor T1 has it’s drain couple to the source of the upper stacked transistor (T2), and the drain of that upper transistor is coupled to the output node (RFout). This stacked transistor arrangement necessarily forms a cascode amplifier stage, thereby meeting the limitation that the first transistor and the fifth transistor form a second amplifying cascode as set forth in claim 7.
Regarding claim 10, as an obvious consequence of the above modification, the resultant combination of Daruwalla as modified by Kathiresan teaches the claimed invention further including wherein the fourth transistor has a gate terminal and the gate terminal of the first transistor, the gate terminal of the second transistor, and the gate terminal of the fourth transistor are each configured to receive a different bias voltage.
Daruwalla teaches separate biasing of stacked transistors and adjustable voltage level depending on implementation and already uses biasing (bias1, bias1’) for stacked devices. Also, separate biasing circuits (ex: 1000b, 1000b’) configured to provide respective bias voltages to the gate terminals of T1 and T’1. Kathiresan further discloses independent bias voltages applied to the gate terminals of its transistors M3 and M5, thereby meeting the claimed limitations of claim 10.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ayranci et al (US 12184248 B2) in view of Mehrjoo et al (US 20180175806 A1)
Ayranci (Fig. 7) discloses a first amplifying stage (LNA1 203) configured to receive an RF signal and provide an amplified output at node 208; a second amplifying stage (LNA2 209) configured to receive an RF signal and provide an amplified output at node 210; and a third amplifying stage (LNA3 706) configured to receive an RF signal and provide an amplified output at node 710. Ayranci further discloses an output network coupled to the third amplifying stage (ex: node 710 and output port 720), including reactive components (i.e. inductor and capacitor) thereby forming a frequency-selective network. Such a network constitutes a filter circuit coupled to the third amplifying stage, as recited.
Mehrjoo (Fig. 5) discloses a common source LNA topology 550, coupled to a low noise amplifier for suppressing intermodulation distortion (paragraphs [0006] – [0008]). Circuit 550 also generates third-order intermodulation distortion (IM3) components due to nonlinear amplification. Mehrjoo further discloses that within circuit 550, post distortion cancellation blocks 510H and 510L generate IM3 currents with opposite phase to cancel the IM3 generated by the LNA. Since IM3 is a type of intermodulation distortion, cancellation of IM3 constitutes suppression of IMD (page 5, paragraphs [0058] and [0059]).
It would have been obvious to one of ordinary skill in the art to incorporate Mehrjoo’s distortion suppression circuitry into Ayranci’s amplifier, such as coupling the suppression circuitry to the second amplifying stage (LNA2 209) at node 210 (Aryanci, column 7, line 40), because nonlinear RF amplifier stages generate intermodulation distortion in the amplified output signal. Accordingly, by placing the distortion suppression circuitry at node (210) of the amplifier output would optimal in reducing distortion and improve linearity of the multi-stage RF amplifier.
Allowable Subject Matter
Claims 2, 3, 4, 8, 9, 11 - 13, 14 -18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATASHA Y MARANO whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 9:30am - 5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATASHA Y. MARANO
Examiner
Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843