DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Swanson et al. (US 2006/0196535 A1).
Regarding claim 20, Swanson discloses a surface-mountable solar cell (fig. 2) (solar cell module 100 is a terrestrial solar cell module that is mounted on a surface, [0018]) comprising:
a semiconductor layer (n-type silicon wafer 203, fig. 2 and [0021]) having a first doped region (P-type doped regions 204) at a first side (bottom side) of the semiconductor layer (203) and a second doped region (n-type front side diffusion region 207) (fig. 2 and [0024]) at a second side (top side) of the semiconductor layer (203), the first side (bottom side) opposing the second side (top side),
the semiconductor layer (203) configured to convert solar radiation to electrical energy, the second side (top side) configured to face the solar radiation (see fig. 2 and [0020] – “The materials on the front side of the solar cell 200 are transparent by nature or thickness to allow solar radiation to shine through”);
a coverglass layer (transparent cover that is made of glass, [0018]) coupled to the second side (top side) via a bond (encapsulant 103-2 that is made EVA to promote adhesion, fig. 2 and [0018-0019]),
the coverglass layer (104) configured to pass the solar radiation to the semiconductor layer (203) and provide structural support for the semiconductor layer (203) (fig. 1 and [0020]); and
a first electrode pad (metal 206 that is connected to p+ region) and a second electrode pad (metal 206 that is connected to n+ region) coupled to the first side (bottom side) and electrically coupled to the semiconductor layer (203) (see fig. 2 and [0022]),
wherein no metal layer is interposed between the semiconductor layer (203) and the coverglass layer (104) (see fig. 2 – layer 207 is made of n-type semiconductor, layers 202 and 201 are made of silicon oxide and silicon nitride, respectively, [0021], encapsulant 103-2 is made of EVA – so there is no metal layer between semiconductor layer 203 and coverglass layer 104).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9 and 11-19 are rejected under 35 U.S.C. 103 as being unpatentable over Youtsey et al. (US 2010/0126573 A1) in view of Swanson et al. (US 2006/0196535 A1) and Chary et al. (US 2017/0345955 A1).
Regarding claim 1, Youtsey et al. discloses a surface-mountable solar cell (solar cell is configured for space or terrestrial application, and thus mounted on a surface of a spacecraft, [0035]) (see figures 2-5) comprising:
a plurality of semiconductor layers (first junction region 210, second junction region 220, and/or third junction region 230, fig. 2) having a first side (bottom side) and a second side (top side), the first side (bottom side) opposing the second side (top side), the plurality of semiconductor layers (210, 220, and/or 230) configured to convert solar radiation to electrical energy ([0033]), the second side (top side) configured to face the solar radiation ([0033]);
a first electrode pad (base contact 250) and a second electrode pad (conductive layer 280) coupled to the first side (bottom side) and electrically coupled to the plurality of semiconductor layers (see fig. 2), and
an antireflection coating (260) on the second side (top side) of the plurality of semiconductor layers (see fig. 2).
Youtsey further discloses the solar cell is configured to be used for space or terrestrial application ([0035]). However, Youtsey is silent as to a coverglass layer coupled to the second side via a bond, the coverglass layer being configured to pass the solar radiation to the plurality of semiconductor layers and provide structural support for the plurality of semiconductor layers; and wherein the coverglass layer is thicker than the plurality of semiconductor layers, and wherein no metal layer is interposed between the plurality of semiconductor layers and the coverglass layer.
Swanson discloses a surface-mountable solar cell (fig. 2) (solar cell module 100 is a terrestrial solar cell module that is mounted on a surface, [0018]) comprising: a semiconductor layer (n-type silicon wafer 203, fig. 2 and [0021]) having a first doped region (P-type doped regions 204) at a first side (bottom side) of the semiconductor layer (203) and a second doped region (n-type front side diffusion region 207) (fig. 2 and [0024]) at a second side (top side) of the semiconductor layer (203), the first side (bottom side) opposing the second side (top side), the semiconductor layer (203) configured to convert solar radiation to electrical energy, the second side (top side) configured to face the solar radiation (see fig. 2 and [0020] – “The materials on the front side of the solar cell 200 are transparent by nature or thickness to allow solar radiation to shine through”); a coverglass layer (transparent cover that is made of glass, [0018]) coupled to the second side (top side) via a bond (encapsulant 103-2 that is made EVA to promote adhesion, fig. 2 and [0018-0019]), the coverglass layer (104) configured to pass the solar radiation to the semiconductor layer (203) and provide structural support for the semiconductor layer (203) (fig. 1 and [0020]); and a first electrode pad (metal 206 that is connected to p+ region) and a second electrode pad (metal 206 that is connected to n+ region) coupled to the first side (bottom side) and electrically coupled to the semiconductor layer (203) (see fig. 2 and [0022]), wherein no metal layer is interposed between the semiconductor layer (203) and the coverglass layer (104) (see fig. 2 – layer 207 is made of n-type semiconductor, layers 202 and 201 are made of silicon oxide and silicon nitride, respectively, [0021], encapsulant 103-2 is made of EVA – so there is no metal layer between semiconductor layer 203 and coverglass layer 104).
Swanson further discloses the coverglass layer (104) is bonded via encapsulant or EVA layer (103-2) to the semiconductor layers to protect the semiconductor layers ([0018]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to have used the coverglass layer as taught by Swanson in the solar cell of Youtsey and bonded to the semiconductor layer via EVA adhesive, as shown by Swanson, such that the semiconductor layers are protected, as shown by Swanson ([0018]).
Youtsey as modified by Swanson discloses that there is there is no metal layer between semiconductor layer and coverglass layer.
However, Youtsey as modified by Swanson does not disclose that the coverglass layer is thicker than the plurality of semiconductor layers
Chary discloses a surface mount solar cell integrated with coverglass (figures 27 and 29A) comprising: a plurality of semiconductor layers (2705/2704) having a first side and a second side, the first side opposing the second side, the plurality of semiconductor layers configured to convert solar radiation to electrical energy, the second side configured to face the solar radiation; a coverglass layer (coverglass 2715) coupled to the second side via a bond
(optically clear adhesive 2714), the coverglass layer (2715) being configured to pass the solar radiation to the plurality of semiconductor layers and provide structural support for the plurality of semiconductor layers; and a first electrode pad (2720) and a second electrode pad (2719) coupled to the first side and electrically coupled to the plurality of semiconductor layers.
Chary further discloses that the coverglass has a thickness of 20-600 µm ([0050]) to protect the solar cell layers from harsh environments ([0050]). Chary further discloses that the semiconductor layers are thinned to less than 20 µm ([0136]) to allow for thinned device to be used in space or terrestrial applications ([0136]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to have used 20-600 µm thick coverglass as taught by Chary to form the transparent cover layer of Youtsey as modified by Swanson such that the solar cell layers are protected from harsh environments, as shown by Chary ([0050]) and also desired by Youtsey as modified by Swanson ([0018] of Swanson).
It would also have been obvious to one of ordinary skill in the art at the time of the invention to have used a thickness of less than 20 µm as taught by Chary to from the semiconductor layers of Youtsey as modified to allow for a thinned device to be used in space or terrestrial applications, as shown by Chary ([0136]) as also desired by Youtsey as modified by Swanson.
Regarding claim 2, Youtsey further discloses that the plurality of semiconductor layers includes sub-cells including at least first sub-cell (210 or 230), a second sub-cell (220), and a third sub-cell (230 or 210), the first sub-cell having a first energy bandgap ([0025]), the second sub-cell having a second energy bandgap ([0025]), and the third sub-cell having a third energy bandgap ([0025]), the first energy bandgap being greater than the second energy bandgap and the third energy bandgap ([0025]).
Regarding claim 3, Youtsey further discloses that the plurality of semiconductor layers
includes Ga, In, As or P ([0025]).
Regarding claim 4, Youtsey further discloses that the first sub-cell is electrically coupled to the second electrode pad (280) by a set of contact vias (290) that partially pass through the first sub-cell (210 or 230), the set of contact vias terminating with an ohmic metallization (240) within the first sub-cell (210 or 230) (fig. 2 and [0027]).
Regarding claim 5, Youtsey further discloses that the first sub-cell (230) is electrically coupled to the second electrode pad (280) by a set of contact vias (290) that partially pass through the first sub-cell (230), the set of through vias (290) being coupled to a transparent conductive layer (layer 210 is a semi-transparent conductive layer as light passes through it to be absorbed by layers 220 and 230) interposed between the plurality of semiconductor layers (220 and 230) and the coverglass layer (as modified by Swanson).
Regarding claim 6, Youtsey further discloses that the transparent conductive layer (210) is deposited on the second side (top side) of the plurality of semiconductor layers (220 and/or 230), and wherein the transparent conductive layer has fingers (380) extending across the second side (top side) of the plurality of semiconductor layers (see fig. 4 that shows the emitter contact pad has plurality of fingers 380).
Regarding claim 7, Youtsey as modified by Swanson further discloses a dielectric layer (260 of figure 2 of Youtsey or 202/201 of Swanson) interposed between the second side of the plurality of semiconductor layers (220 and/or 230) and the coverglass layer (of Swanson).
It is further noted that the limitation “the bond between the second side of the plurality of semiconductor layers and the coverglass layer is formed by a force applied to a dielectric layer interposed between the second side of the plurality of semiconductor layers and the coverglass layer” is a process limitation, which does not further define the structure of the claimed device. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." See MPEP §2113. See also In re Thorpe, 777 F.2d 695, 698,227 USPQ 964, 966 (Fed. Cir. 1985). There is no difference evident between the solar cell of the instant claims and those taught by the prior art as described above.
Regarding claim 8, Youtsey as modified by Swanson further discloses the dielectric layer includes a first dielectric layer portion (202 of Swanson) coupled to the second side (top side) of the plurality of semiconductor layers and a second dielectric layer portion (201 of Swanson) coupled to the coverglass layer (104) (see fig. 2 of Swanson).
It is further noted that the limitation “the bond between the second side of the plurality of semiconductor layers and the coverglass layer is formed by the force applied to the first dielectric layer portion and the second dielectric layer portion interposed between the second side of the plurality of semiconductor layers and the coverglass layer” is a process limitation, which does not further define the structure of the claimed device. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." See MPEP §2113. See also In re Thorpe, 777 F.2d 695, 698,227 USPQ 964, 966 (Fed. Cir. 1985). There is no difference evident between the solar cell of the instant claims and those taught by the prior art as described above.
Regarding claim 9, Youtsey as modified by Chary further discloses that the coverglass layer is 20-200 µm thick ([0050] of Chary), which overlaps with the claimed range of less than 200 µm thick.
Regarding claim 11, Youtsey further discloses a contact metal layer (base contact pad 420, fig. 3) extending across the first side of the plurality of semiconductor layers, the contact metal layer configured to electrically couple to at least one of the first electrode pad or the second electrode pad (370) (see fig. 3).
Regarding claim 12, although Youtsey as modified does not disclose that the surface-mountable solar cell has a mass per area is <0.1 g/cm3, Youtsey as modified by Chary discloses the solar cell is thinned so that it can used for space applications ([0136] of Chary). Thus, it would be obvious to have choose appropriate dimensions of solar cell, and thus weight of the solar cell, so that it can be used for space application.
It is further noted that selection of element’s dimension is considered to be a matter of design choice, depending upon the dimensions and gradient present in the installation site, among other considerations. In the absence of evidence of criticality, selection of dimensions, and thus, the mass, as claimed is considered obvious to one having ordinary skill in the art. Also note that in Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Regarding claim 13, Youtsey as modified by Swanson further discloses an anti-reflective layer (201 and 202, fig. 2 of Swanson) interposed between the plurality of semiconductor layers and the coverglass layer, the anti-reflective layer configured to minimize reflection between the plurality of semiconductor layers and the coverglass layer.
Regarding claim 14, Youtsey as modified by Swanson further discloses anti-reflective layer includes a stack of dielectric layers (201 and 202, fig. 2 of Swanson) and wherein the anti-reflective layer is further configured to reduce reflection of incident light passing through the coverglass layer.
Regarding claim 15, Youtsey as modified by Swanson further discloses an anti-reflective layer (201 and 202, fig. 2 of Swanson) deposited on a bottom side of coverglass layer (see fig. 2 of Swanson), the anti-reflective layer configured to minimize reflection at the coverglass layer.
Regarding claim 16, Youtsey as modified by Swanson further discloses anti-reflective layer includes a stack of dielectric layers (201 and 202, fig. 2 of Swanson) and wherein the anti-reflective layer is further configured to reduce reflection of incident light passing through the coverglass layer.
Regarding claim 17, Youtsey et al. discloses a surface-mountable solar cell (solar cell is configured for space or terrestrial application, and thus mounted on a surface of a spacecraft, [0035]) (see figures 2-5) comprising:
a plurality of semiconductor layers (first junction region 210, second junction region 220, and/or third junction region 230, fig. 2) having a first side (bottom side) and a second side (top side), the first side (bottom side) opposing the second side (top side), the plurality of semiconductor layers (210, 220, and/or 230) configured to convert solar radiation to electrical energy ([0033]), the second side (top side) configured to face the solar radiation ([0033]);
a first electrode pad (base contact 250) and a second electrode pad (conductive layer 280) coupled to the first side (bottom side) and electrically coupled to the plurality of semiconductor layers (see fig. 2), and
an antireflection coating (260) on the second side (top side) of the plurality of semiconductor layers (see fig. 2),
wherein the surface-mountable solar cell is configured to power a non-terrestrial application device (space applications, [0035]) coupled to the surface-mountable solar cell.
Youtsey further discloses the solar cell is configured to be used for space or terrestrial application ([0035]). However, Youtsey is silent as to a coverglass layer coupled to the second side via a bond, the coverglass layer being configured to pass the solar radiation to the plurality of semiconductor layers and provide structural support for the plurality of semiconductor layers; and wherein the coverglass layer is thicker than the plurality of semiconductor layers, and wherein no metal layer is interposed between the plurality of semiconductor layers and the coverglass layer.
Swanson discloses a surface-mountable solar cell (fig. 2) (solar cell module 100 is a terrestrial solar cell module that is mounted on a surface, [0018]) comprising: a semiconductor layer (n-type silicon wafer 203, fig. 2 and [0021]) having a first doped region (P-type doped regions 204) at a first side (bottom side) of the semiconductor layer (203) and a second doped region (n-type front side diffusion region 207) (fig. 2 and [0024]) at a second side (top side) of the semiconductor layer (203), the first side (bottom side) opposing the second side (top side), the semiconductor layer (203) configured to convert solar radiation to electrical energy, the second side (top side) configured to face the solar radiation (see fig. 2 and [0020] – “The materials on the front side of the solar cell 200 are transparent by nature or thickness to allow solar radiation to shine through”); a coverglass layer (transparent cover that is made of glass, [0018]) coupled to the second side (top side) via a bond (encapsulant 103-2 that is made EVA to promote adhesion, fig. 2 and [0018-0019]), the coverglass layer (104) configured to pass the solar radiation to the semiconductor layer (203) and provide structural support for the semiconductor layer (203) (fig. 1 and [0020]); and a first electrode pad (metal 206 that is connected to p+ region) and a second electrode pad (metal 206 that is connected to n+ region) coupled to the first side (bottom side) and electrically coupled to the semiconductor layer (203) (see fig. 2 and [0022]), wherein no metal layer is interposed between the semiconductor layer (203) and the coverglass layer (104) (see fig. 2 – layer 207 is made of n-type semiconductor, layers 202 and 201 are made of silicon oxide and silicon nitride, respectively, [0021], encapsulant 103-2 is made of EVA – so there is no metal layer between semiconductor layer 203 and coverglass layer 104).
Swanson further discloses the coverglass layer (104) is bonded via encapsulant or EVA layer (103-2) to the semiconductor layers to protect the semiconductor layers ([0018]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to have used the coverglass layer as taught by Swanson in the solar cell of Youtsey and bonded to the semiconductor layer via EVA adhesive, as shown by Swanson, such that the semiconductor layers are protected, as shown by Swanson ([0018]).
Youtsey as modified by Swanson discloses that there is there is no metal layer between semiconductor layer and coverglass layer.
However, Youtsey as modified by Swanson does not disclose that the coverglass layer is thicker than the plurality of semiconductor layers
Chary discloses a surface mount solar cell integrated with coverglass (figures 27 and 29A) comprising: a plurality of semiconductor layers (2705/2704) having a first side and a second side, the first side opposing the second side, the plurality of semiconductor layers configured to convert solar radiation to electrical energy, the second side configured to face the solar radiation; a coverglass layer (coverglass 2715) coupled to the second side via a bond
(optically clear adhesive 2714), the coverglass layer (2715) being configured to pass the solar radiation to the plurality of semiconductor layers and provide structural support for the plurality of semiconductor layers; and a first electrode pad (2720) and a second electrode pad (2719) coupled to the first side and electrically coupled to the plurality of semiconductor layers.
Chary further discloses that the coverglass has a thickness of 20-600 µm ([0050]) to protect the solar cell layers from harsh environments ([0050]). Chary further discloses that the semiconductor layers are thinned to less than 20 µm ([0136]) to allow for thinned device to be used in space or terrestrial applications ([0136]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to have used 20-600 µm thick coverglass as taught by Chary to form the transparent cover layer of Youtsey as modified by Swanson such that the solar cell layers are protected from harsh environments, as shown by Chary ([0050]) and also desired by Youtsey as modified by Swanson ([0018] of Swanson).
It would also have been obvious to one of ordinary skill in the art at the time of the invention to have used a thickness of less than 20 µm as taught by Chary to from the semiconductor layers of Youtsey as modified to allow for a thinned device to be used in space or terrestrial applications, as shown by Chary ([0136]) as also desired by Youtsey as modified by Swanson.
Regarding claim 18, Youtsey as modified by Swanson discloses that the surface-mountable solar cell forms an array with a second surface-mountable solar cell (see figure 1 of Swanson that discloses multiple cells forming solar cell module 100), and wherein a first edge of the surface-mountable solar cell is within a distance of a second edge of the second surface-mountable solar cell (see fig. 1 of Swanson).
However, Youtsey as modified does not disclose the distance is 0.5 mm. However, selection of element’s dimension is considered to be a matter of design choice, depending upon the dimensions and gradient present in the installation site, among other considerations. In the absence of evidence of criticality, selection of the distance as claimed is considered obvious to one having ordinary skill in the art. Also note that in Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Regarding claim 19, Youtsey as modified by Swanson does not disclose the surface-mountable solar cell and the second surface-mountable solar cell cover more than 75% of a module surface area of the non-terrestrial application device.
However, selection of element’s dimension is considered to be a matter of design choice, depending upon the dimensions and gradient present in the installation site, among other considerations. In the absence of evidence of criticality, selection of the dimensions of the first and second module as claimed is considered obvious to one having ordinary skill in the art. Also note that in Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Youtsey et al. (US 2010/0126573 A1) in view of Swanson et al. (US 2006/0196535 A1) and Chary et al. (US 2017/0345955 A1) as applied above, and further in view of Chang et al. (US 2008/0053518 A1).
Regarding claim 20, Youtsey as modified does not disclose the top cover or coverglass layer includes sapphire.
Chang discloses a solar cell (10) (fig. 2) wherein light transparent substrate or cover (12) is made of sapphire ([0018]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to have used sapphire as taught by Chang to form the transparent top cover of Youtsey as modified because selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP § 2144.07.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GOLAM MOWLA whose telephone number is (571)270-5268. The examiner can normally be reached M-Th, 7am - 4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allison Bourke can be reached at 303-297-4684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GOLAM MOWLA/ Primary Examiner, Art Unit 1721