Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
2. Claims 2, 16 objected to because of the following informalities:
Claim 2, line 1, “the output voltage” should be—the voltage output--
Claim 16, line 2, “the output voltage” should be –the voltage output--
Appropriate correction is required.
Response to arguments
3,The objection of claim 9 has been withdrawn because of Applicant’s amendment of the claims. Regard to 102 rejection of claim 1 and claim 15, and 103 rejection of claim 20, applicant argues that during the March 4, 2026 interview, the previous Examiner ( Thienvu Tran) acknowledged that the amendment overcame Amara (A 50% Ripple Reduction Hybrid Multiphase Interleaving SC Converter with Bottom-Plate Charge Sharing). However, after the careful review of Amara. the Examiner found that Amara teaches the newly adding limitation: Wherein the controller is configured to generate control signals to control timing of activating or deactivating the plurality of switches of the first circuit and the plurality of switches of the second circuit ( see Fig. 6, These 8-cores are switched using 8 NOCpulses according to the phase diagram in Fig. 4(b).), such that a ripple voltage of a combined output voltage of the plurality of circuits is within a specific range ( page 539, table II, . Ripple(∆VR) (mV) at 9.9 mv).
Therefore the rejection of claim 1, claim 15 and claim 20 has been maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-12, and 15-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Amara (A 50% Ripple Reduction Hybrid Multiphase Interleaving SC Converter with Bottom-Plate Charge Sharing).
Regarding Claim 1, Amara discloses a system (e.g. 8-core, 8-phase interleaved ½ SCC)(fig.5), comprising:
a controller and, a plurality of circuits (e.g. 8-core, 8-phase interleaved ½ SCC)(fig.5) configured to provide a voltage output (e.g. 8-core, 8-phase interleaved ½ SCC with DC output voltage VOUT)(fig.5) responsive to a voltage input (e.g. SCC is connected to an input voltage VIN)(fig.5), each circuit of the plurality of circuits comprising a plurality of switches and one or more capacitors (e.g. switches of a regular 2-phase SCC and one or more capacitors such as flying capacitance Cfly)(fig.3a);
wherein each circuit of the plurality of circuits is coupled in parallel with each of other circuits of the plurality of circuits (e.g. multiphase interleaving where the SCC is operated as multiple phase-shifted converter cores in a parallel configuration, such as 4-phase interleaving)(fig.3b), wherein an input of each circuit is coupled to the voltage input (e.g. cores are connected to a common input voltage VIN)(fig.5) and wherein an output of each circuit is coupled to the voltage output (e.g. cores are connected to a common output voltage VOUT)(fig.5); and
wherein the plurality of switches of a first circuit of the plurality of circuits is configured to be switched on and off at a phase (e.g. 8-phase non overlapping clock (NOC) generator that produces 8-phase shifted non-overlapping pulses (φ1 − φ8))(fig.5-6) that is different from a phase of at least the plurality of switches of a second circuit of the plurality of circuits (e.g. phase-shifted converter cores)(fig.3b).
Wherein the controller is configured to generate control signals to control timing of activating or deactivating the plurality of switches of the first circuit and the plurality of switches of the second circuit ( see Fig. 6, These 8-cores are switched using 8-phase non-overlapping pulses according to the phase diagram in Fig. 4(b).), such that a ripple voltage of a combined output voltage of the plurality of circuits is within a specific range ( page 539, table II, . This work Ripple(∆VR) (mV) at 9.9 mv)
Regarding claim 2, Amara discloses the system of claim 1, wherein a ripple of the output voltage (e.g. output voltage ripple ∆VR or ∆VSPCR)(pg.1, eq.1)((pg.2, eq.4) is configured to be reduced according to a number of phases (e.g. “the ripple in 4-core, 8-phase (4C8P) is four times lesser than regular converter (1C2P), and in 4C4P, it is two times lesser than 1C2P”)(p.2)(fig.3(d)) at which the plurality of switches from one or more circuits of the plurality of circuits is switched on or off (e.g. multiphase interleaving is a technique used to reduce ripple)(p.2)(fig3 (a-d).
Regarding Claim 3, Amara discloses the system of claim 1, wherein the voltage output of the plurality of circuits is generated according to a sum of outputs of a subset of the plurality of circuits (e.g. 8 interleaved cores supply a common output)(fig.5) receiving a plurality of signals (8-phase NOC generator that provides 8-phase shifted non-overlapping pulses (φ1 − φ8))(fig.5 and 6) to control the respective phases of each of the subset of the plurality of circuits according to which each of the plurality of switches of each of the subset of the plurality of circuits is switched on or off (e.g. phase shifted pulses control the switching of the interleaved cores)(fig.5).
Regarding Claim 4, Amara discloses the system of claim 1, wherein the plurality of switches of the first circuit of the plurality of circuits switch on and off at a first time (e.g. timing of pulse φ1) (fig.6) that is different than a second time (e.g. timing of pulse φ2) (fig.6) at which the plurality of switches of the second circuit of the plurality of circuits is switched on and off, responsive to a plurality of signals provided by a controller (e.g. 8-phase NOC generator and control blocks)(fig.5).
Regarding Claim 5, Amara discloses the system of claim 1, wherein the phase at which the plurality of switches of the first circuit (e.g. the first core controlled by φ1)(fig.5 and 6) is configured to be switched on and off and the phase at which the plurality of switches of the second circuit (e.g. the second core controlled by φ2)(fig.5 and 6) is configured to be switched on and off are each different than a third phase (e.g. third phase φ3)(fig.5 and 6) at which the plurality of switches of a third circuit (e.g. the third core controlled by φ3)(fig.5 and 6) of the plurality of circuits is configured to be switched on and off (e.g. a system with 8-phase shifted non-overlapping pulses (φ1 − φ8), with a first phase φ1, a second phase φ2, and a third phase φ3, which are all different)(fig.5 and 6).
Regarding Claim 7, Amara discloses the system of claim 1, wherein the plurality of circuits provide the voltage output according to a sum of outputs of each of the plurality of circuits (e.g. 8 interleaved cores supply a common output)(fig.5) responsive to a signal (e.g. 8-phase signals φ1- φ8 from NOC sent to the cores)(fig.5) from the controller (e.g. 8-phase NOC generator and control blocks)(fig.5-6), the sum including at least a first voltage (e.g. first core output voltage at common VOUT)(fig.5) from a first output (e.g. output of first interleaved core into shared node before common VOUT)(fig.5) of the first circuit of the plurality of circuits and a second voltage from a second output (e.g. output of second interleaved core into shared node before common VOUT)(fig.5) of the second circuit of the plurality of circuits.
Regarding Claim 8, Amara discloses the system of claim 1, wherein a first one or more capacitors of the one or more capacitors of the first circuit (e.g. flying capacitors)(fig.3a) charge in response to first one or more switches of the plurality of switches being switched off and discharge in response to the first one or more switches being switched on (e.g. 2-phase switch capacitor converter (SSC) pairs of switches)(fig.3a).
Regarding Claim 9, Amara discloses the system of claim 8, wherein the first one or more capacitors charge in response to second one or more switches (e.g. 2-phase switch capacitor converter (SSC) pairs of switches)(fig.3a) being switched on and discharge in response to the second one or more switches being switched off.
Regarding Claim 10, Amara discloses the system of claim 9, comprising:
the controller (e.g. 8 phase NOC generator and control blocks)(fig.5) is coupled with the plurality of circuits, wherein the first one or more switches and the second one or more switches are switched on and off at a same time (i.e. the controller tells one set of switches to be on and another set of switches to be off, such as within the two-phase core in figure 3(a) or the non-overlapping phase outputs in figure 6) responsive to a first plurality of signals from the controller (e.g. signals for a single core derived from the 8-phase non-overlapping pulses φ1- φ8)(fig.5-6).
Regarding Claim 15, Amara discloses a method, comprising:
providing, by a plurality of circuits (e.g. 8 core 8 phase interleaving SC converter)(fig.5), a voltage output (e.g. VOUT)(fig.5) responsive to a voltage input (e.g. VIN)(fig.5), each circuit of the plurality of circuits comprising a plurality of switches (e.g. switches S1-S7)(fig.5) and one or more capacitors (e.g. capacitors in MAIN CORE)(fig.5);
coupling, by each circuit of the plurality of circuits, input of each respective circuit to the voltage input of the plurality of circuits and output of each respective circuit to the voltage output (e.g. common VIN and VOUT rails)(fig.5) of the plurality of circuits, the plurality of circuits configured in parallel with each of other circuits of the plurality of circuits (e.g. parallel configuration of the circuits)(fig.5); and switching the plurality of switches of a first circuit of the plurality of circuits on and off at a phase (e.g. φ1)(fig.6) that is different from a phase (e.g. φ2)(fig.6) of at least the plurality of switches of a second circuit (e.g. 8-phase shifted non-overlapping pulses)(fig.6) of the plurality of circuits.
Generating, by a controller, control signals to control timing of activating or deactivating the plurality of switches of the first circuit and the plurality of switches of the second circuit ( see Fig. 6, These 8-cores are switched using 8 NOC pulses according to the phase diagram in Fig. 4(b).), such that a ripple voltage of a combined output voltage of the plurality of circuits is within a specific range ( page 539, table II, this work Ripple(∆VR) (mV) at 9.9 mv)
Regarding Claim 16, Amara discloses the method of claim 15, comprising:
reducing, by the plurality of circuits, a ripple of the output voltage (e.g. output ripple)(fig.3(d)) according to a number of phases (e.g. 4C4P and 4C8P ripple)(fig.3(d)) at which the plurality of switches from one or more circuits of the plurality of circuits is turned on or off; and generating, by the plurality of circuits, the voltage output according to a sum of outputs (e.g. outputs for each of the parallel cores leading to VOUT)(fig.5) of a subset of the plurality of circuits (e.g. the 8 cores)(fig.5) receiving a plurality of signals (8-phase shifted non-overlapping pulses φ1- φ8)(fig.5-6) to control the respective phases of each of the subset of the plurality of circuits according to which each of the plurality of switches of each of the subset of the plurality of circuits is turned on or off (e.g. turning the switches on and off with the decoder, level shifters and 8-phase signal pulse generator)(fig.5).
Regarding Claim 17, Amara discloses the method of claim 15, comprising:
providing, by the controller (e.g. control blocks such as the 8-phase NOC generator)(fig.5), a plurality of signals (e.g. 8-phase signal pulses)(fig.5 and 6) in response to which the plurality of switches of the first circuit of the plurality of circuits switch on and off at a first time (e.g. timing of φ1)(fig.3, 5 and 6) that is different than a second time (e.g. timing of φ2)(fig.3, 5 and 6) at which the plurality of switches of the second circuit of the plurality of circuits switches on and off.
Regarding Claim 18, Amara discloses the method of claim 15, comprising:
switching the plurality of switches of the first circuit of the plurality of circuits on and off according to a first phase (e.g. φ1)(fig. 5 and 6); switching the plurality of switches of the second circuit of the plurality of circuits on and off according to a second phase (e.g. φ2)(fig.5 and 6) that is different than the first phase; and switching the plurality of switches of a third circuit (e.g. 8 core 8 phase interleaving SC converter)(fig.5) of the plurality of circuits on and off according to a third phase (e.g. φ3)(fig.5 and 6) that is different than the first phase and different than the second the second phase (e.g. 8 distinct phases)(fig.5 and 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Amara (A 50% Ripple Reduction Hybrid Multiphase Interleaving SC Converter with Bottom-Plate Charge Sharing) and in view of Azrai (US 7190210 B2).
Regarding Claim 6, Amara teaches the system of claim 1,
However, Amara does not explicitly disclose comprising:
a memory coupled with a controller, wherein the memory is configured to store one or more instructions for the controller to provide the phase for the plurality of switches of the first circuit and the plurality of switches of the second circuit.
Azrai teaches in a similar field of endeavor, comprising:
a memory (e.g. a multi-phase switched capacitor system with control logic 24 and memory 25)(fig.2) coupled with a controller (e.g. control logic 24)(fig.2), wherein the memory is configured to store one or more instructions (e.g. “control logic 24 calculates configuration and operating instructions for power stage 28”)(Col 10, lines 46-47) for the controller to provide the phase for the plurality of switches of the first circuit and the plurality of switches of the second circuit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have optionally implemented a controller with memory in Amara, as taught by Azrai. A person of ordinary skill in the art would be motivated to include a controller with memory to allow for the configurability of phase timing and other instructions, rather than be limited by a control scheme fixed in hardware logic.
Claims 11-12, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Amara (A 50% Ripple Reduction Hybrid Multiphase Interleaving SC Converter with Bottom-Plate Charge Sharing) and in view of Chandrasekar (US 10812085 B2).
Regarding Claim 11, Amara teaches the system of claim 1, comprising:
a die (e.g. implemented 180nm CMOS)(fig.8) comprising an integrated circuit (e.g. 8C8P SCC with switches, control logic, and capacitors)(fig.8) powered by the voltage output of the plurality of circuits,
Amara does not explicitly teach wherein the plurality of circuits are disposed beneath the die and the voltage output is provided to the integrated circuit using one or more vias oriented vertically and coupled with the integrated circuit at the die.
Chandrasekar teaches in a similar field of endeavor wherein the plurality of circuits (e.g. base die 24 which can be identified as an active interposer and further shown to include a fully integrated voltage regulator or “FIVR” 96)(fig.2, 8, and 15) are disposed beneath the die (e.g. base die 24 is beneath fabric die 22) and the voltage output is provided to the integrated circuit (e.g. the active interposer base die 24, “may also perform power management and/or regulatory operations to control voltage and/or current”)(fig.2 and 15) using one or more vias oriented vertically (e.g. microbumps 26 which are vertical interconnects between the stacked dies)(fig.2) and coupled with the integrated circuit at the die (e.g. the microbumps 26 couple the bas die 24 to the fabric die 22)(fig.2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined Amara’s plurality of voltage regulation circuits with reduced ripple and implement Chandrasekar’s efficient packaging structure of an active interposer to save space.
Regarding claim 12, Amara teaches the system of claim 1, comprising:
a die (e.g. implemented 180nm CMOS)(fig.8) comprising an integrated circuit (e.g. 8C8P SCC)(fig.8) powered by the voltage output of the plurality of circuits,
Amara does not explicitly teach wherein at least a portion of the first circuit of the plurality of circuits is formed within one of an interposer, a package, or a printed circuit board, wherein the one of the interposer, the package or the printed circuit board includes an outer surface supporting the die thereon.
Chandrasekar teaches in a similar field of endeavor wherein at least a portion of the first circuit (e.g. the FIVR 96 is integrated into the interposer)(fig.15) of the plurality of circuits is formed within one of an interposer (e.g. active interposer base die 24)(fig.15), a package (e.g. package 32)(fig.2), or a printed circuit board (e.g. package 32)(fig.2), wherein the one of the interposer, the package or the printed circuit board includes an outer surface supporting the die thereon (e.g. the interposer base die 24 supports the fabric die 22, and the package 32 supports the interposer base die 24)(fig.2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined Amara’s plurality of voltage regulation circuits with reduced ripple and implement Chandrasekar’s efficient packaging structure of an active interposer to save space.
Regarding Claim 19, Amara teaches the method of claim 15, and further teaches comprising:
switching, by the first circuit of the plurality of circuits, first one or more switches (e.g. switch set for φ1)(fig.3(a)) of the plurality of switches of the first circuit in response to which a first one or more capacitors (e.g. capacitor Cfly)(fig.3a) of the one or more capacitors of the first circuit to charge responsive to the first one or more switches being switched off and discharge responsive to the first one or more switches being switched on (e.g. φ1 switches turn on to begin discharge into VOUT)(fig.3a);
switching, by the first circuit, second one or more switches (e.g. switch set for φ2)(fig.3a) of the plurality of switches of the first circuit in response to which the first one or more capacitors charge responsive to the second one or more switches being switched on (e.g. φ2 switches turn on to begin the charging phase)(fig.3a) and discharge responsive to the second one or more switches being switched off (e.g. φ1 switches turn off to complete discharge)(fig.3a);
providing, by the controller coupled with the plurality of circuits (e.g. 8-phase NOC generator and control blocks)(fig.5), a first plurality of signals (e.g. signals for a single core derived from the 8-phase non-overlapping pulses φ1- φ8)(fig.5-6) to cause the first one or more switches and the second one or more switches to switch on and off at a same time (e.g. switching controlled by non-overlapping phase outputs)(fig.3a and 6); and
powering an integrated circuit on a die (e.g. SCC outputs voltage to a linear regulator which feeds a current ILoad consumed by different blocks of wireless sensor nodes (WSNs))(fig.1, 5, and 8) using the voltage output of the plurality of circuits,
Amara does not explicitly disclose wherein the plurality of circuits are disposed beneath the die and the voltage output is provided to the integrated circuit using one or more vias oriented vertically and coupled with the integrated circuit at the die.
Chandrasekar teaches in a similar field of endeavor wherein the plurality of circuits (e.g. FIVR 96 on base die 24)(fig.8 and15) are disposed beneath the die (e.g. base die 24 is beneath fabric die 22)(fig.8 and 15) and the voltage output is provided to the integrated circuit using one or more vias oriented vertically (e.g. microbumps 26 which are vertical interconnects between the stacked dies)(fig.2) and coupled with the integrated circuit at the die.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined Amara’s plurality of voltage regulation circuits with reduced ripple and implement Chandrasekar’s efficient packaging structure of an active interposer to save space.
Regarding Claim 20, Amara teaches a system (e.g. 8-core, 8-phase interleaved ½ SCC)(fig.5 and 8), comprising:
A controller and
a plurality of circuits (e.g. 8-core, 8-phase interleaved ½ SCC)(fig.5).
each circuit of the plurality of circuits comprising a plurality of switches and one or more capacitors (e.g. switches for phases φ1 and φ2 with capacitor Cfly in figure 3(a) and later updated to switches S1-S7)(fig.5);
wherein each circuit of the plurality of circuits is coupled in parallel with each of other circuits of the plurality of circuits (e.g. 8 cores in parallel)(fig.5), wherein an input of each circuit is coupled to the voltage input (e.g. common VIN)(fig.5) and wherein an output of each circuit is coupled to the voltage output (e.g. common VOUT)(fig.5);
wherein the plurality of switches of each circuit of the plurality of circuits is configured to be switched on and off at a phase (e.g. phase φ1)(fig.6) that is different from a phase (e.g. phase φ2)(fig.6) of at least one another plurality of switches of another circuit of the plurality of circuits (e.g. non-overlapping phase outputs)(fig.5 and 6); and
Wherein the controller is configured to generate control signals to control timing of activating or deactivating the plurality of switches of the first circuit and the plurality of switches of the second circuit ( see Fig. 6, These 8-cores are switched using 8 phase non-overlapping pluses according to the phase diagram in Fig. 4(b).), such that a ripple voltage of a combined output voltage of the plurality of circuits is within a specific range ( page 539, table II, this work. Ripple(∆VR) (mV) at 9.9 mv)
Amara does not explicitly teach configured beneath a die to provide a voltage output to an integrated circuit comprised by the die in response to a voltage input, nor does Amara explicitly teach wherein the voltage output is coupled with the die using one or more vias oriented vertically.
Chandrasekar teaches in a similar field of endeavor configured beneath a die (e.g. base die 24 beneath fabric die 22)(fig.2 and15) to provide a voltage output (e.g. VOUT)(fig.16A) to an integrated circuit (e.g. “the FIVR 96 may be used to exclusively power the fabric die 22”)(Col 19, lines [18-19]) comprised by the die in response to a voltage input (e.g. voltage supply 200)(fig.16A), each circuit of the plurality of circuits comprising a plurality of switches (e.g. switch 196)(fig.16A) and one or more capacitors (e.g. capacitor 192)(fig.16A);
wherein each circuit of the plurality of circuits is coupled in parallel with each of other circuits of the plurality of circuits (e.g. programmable switched fully integrated voltage regulator with L/C branches using inductors 190A, 190B, and capacitors 192A, 192B)(fig.16B), wherein an input of each circuit (e.g. voltage supply 200)(fig.16B) is coupled to the voltage input and wherein an output of each circuit (e.g. VOUT 198)(fig.16B) is coupled to the voltage output;
wherein the voltage output is coupled with the die using one or more vias oriented vertically (e.g. microbumps 26 connecting base die 24 to fabric die 22)(fig.2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined Amara’s plurality of voltage regulation circuits in a parallel configuration with reduced ripple and implement Chandrasekar’s efficient vertical 2.5D packaging structure of an active interposer including a fully integrated voltage regulator beneath the die to save space.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Amara (A 50% Ripple Reduction Hybrid Multiphase Interleaving SC Converter with Bottom-Plate Charge Sharing) and in view of TDCommons (Integrated, Switched-Capacitor Voltage Regulator with Deep Trench Capacitor).
Regarding Claim 13 Amara teaches the system of claim 1, comprising:
a die (e.g. 180nm CMOS die)(fig.8) comprising an integrated circuit (e.g. current consuming blocks of wireless sensor nodes (WSNs))(fig.1) powered by the voltage output of the plurality of circuits (e.g. VOUT node powering current load)(fig.1),
Amara does not explicitly teach the specific packaging wherein the die is supported on an outer surface of an interposer that is supported on an outer surface of a package, wherein the one or more capacitors of the first circuit of the plurality of circuits is at least partly disposed within the interposer and the plurality of switches of the first circuit is disposed beneath the one or more capacitors of the first circuit, the plurality of switches of the first circuit coupled with the one or more capacitors of the first circuit using a first one or more vias oriented vertically.
TDcommons teaches in a similar field of endeavor wherein the die (e.g. silicon)(fig.4) is supported on an outer surface of an interposer (e.g. interposer w/DTC)(fig.4) that is supported on an outer surface of a package (e.g. PCB)(fig.4), wherein the one or more capacitors of the first circuit of the plurality of circuits is at least partly disposed within the interposer (e.g. fly capacitors in options 2-4)(fig.4) and the plurality of switches of the first circuit is disposed beneath the one or more capacitors of the first circuit (e.g. MOSFETs on the package below the capacitors in options such as option 2)(fig.4), the plurality of switches of the first circuit coupled with the one or more capacitors of the first circuit using a first one or more vias oriented vertically (i.e. vertical vias are an inherent and/or obvious implementation for connecting layer stacks shown from the technical disclosure shown in figure 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined Amara’s system of a plurality of voltage regulation circuits in a parallel configuration with reduced ripple and save space with TDCommons vertical packaging structure of an active interposer including a fully integrated voltage regulator and capacitors beneath the die to save space.
Regarding Claim 14. Amara and TDCommons teach the system of claim 13,
Amara does not explicitly teach wherein the first plurality of switches is disposed on the package located beneath the interposer and wherein the one or more capacitors are coupled with the integrated circuit of the die using a second one or more vias oriented vertically. TDcommons teaches in a similar field of endeavor wherein the first plurality of switches is disposed on the package located beneath the interposer (e.g. MOSFETs and controller located on the package)(fig.4) and wherein the one or more capacitors are coupled with the integrated circuit of the die using a second one or more vias oriented vertically (e.g. fly capacitors are coupled to the silicon die and to the switches while placed in a vertical layer stack)(fig.4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined Amara’s system of a plurality of voltage regulation circuits in a parallel configuration with reduced ripple and save space with TDCommons vertical packaging structure of an active interposer, including a fully integrated voltage regulator, and capacitors beneath the die to save space.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Giuliano (US 20170244318 A1) teaches an apparatus for power conversion includes a transformation stage for transforming a first voltage into a second voltage. The transformation stage includes a switching network, a filter, and a controller. The filter is configured to connect the transformation stage to a regulator. The controller controls the switching network.
Dong (US20130257527A1) teaches a method includes receiving an input signal in transmitter circuitry of a first semiconductor die and processing the input signal, sending the processed input signal to an isolation circuit of the die to generate a voltage isolated signal
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINPING SUN whose telephone number is (571)270-1284. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PINPING SUN/Supervisory Patent Examiner, Art Unit 2872
