DETAILED ACTION
This office action is in response to amendment filed on 4/16/2026.
Claims 1, 11 and 18 are amended.
Claims 1 – 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “data storage device” and “controller” in claim 18 – 20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Au et al (USPAT 11481156, hereinafter Au), in view of Xu et al (US 20200104256, hereinafter Xu).
As per claim 1, Au discloses: A data storage device, comprising: a memory device; and a controller coupled to the memory device, wherein the controller is configured to:
allocate first bandwidth of total bandwidth to a first tenant; allocate second bandwidth of the total bandwidth to a second tenant; (Au figure 3 and col 14, lines 1 – 16: “at 302 where data including a total bandwidth utilization amount allocated to each of a plurality of client devices for a time interval and a current bandwidth amount utilized by each of the plurality of client devices during the time interval is stored at storage circuitry 112. At 304, a bandwidth monitoring circuitry monitors an actual bandwidth amount utilized for servicing one or more requests received from respective ones of the plurality of client devices over a network is monitored. At 306, an expected bandwidth utilization amount for servicing a request received from respective ones of the plurality of client devices over the network, wherein the request comprises a request to access a distributed storage system formed of a plurality of storage devices interconnected over the network is determined by the bandwidth monitoring circuitry”.)
and arbitrate data transfer requests between the first tenant and the second tenant based upon the allocated first and second bandwidths. (Au figure 3 and col 14, lines 16 – 23: “At block 308, for a request of a plurality of requests received from respective ones of the plurality of client devices during the time interval, the arbiter circuitry 114 determines whether to permit or deny the client device transmitting the request access to the distributed storage system based on a function of the expected bandwidth utilization of the request relative to the total bandwidth utilization amount allocated to the requesting client device.”)
Au did not explicitly disclose:
wherein the first tenant does not use all of the first bandwidth and the second tenant uses the first bandwidth when the first tenant does not need to use the first bandwidth;
However, Xu teaches:
wherein the first tenant does not use all of the first bandwidth and the second tenant uses the first bandwidth when the first tenant does not need to use the first bandwidth; (Xu [0002]: “determining a respective share of the total memory bandwidth for each tenant, and determining a respective dynamic memory bandwidth budget for the each tenant. The memory bandwidth allocations may be controlled based on the determined respective dynamic memory bandwidth budgets, wherein the each respective dynamic memory bandwidth budget supports utilizing the each respective share and supports sharing unused memory bandwidth of the each respective tenant with a different tenant included in the plurality of tenants.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into that of Au in order to have the first tenant does not use all of the first bandwidth and the second tenant uses the first bandwidth when the first tenant does not need to use the first bandwidth. Au col 14, lines 16 – 23 teaches the arbiter circuitry 114 determines whether to permit or deny the client device transmitting the request access to the distributed storage system based on a function of the expected bandwidth utilization of the request relative to the total bandwidth utilization amount allocated to the requesting client device. Xu [0002] teaches the concept of load balancing is commonly known and used methods for arbitrating access in order to improve the efficiency of the shared processing system, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results of load balancing of unused shared computing capacity and is therefore rejected under 35 USC 103.
As per claim 8, the combination of Au and Xu further teach:
The data storage device of claim 1, wherein the controller comprises a weighted round robin arbiter. (Au col 7, line 54 – col 8, line 10: weighted round robin scheme.)
As per claim 9, the combination of Au and Xu further teach:
The data storage device of claim 8, wherein the weighted round robin arbiter is configured to allocate bandwidth for scatter-gather list (SGL) fetching and data-fetching. (Au col 7, line 54 – col 8, line 10: weighted round robin scheme. Examiner notes that the limitation “for scatter-gather list (SGL) fetching and data-fetching” is merely claiming the intended usage of the bandwidth and is not given patentable weight in this office action.)
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Au and Xu, in view of Chrabieh (US 20060107268).
As per claim 2, the3 combination of Au and Xu did not teach:
The data storage device of claim 1, wherein the arbitration comprises: beginning processing of a first command for the first tenant; and beginning processing of a second command for the second tenant, wherein processing of the second command begins prior to completion of processing the first command.
However, Chrabieh teaches:
The data storage device of claim 1, wherein the arbitration comprises: beginning processing of a first command for the first tenant; and beginning processing of a second command for the second tenant, wherein processing of the second command begins prior to completion of processing the first command. (Chrabieh [0038]: “Each task is assigned a priority level, and is associated with a stack 140. A first task may be preempted by a second task with higher priority, for example, which requires the system to momentarily suspend the first task. The system uses the stack 140 to preserve the state of the first task when the first task suspends. As previously described, when a task "A" stops or suspends and a task "B" resumes, a "context switch" occurs.”.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lee into that of Au and Xu in order to have the arbitration comprises: beginning processing of a first command for the first tenant; and beginning processing of a second command for the second tenant, wherein processing of the second command begins prior to completion of processing the first command. Au col 7, line 54 – col 8, line 10 teaches using priority as arbitration criteria in round robin fashion. One of ordinary skill can easily see that having a higher priority request preempt an currently executing, lower priority request would be allow the priority arbitration to function more dynamically to improve the efficiency of the scheduling system, such combination would enhance the overall appeals of all references and is therefore rejected under 35 USC 103.
Claim(s) 3, 4, 6, 7, 11 – 13, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Au and Xu, in view of Kutch et al (US 20210117360, hereinafter Kutch), and further in view of Jadon et al (USPAT 10552058, hereinafter Jadon).
As per claim 3, Au and Xu further teach:
The data storage device of claim 1, wherein the controller comprises a data path, wherein the data path comprises: a write handler (Au figure 2, arbiter).
Au and Xu did not teach:
wherein the controller comprises a control path, wherein the data path further comprises: a flash interface module (FIM); a scatter-gather list (SGL) fetching module; a direct memory access (DMA) module; and a cached memory module;
However, Kutch teaches:
wherein the controller comprises a control path (Kutch [0268]: control path), wherein the data path comprises: a scatter-gather list (SGL) fetching module (Kutch [0179] – [0180]); a direct memory access (DMA) module (Kutch [0063]); and a cached memory module (Kutch [0063])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kutch into that of Au and Xu in order to have the controller comprises a data path, wherein the data path comprises: a scatter-gather list (SGL) fetching module; a direct memory access (DMA) module; and a cached memory module. Kutch has shown that the claimed limitations are merely commonly known modules used in memory management, and thus applicant have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
Jadon teaches:
wherein the data path comprises: a flash interface module (FIM); (Jadon col 32, line – col 33, line 33)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jadon into that of Au, Xu and Kutch in order to have the data path comprises a flash interface module. Jadon has shown that the claimed limitations are merely commonly known modules used in memory management, and thus applicant have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
As per claim 4, the combination of Au, Xu, Kutch and Jadon further teach:
The data storage device of claim 3, wherein the write handler comprises: an arbiter; a first queue corresponding to the first tenant; and a second queue corresponding to the second tenant. (Au figure 2.)
As per claim 6, the combination of Au, Xu, Kutch and Jadon further teach:
The data storage device of claim 4, wherein the arbiter is a weighted round robin arbiter. (Au col 7, line 54 – col 8, line 10: weighted round robin scheme.)
As per claim 7, the combination of Au, Xu, Kutch and Jadon further teach:
The data storage device of claim 3, wherein the arbiter is a flash management unit (FMU) sized arbiter. (Jadon col 32, line – col 33, line 33.)
As per claim 11, Au discloses: A data storage device, comprising: a memory device; and a controller coupled to the memory device, wherein the controller comprises:
a data path, wherein the data path comprises: a write handler including a weighted round robin arbiter; (Au figure 2, arbiter; col 7, line 54 – col 8, line 10: weighted round robin scheme.)
Wherein the controller is configured to allocate guaranteed bandwidth to a first tenant and second bandwidth to a second tenant, (Au figure 3 and col 14, lines 1 – 16: “at 302 where data including a total bandwidth utilization amount allocated to each of a plurality of client devices for a time interval and a current bandwidth amount utilized by each of the plurality of client devices during the time interval is stored at storage circuitry 112. At 304, a bandwidth monitoring circuitry monitors an actual bandwidth amount utilized for servicing one or more requests received from respective ones of the plurality of client devices over a network is monitored. At 306, an expected bandwidth utilization amount for servicing a request received from respective ones of the plurality of client devices over the network, wherein the request comprises a request to access a distributed storage system formed of a plurality of storage devices interconnected over the network is determined by the bandwidth monitoring circuitry”.)
Au did not explicitly disclose:
wherein the controller comprises: a PCIe bus; and a control path;
a scatter gather list (SGL) fetching module coupled to the write handler;
a direct memory access (DMA) module coupled to the SGL fetching module;
a cached memory module coupled to the DMA module;
and a flash interface module (FIM) coupled to the memory device and the cached memory module;
wherein the first tenant does not use all of the first bandwidth and the second tenant uses the first bandwidth when the first tenant does not need to use the first bandwidth;
However, Xu teaches:
wherein the first tenant does not use all of the first bandwidth and the second tenant uses the first bandwidth when the first tenant does not need to use the first bandwidth; (Xu [0002]: “determining a respective share of the total memory bandwidth for each tenant, and determining a respective dynamic memory bandwidth budget for the each tenant. The memory bandwidth allocations may be controlled based on the determined respective dynamic memory bandwidth budgets, wherein the each respective dynamic memory bandwidth budget supports utilizing the each respective share and supports sharing unused memory bandwidth of the each respective tenant with a different tenant included in the plurality of tenants.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into that of Au in order to have the first tenant does not use all of the first bandwidth and the second tenant uses the first bandwidth when the first tenant does not need to use the first bandwidth. Au col 14, lines 16 – 23 teaches the arbiter circuitry 114 determines whether to permit or deny the client device transmitting the request access to the distributed storage system based on a function of the expected bandwidth utilization of the request relative to the total bandwidth utilization amount allocated to the requesting client device. Xu [0002] teaches the concept of load balancing is commonly known and used methods for arbitrating access in order to improve the efficiency of the shared processing system, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results of load balancing of unused shared computing capacity and is therefore rejected under 35 USC 103.
Kutch teaches:
wherein the controller comprises: a PCIe bus; and a control path; (Kutch [0056]: PCIe bus; [0268]: control path.)
a scatter gather list (SGL) fetching module coupled to the write handler; (Kutch [0179] – [0180])
a direct memory access (DMA) module coupled to the SGL fetching module; (Kutch [0063])
a cached memory module coupled to the DMA module; (Kutch [0063])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kutch into that of Au and Xu in order to have the controller comprises a control path, wherein the data path comprises: a scatter-gather list (SGL) fetching module; a direct memory access (DMA) module; and a cached memory module. Kutch has shown that the claimed limitations are merely commonly known modules used in memory management, and thus applicant have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
Jadon teaches:
and a flash interface module (FIM) coupled to the memory device and the cached memory module. (Jadon col 32, line – col 33, line 33)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jadon into that of Au, Xu and Kutch in order to have a flash interface module (FIM) coupled to the memory device and the cached memory module. Jadon has shown that the claimed limitations are merely commonly known modules used in memory management, and thus applicant have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
As per claim 12, the combination of Au, Xu, Kutch and Jadon further teach:
The data storage device of claim 11, wherein the write handler further comprises a plurality of queues (Au figure 2.), wherein each queue of the plurality of queues corresponds to a virtual host. (Kutch [0101: virtual hardware platforms.)
As per claim 13, the combination of Au, Xu, Kutch and Jadon further teach:
The data storage device of claim 12, wherein the weighted round robin arbiter is configured to assign slots to a corresponding queue of the plurality of queues based upon bandwidth assigned to the virtual hosts. (Au col 7, line 54 – col 8, line 10: weighted round robin scheme.)
As per claim 16, the combination of Au, Xu, Kutch and Jadon further teach:
The data storage device of claim 12, wherein at least one queue of the plurality of queues has a different quality of service (QoS) compared to at least one other queue of the plurality of queues. (Kutch [0140])
As per claim 17, the combination of Au, Xu, Kutch and Jadon further teach:
The data storage device of claim 11, wherein the control path comprises a command fetching module for fetching commands and wherein the SGL fetching module fetches SGLs for the fetched commands. (Kutch [0179] – [0180])
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Au, Xu, Kutch and Jadon, and further in view of Greenspan et al (US 20190004953, hereinafter Greenspan).
As per claim 5, the combination of Au, Xu, Kutch and Jadon did not teach:
The data storage device of claim 4, wherein the first queue and the second queue each service a single 4K Byte at a time.
However, Greenspan teaches:
The data storage device of claim 4, wherein the first queue and the second queue each service a single 4K Byte at a time. (Greenspan [0038])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Greenspan into that of Au, Xu, Kutch and Jadon in order to have the first queue and the second queue each service a single 4K Byte at a time. It is merely an obvious design choice made by the applicant to set the specific size of the queue and is therefore rejected under 35 USC 103.
Claim(s) 10 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Au and Xu, and in view of Kutch.
As per claim 10, the combination of Au and Xu did not explicitly teach:
The data storage device of claim 1, wherein the first tenant corresponds to a first virtual host and the second tenant corresponds to a second virtual host.
However, Kutch teaches:
The data storage device of claim 1, wherein the first tenant corresponds to a first virtual host and the second tenant corresponds to a second virtual host. (Kutch [0101: virtual hardware platforms.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kutch into that of Au and Xu in order to have the first tenant corresponds to a first virtual host and the second tenant corresponds to a second virtual host. Kutch has shown that the claimed virtual host is commonly known and used in the field and serves the same functions as the client devices of Au, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
As per claim 18, Au discloses: A data storage device, comprising: memory means; and a controller coupled to the memory means, wherein the controller is configured to:
process scatter [commands] for multiple [hosts] based upon bandwidth assigned to [hosts] of the [hosts] and wherein SGL commands for the multiple [hosts] are processed consecutively. (Au figure 3 and col 14, lines 1 – 23: “at 302 where data including a total bandwidth utilization amount allocated to each of a plurality of client devices for a time interval and a current bandwidth amount utilized by each of the plurality of client devices during the time interval is stored at storage circuitry 112. At 304, a bandwidth monitoring circuitry monitors an actual bandwidth amount utilized for servicing one or more requests received from respective ones of the plurality of client devices over a network is monitored. At 306, an expected bandwidth utilization amount for servicing a request received from respective ones of the plurality of client devices over the network, wherein the request comprises a request to access a distributed storage system formed of a plurality of storage devices interconnected over the network is determined by the bandwidth monitoring circuitry. At block 308, for a request of a plurality of requests received from respective ones of the plurality of client devices during the time interval, the arbiter circuitry 114 determines whether to permit or deny the client device transmitting the request access to the distributed storage system based on a function of the expected bandwidth utilization of the request relative to the total bandwidth utilization amount allocated to the requesting client device.”; Figure 5, step 508, arbitrate client request based on priority and then allow the client device access sequentially based on priority.)
Au did not explicitly disclose:
wherein the commands are scatter gather list (SGL) commands;
wherein the hosts comprise virtual hosts;
wherein the first tenant does not use all of the first bandwidth and the second tenant uses the first bandwidth when the first tenant does not need to use the first bandwidth;
However, Xu teaches:
wherein the first tenant does not use all of the first bandwidth and the second tenant uses the first bandwidth when the first tenant does not need to use the first bandwidth; (Xu [0002]: “determining a respective share of the total memory bandwidth for each tenant, and determining a respective dynamic memory bandwidth budget for the each tenant. The memory bandwidth allocations may be controlled based on the determined respective dynamic memory bandwidth budgets, wherein the each respective dynamic memory bandwidth budget supports utilizing the each respective share and supports sharing unused memory bandwidth of the each respective tenant with a different tenant included in the plurality of tenants.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Xu into that of Au and Kutch in order to have the first tenant does not use all of the first bandwidth and the second tenant uses the first bandwidth when the first tenant does not need to use the first bandwidth. Au col 14, lines 16 – 23 teaches the arbiter circuitry 114 determines whether to permit or deny the client device transmitting the request access to the distributed storage system based on a function of the expected bandwidth utilization of the request relative to the total bandwidth utilization amount allocated to the requesting client device. Xu [0002] teaches the concept of load balancing is commonly known and used methods for arbitrating access in order to improve the efficiency of the shared processing system, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results of load balancing of unused shared computing capacity and is therefore rejected under 35 USC 103.
Kutch teaches:
wherein the commands are scatter gather list (SGL) commands; (Kutch [0179] – [0180])
wherein the hosts comprise virtual hosts; (Kutch [0101: virtual hardware platforms.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kutch into that of Au and Xu in order to have the commands are scatter gather list (SGL) commands and the hosts comprise virtual hosts. Kutch has shown that the claimed limitations are merely commonly known modules used in memory management, and thus applicant have merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Au, Xu, Kutch and Jadon, and further in view of Chrabieh.
As per claim 14, the combination of Au, Xu, Kutch and Jadon did not teach:
The data storage device of claim 13, wherein the controller is configured to process a first command from a first queue of the plurality of queues prior to completing processing of a second command from a second queue of the plurality of queues.
However, Chrabieh teaches:
The data storage device of claim 13, wherein the controller is configured to process a first command from a first queue of the plurality of queues prior to completing processing of a second command from a second queue of the plurality of queues. (Chrabieh [0038]: “Each task is assigned a priority level, and is associated with a stack 140. A first task may be preempted by a second task with higher priority, for example, which requires the system to momentarily suspend the first task. The system uses the stack 140 to preserve the state of the first task when the first task suspends. As previously described, when a task "A" stops or suspends and a task "B" resumes, a "context switch" occurs.”.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Chrabieh into that of Au, Xu, Kutch and Jadon in order to have the arbitration comprises: beginning processing of a first command for the first tenant; and beginning processing of a second command for the second tenant, wherein processing of the second command begins prior to completion of processing the first command. Au col 7, line 54 – col 8, line 10 teaches using priority as arbitration criteria in round robin fashion. One of ordinary skill can easily see that having a higher priority request preempt an currently executing, lower priority request would be allow the priority arbitration to function more dynamically to improve the efficiency of the scheduling system, such combination would enhance the overall appeals of all references and is therefore rejected under 35 USC 103.
As per claim 15, the combination of Au, Xu, Kutch, Jadon and Chrabieh further teach:
The data storage device of claim 14, wherein the second queue utilizes more bandwidth than the first queue. (Au col 14, limes 35 – 63.)
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Au, Xu and Kutch, and further in view of Chrabieh.
As per claim 19, the combination of Au, Xu and Kutch did not teach:
The data storage device of claim 18, wherein the controller is configured to pause processing a first SGL command prior to completing the first SGL command.
However, Chrabieh teaches:
The data storage device of claim 18, wherein the controller is configured to pause processing a first SGL command prior to completing the first SGL command. (Chrabieh [0038]: “Each task is assigned a priority level, and is associated with a stack 140. A first task may be preempted by a second task with higher priority, for example, which requires the system to momentarily suspend the first task. The system uses the stack 140 to preserve the state of the first task when the first task suspends. As previously described, when a task "A" stops or suspends and a task "B" resumes, a "context switch" occurs.”.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Chrabieh into that of Au, Xu and Kutch in order to have the arbitration comprises: beginning processing of a first command for the first tenant; and beginning processing of a second command for the second tenant, wherein processing of the second command begins prior to completion of processing the first command. Au col 7, line 54 – col 8, line 10 teaches using priority as arbitration criteria in round robin fashion. One of ordinary skill can easily see that having a higher priority request preempt an currently executing, lower priority request would be allow the priority arbitration to function more dynamically to improve the efficiency of the scheduling system, such combination would enhance the overall appeals of all references and is therefore rejected under 35 USC 103.
As per claim 20, the combination of Au, Xu, Kutch and Chrabieh further teach:
The data storage device of claim 19, wherein the controller is further configured to process a second SGL command prior to completing the first SGL command, wherein the second SGL command begins processing after the first SGL command processing begins, and wherein the first SGL command and the second SGL commands are from separate and distinct virtual hosts of the multiple virtual hosts. (Chrabieh [0038]: “Each task is assigned a priority level, and is associated with a stack 140. A first task may be preempted by a second task with higher priority, for example, which requires the system to momentarily suspend the first task. The system uses the stack 140 to preserve the state of the first task when the first task suspends. As previously described, when a task "A" stops or suspends and a task "B" resumes, a "context switch" occurs.”; Kutch [0101: virtual hardware platforms.)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 – 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM.
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/CHARLES M SWIFT/Primary Examiner, Art Unit 2196
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