Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-5, 21-23, 27-30, 32, 34-38, 40-43, and 49-51 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ware et al., US PGPub 2013/0083611, in view of Woo et al., US PGPub 2001/0014049, further in view of Hsu et al., US Patent 9,046,424.
With respect to claim 1, Ware teaches a memory module comprising:
a memory device configured to store received data through a memory interface (par. 78 and fig. 4, memory device 253);
a register clock driver configured to enable a clock and provide the clock to the memory device (par. 78, clock driver 327 forwards the reference clock signal to memory device 253);
wherein the memory module is divided into a first region and a second region based on the memory controller (par. 126, the memory module 805 is divided into sets or “ranks” of memory devices 807), and
wherein the memory device in the first region is operated in a different way than another memory device in the second region (par. 127, different timing calibration values are applied for each rank of memory devices within the memory module, such as different packet, bit and phase adjust values, with a separate set of alignment registers maintained for each group/rank, meaning that a memory device in a first rank is operated in a different way than a memory device in a second rank).
Ware fails to teach a temperature sensor placed on the memory module.
Woo teaches:
a temperature sensor placed on the memory module and configured to sense module temperature (par. 84, a temperature sensing circuit is on memory device 410);
a memory controller configured to control operation of the memory device in response to information regarding temperature sensed by the temperature sensor (pars. 82-84, the memory controller 640 controls operation of memory system 600, based on temperature sensors),
wherein the memory controller operates the memory device in a region based on temperature information measured by the temperature sensor and changes an operation mode of the memory device in the region having a temperature higher than a threshold among the first region and the second region (par. 84, the controller initiates a regulation scheme to reduce the temperature of any memory devices operating above a threshold temperature. The memory devices, such as 610 and 620 correspond to the first and second regions).
Woo and Ware fail to teach a serial presence detect circuit.
Hsu teaches:
a serial presence detect (SPD) circuit configured to store information regarding temperature of the memory module (col. 3, lines 6-15, the SPD).
It would have been obvious to one of ordinary skill in the art, having the teachings of Ware and Woo before him before the earliest effective filing date, to modify the memory module of Ware with the memory module of Woo, in order to avoid memory failure a result of high operating temperature, as taught by Woo in par. 10. Further, it would have been obvious to one of ordinary skill in the art, having the teachings of Ware, Woo and Hsu before him before the earliest effective filing date, to modify the memory module of Ware and Woo with the memory module of Hsu, in order to detect overheating much more quickly than conventional measurements, as taught by Hsu in col. 2, lines 49-59.
With respect to claim 2, Ware, Woo and Hsu teach all limitations of the parent claim. Woo further teaches the memory module according to claim 1, wherein the memory controller adjusts a refresh cycle operation of the memory device in response to information regarding temperature sensed by the temperature sensor (par. 74, the regulation scheme consists of increasing the refresh rate of the memory device).
With respect to claim 4, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 1, further comprising:
a data buffer configured to transfer data from the memory controller to the memory device (par. 32, the data is buffered from a memory controller to meet timing constraints imposed by the memory device).
With respect to claim 5, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 1, further comprising:
a second temperature sensor, wherein the second temperature sensor is placed in a peripheral region of a data buffer (par. 84, the second temperature sensor corresponds to the sensor on memory device 620)
With respect to claim 21, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 1, wherein the register clock driver is configured to enable the clock in response to an enable signal (par. 78, clock driver 327 forwards the reference clock signal to memory device 253 in response to a clock-enable signal EnRCK).
With respect to claim 22, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 1, wherein the register clock driver provides the clock to the memory device while the register clock driver blocks the clock to a second memory device (pars. 73-74, clock drivers 310 and 364 are disabled, and the other clock drivers are enabled, thus providing the clock to some memory devices and blocking the clock to others).
With respect to claim 23, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 1, further comprising:
a power management integrated circuit configured to manage a power applied to the memory device (par. 30 memory controller 101 applies power management policies).
With respect to claim 27, Ware, Woo and Hsu teach all limitations of the parent claim. Hsu further teaches the memory module according to claim 1, wherein the SPD circuit is configured to store information regarding temperature sensed by the temperature sensor (col. 3, lines 6-15, the SPD stores sensed temperature information for transfer).
With respect to claim 28, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 1, further comprising:
a second memory device (par. 84, memory device 620); and
a second temperature sensor placed on a different region than the region on which the temperature sensor is placed (par. par. 84, the second temperature sensor is the one on memory device 620, which is a different region than memory device 610 with the first temperature sensor),
wherein the second memory device operates in a different way than the memory device (par. 84, the memory devices are operated in different ways based on temperature being above a threshold).
With respect to claim 29, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 28, wherein a position of the second temperature sensor is closer to the second memory device than the memory device (par. 84, the second temperature sensor is on memory device 520).
With respect to claim 30, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 28, wherein difference between operation of the second memory device and operation of the memory device is related to difference between temperature sensed by the second temperature sensor and temperature sensed by the temperature sensor (par. 84, memory devices are identified by temperature exceeding a predetermined threshold).
With respect to claim 32, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 1, wherein an operation of the memory device includes at least one of a refresh operation, data transmission, read operation, or write operation, or any combination thereof (par. 134, refresh operation, par. 142, data transmission, and par. 27, memory read or write).
With respect to claim 34, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 32, wherein the operation of the memory device is adjusted by a parameter (par. 65, ADJ_TCK corresponding to the parameter).
With respect to claim 35, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 34, wherein the parameter includes at least one of tREF, tREFI, tREFC, tWR, tRCD, tRP, tAA, tCK, WL, or RL, or any combination thereof (par. 65, ADJ_TCK corresponding to the parameter tCK).
With respect to claim 36, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 32, wherein the operation of the memory device is adjusted in response to Mode Register Set (MRS) information (par. 102, register elements 591 and 592 store mode information for adjusting memory power operation).
With respect to claim 37, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 36, wherein the memory device comprises a register configured to store the MRS information (par. 102, register elements 591 and 592 store mode information).
With respect to claim 38, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 36, wherein the MRS information includes a parameter or an operation mode (par. 102, register elements 591 and 592 store operation mode information).
With respect to claim 40, Ware, Woo and Hsu teach all limitations of the parent claim. Woo further teaches the memory module according to claim 1, wherein the memory device comprises a thermal sensor configured to measure temperature inside the memory device or a thermal sensor in the memory device (par. 84, the temperature sensing circuits are thermal sensors).
With respect to claim 41, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 1, further comprising:
a serial presence detect (SPD) circuit (par. 126, “serial presence detect”), but does not teach that the SPD stores temperature information.
Woo teaches configured to store information regarding temperature of the memory module (par. 84, the temperature sensing circuits store temperature information).
With respect to claim 42, Ware, Woo and Hsu teach all limitations of the parent claim. Hsu further teaches the memory module according to claim 1, wherein the SPD circuit comprises a thermal sensor to monitor the temperature of the memory module (col. 3, lines 6-10, the temperature measurement module including a SPD and thermal diodes).
With respect to claim 43, Ware, Woo and Hsu teach all limitations of the parent claim. Woo further teaches the memory module according to claim 1, wherein the information regarding the temperature of the memory module from the temperature sensor is transmitted to the memory controller (par. 84, the controller 640 controls regulation schemes based on the communicated temperature).
With respect to claim 49, Ware, Woo and Hsu teach all limitations of the parent claim. Ware further teaches the memory module according to claim 1, wherein the register clock driver redistributes the clock received from the memory controller to the memory device (par. 112, the clock driver drives internal reference clock RCK1 in response to the reference clock supplied).
With respect to claim 50, Ware, Woo and Hsu teach all limitations of the parent claim. Hsu further teaches the memory module according to claim 1, wherein the SPD circuit includes the temperature sensor placed on the memory module and configured to sense memory module temperature (col. 3, lines 2-4).
With respect to claim 51, Ware, Woo and Hsu teach all limitations of the parent claim. Hsu further teaches the memory module according to claim 1, wherein the SPD circuit includes a non-volatile memory for storing the information regarding temperature, and wherein the non-volatile memory includes an EEPROM (col. 3, lines 44-48).
Claim(s) 44-48 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ware, Woo and Hsu as applied to claim 1 above, and further in view of Bates et al., US PGPub 2013/0067136
With respect to claim 44, Ware, Woo and Hsu teach all limitations of the parent claim, but fail to teach a module substrate having a first surface and a second surface facing away from each other. Bates further teaches the memory module according to claim 1, further comprising:
a module substrate having a first surface and a second surface facing away from each other (par. 15 and fig. 1, the DIMMs are shown as standard DIMMs which have a first and second surface on each side of the DIMM, thus facing away from each other).
It would have been obvious to one of ordinary skill in the art, having the teachings of Ware, Woo, Hsu and Bates before him before the earliest effective filing date, to modify the memory module of Ware, Woo and Hsu with the memory module of Bates, in order to allow overheated memory modules to cool, as taught by Bates in par. 22.
With respect to claim 45, Ware, Woo, Hsu and Bates teach all limitations of the parent claim. Bates further teaches the memory module according to claim 44, wherein the module substrate comprises short sides along a first direction and long sides along a second direction, and wherein the module substrate comprises a plurality of electrode pads arranged on both sides of the module substrate along an edge in the second direction (par. 15 and fig. 1, the DIMMs are shown as standard DIMMs with electric connections on the bottom).
With respect to claim 46, Ware, Woo, Hsu and Bates teach all limitations of the parent claim. Ware further teaches the memory module according to claim 44, wherein the register clock driver is placed on a first side of the module substrate (par. 73, and fig. 4, the clock drivers are shown on one side of substrate). Bates teaches the temperature sensor on a first side of the module substrate (par. 15 and fig. 1).
With respect to claim 47, Ware, Woo, Hsu and Bates teach all limitations of the parent claim. Bates further teaches the memory module according to claim 44, further comprising:
a second temperature sensor which is placed on the same side of the module substrate as the register clock driver (par. 19, the second temperature sensor 102b is placed on the same side of the substrate).
With respect to claim 48, Ware, Woo and Hsu teach all limitations of the parent claim, but fail to teach the placement of a temperature sensor near an end of a memory module. Bates further teaches the memory module according to claim 1, further comprising:
a second temperature sensor (par. 19, temperature sensor 102b),
wherein each temperature sensor is placed near each end of the memory module (par. 14, the temperature sensors are placed near the DIMM slot for DIMM).
It would have been obvious to one of ordinary skill in the art, having the teachings of Ware, Woo, Hsu and Bates before him before the earliest effective filing date, to modify the memory module of Ware, Woo and Hsu with the memory module of Bates, in order to allow overheated memory modules to cool, as taught by Bates in par. 22.
Claim(s) 3, 31, and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ware, Woo and Hsu as applied to claims 1, 28, and 32 above, and further in view of Ashwood, US PGPub 2009/0094406.
With respect to claim 3, Ware, Woo and Hsu teach all limitations of the parent claim, but fail to teach limiting a power source applied to the memory devices when a sensed temperature is higher than a threshold. Ashwood teaches the memory module according to claim 1, wherein a memory controller limits a power source applied to the memory devices when a sensed temperature is higher than a threshold (par. 110, the memory is powered of when the sensed temperature exceeds a threshold temperature).
It would have been obvious to one of ordinary skill in the art, having the teachings of Ware, Woo, Hsu and Ashwood before him before the earliest effective filing date, to modify the memory device of Ware, Woo and Hsu with the memory device of Ashwood, in order to prevent the memory from being damaged, as taught by Ashwood in par. 110.
With respect to claim 31, Ware, Woo and Hsu teach all limitations of the parent claim, but fail to teach limiting a power source applied to the memory devices when a sensed temperature is higher than a threshold. Ashwood teaches the memory module according to claim 28, wherein a power source to be applied to the second memory device is limited when the second memory device has a temperature higher than a specific temperature (par. 110, the memory is powered of when the sensed temperature exceeds a threshold temperature).
It would have been obvious to one of ordinary skill in the art, having the teachings of Ware, Woo, Hsu and Ashwood before him before the earliest effective filing date, to modify the memory device of Ware, Woo and Hsu with the memory device of Ashwood, in order to prevent the memory from being damaged, as taught by Ashwood in par. 110.
With respect to claim 33, Ware, Woo and Hsu teach all limitations of the parent claim, but fail to teach adjusting operation of the memory device in response to information including sensed temperature by the temperature sensor. Ashwood teaches the memory module according to claim 32, wherein the operation of the memory device is adjusted in response to information including sensed temperature by the temperature sensor or a thermal sensor in the memory device (par. 110, the memory is powered of when the sensed temperature exceeds a threshold temperature).
It would have been obvious to one of ordinary skill in the art, having the teachings of Ware, Woo, and Ashwood before him before the earliest effective filing date, to modify the memory device of Ware, Woo and Hsu with the memory device of Ashwood, in order to prevent the memory from being damaged, as taught by Ashwood in par. 110.
Claim(s) 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ware, Woo and Hsu as applied to claim 23 above, and further in view of Mizuno, US Patent 6,366,506
With respect to claim 24, Ware, Woo and Hsu teach all limitations of the parent claim, but fail to teach a voltage generator configured to generate a plurality of internal voltages. Mizuno teaches the memory module according to claim 23, wherein the power management integrated circuit includes:
a voltage generator configured to generate a plurality of internal voltages (col. 17, lines 4-12, and fig. 27, the voltage conversion circuit REG1 generates a plurality of internal voltages VINT1 to VINTn); and
a storage circuit configured to store information regarding the voltage generator (col. 5, lines 55-60, col. 17, lines 4-12, and GEN1 in fig. 27, GEN1 stores a voltage VPRW1 for the voltage generator REG1).
It would have been obvious to one of ordinary skill in the art, having the teachings of Ware, Woo, Hsu and Mizuno, to modify the semiconductor device of Ware, Woo and Hsu with the semiconductor device of Mizuno, in order to improve voltage conversion efficiency, as taught by Mizuno in col. 16, lines 55-63.
With respect to claim 25, Ware, Woo and Hsu teach all limitations of the parent claim, but fail to teach a low drop-out regulator or switching regulator. Mizuno teaches the memory module according to claim 23, wherein the power management integrated circuit includes at least one of a low drop-out regulator and a switching regulator (col. 14, lines 33-36, the switching regular).
It would have been obvious to one of ordinary skill in the art, having the teachings of Ware, Woo, Hsu and Mizuno, to modify the semiconductor device of Ware, Woo and Hsu with the semiconductor device of Mizuno, as the use of a switching regulator system makes voltage conversion efficiency increase, as taught by Mizuno in col. 14, lines 39-42.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ware, Woo and Hsu as applied to claim 1 above, and further in view of Sun et al., US PGPub 2016/0267954.
With respect to claim 26, Ware, Woo and Hsu teach all limitations of the parent claim, but fail to teach a register clock driver configured to redrive a command and address signal received from a memory controller to the memory device. Sun teaches the memory module according to claim 1, wherein the register clock driver is configured to redrive a command and address signal received from a memory controller to the memory device (pars. 36-37, the RCD receives the control/command/address/clock signals from the memory controller and directs to the memory chips).
It would have been obvious to one of ordinary skill in the art, having the teachings of Ware, Woo, Hsu and Sun before him before the earliest effective filing date, to modify the memory module of Ware, Woo and Hsu with the memory module of Sun, in order to reduce latency, as taught by Sun in par. 46.
Claim(s) 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ware, Woo and Hsu as applied to claim 36 above, and further in view of Byeon, US PGPub 2015/0162911
With respect to claim 39, Ware, Woo and Hsu teach all limitations of the parent claim, but fail to teach wherein the MRS information includes a value regarding sensed temperature by the temperature sensor. Byeon further teaches the memory module according to claim 36, wherein the MRS information includes a value regarding sensed temperature by the temperature sensor (pars. 131-132, the temperature sensor outputs a representation of the detected temperature to the mode register set).
It would have been obvious to one of ordinary skill in the art, having the teachings of Ware, Woo, Hsu and Byeon before him before the earliest effective filing date, to modify the memory device of Ware, Woo and Hsu with the memory device of Byeon, in order to detect a change in temperature and adjust an operating mode, as taught by Byeon in par. 136.
Response to Arguments
Applicant's arguments filed 12/5/2025 have been fully considered but they are not persuasive. Applicant argues on pages 8-9 that Ware allegedly fails to teach "wherein the memory controller operates the memory device in a region based on temperature information measured by the temperature sensor and changes an operation mode of the memory device in the region having a temperature higher than a threshold among the first region and the second region." As evidence of this, Applicant states that Woo controls the operation of memory devices, not the operation of each memory region. However, the examiner is considering the memory system 602 in fig. 10 as the “memory device” of the claim, and the memories 610, 620, and 630 as the regions. Therefore, by operating the memory 610 different than the memory 620, for example, means operating a first region and a second region differently, as claimed.
With respect to Applicant’s arguments on page 9, regarding Woo and Ware failing to teach the new limitation “a serial presence detect circuit configured to store information regarding temperature of the memory module,” the new Hsu reference has been used to teach this new limitation.
Conclusion
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/RYAN DARE/Examiner, Art Unit 2132