Prosecution Insights
Last updated: May 29, 2026
Application No. 18/359,840

MATCH NETWORK DESIGN FOR USE WITH FREQUENCY SWEEPING

Non-Final OA §103
Filed
Jul 26, 2023
Examiner
WELLS, KENNETH B
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Energy Industries Inc.
OA Round
3 (Non-Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1219 granted / 1413 resolved
+18.3% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
32 currently pending
Career history
1444
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
61.0%
+21.0% vs TC avg
§102
13.9%
-26.1% vs TC avg
§112
15.0%
-25.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1413 resolved cases

Office Action

§103
DETAILED ACTION Continued Examination Under 37 CFR 1.114 1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/10/26 has been entered. Claim Objections 2. Claim 16 is objected to because of the following informalities: On the first line of claim 16, the word --wherein-- should be inserted after the comma, and on the second line of this claim, "comprising instructions to" should be deleted. Appropriate correction is required. Claim Rejections - 35 USC § 103 3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Valcore, Jr et al (USP 9,462,672) in view of Backes et al (USPAP 2018/0159222). As to claim 1, Valcore, Jr et al discloses, in figure 1, an input (the input of matching circuit 106); an output (the output of matching circuit 106); and a controller (the unillustrated but inherent or obvious controller in Valcore, Jr et al which performs tuning of matching circuit 106, note that Valcore, Jr et al indicates at column 7, lines 61-64, that matching circuit 106 is tunable, and therefore inherently or obviously there will be some type of controller in figure 1 of Valcore, Jr et al which will output control signals to matching circuit 106 in order to tune it and thereby perform impedance matching between the power sources 160, 162 and the plasma chamber 104). Not disclosed by Valcore, Jr et al are the recited first through third variable reactive components recited on lines 4-6 of claim 1 which are controlled by the controller. Such would have been obvious, however, to one of ordinary skill in the art, the reason being that it was old and well-known in the art before the effective filing date of applicant's invention to use a controller for controlling first through third variable reactive components of a matching circuit, i.e., it would have been obvious to one of ordinary skill in the art that matching circuit 106 shown in figure 1 of Valcore, Jr et al could be implemented as shown in figure 3 of Backes et al, the motivation for using the Backes et al matching circuit illustrated in figure 3 of this reference is a simple specific-for-broad substitution, i.e., Valcore, Jr et al shows the tunable matching network 106 generically as a blank box which would suggest to the ordinarily skilled circuit designer that any known tunable matching network could be used for implementing tunable matching network 106 in figure 1 of Valcore, Jr et al, including that shown in figure 3 of Backes et al. As to the limitations recited on lines 8-10 of claim 1, i.e., controlling the first and second variable reactive components to match a load impedance at the output to a source impedance at the input during a first power state at a first frequency, such will be inherent or obvious during the operation of the Valcore, Jr et al figure 1 controller when the capacitance values of the first and second variable reactive components included within tunable matching circuit 106 are varied in response to control outputs of the above-noted controller, note that such tuning of matching circuit 106 will inherently or obviously occur during a first power state at a first frequency--note the Valcore, Jr et al disclosure at column 7, line 28 through column 20, line 61 where this reference discloses adjusting between power states and frequencies, i.e., changing the output power and frequency of the power sources 160, 162 shown in figure 1 of Valcore, Jr et al between multiple different power states and multiple different frequencies, and note that such variation of the power states and frequencies of power sources 160, 162 will inherently or obviously occur simultaneously with the variation of the capacitance values of the first through third variable reactive components used within matching circuit 106 (as noted above, it would have been obvious to one of ordinary skill in the art to include first through third variable reactive components within Valcore, Jr et al's tunable matching circuit 106 in view of what is shown in figure 3 of Backes et al). As to claim 2, the above-noted unillustrated but inherent controller in Valcore, Jr et al will inherently or obviously be configured to control the above-noted first and second variable reactive components together to match a load impedance at the output to a source impedance at the input during the first power state and to set the third variable reactive component so that frequency sweeping completes tuning during the second power state, i.e., as noted above there will be multiple different power states during the operation of Valcore, Jr et al's figure 1, and as noted above tunable impedance matching circuit 106 can obviously include first and second variable reactive components together (any two of the four variable reactive components shown in figure 3 of Backes et al) which will be adjusted for the purpose of matching the load impedance at the output to the source impedance at the input during different power states, and the third variable reactive component (any additional one of the four variable reactive components shown in figure 3 of Backes et al, other than the above-noted any two variable reactive components) will inherently or obviously be set so that frequency sweeping completes tuning during the second power state, i.e., the disclosure in Valcore, Jr et al of changing the frequencies of the power sources 160, 162 from one value to a next value can be interpreted as frequency sweeping, and such frequency sweeping will inherently or obviously complete the tuning during the different power states. As to claims 3 and 4, note that figure 3 of Backes et al includes a pair of shunt capacitors 302A and 302C, and also includes a pair of series capacitors 302B and 302D. As to claim 5, although not disclosed by Backes et al, forming the variable capacitors 302A-D shown in figure 3 of this reference using an array of fixed reactive components, i.e., using an array of fixed capacitors, wherein each fixed reactive component is switchably engaged and disengaged, would have been obvious to one of ordinary skill in the art, the reason being that it was old and well-known in the art before the effective filing date of applicant's invention to form variable capacitors in this manner, of which fact official notice is taken by the examiner. As to claim 6, the claimed functional limitations will all be inherent during the operation of the Valcore, Jr et al’s figure 1 matching network when it is modified so that the tunable matching circuit 106 is implemented as shown in figure 3 of Backes et al, again note that figure 3 of Backes et al includes a pair of shunt capacitors 302A and 302C, and also includes a pair of series capacitors 302B and 302D, and note further that all of the four capacitors will inherently or obviously be controlled so as to achieve a desired impedance when the frequency of power applied to the match network changes, i.e., as noted above both the power output and frequency output of power sources 160, 162 in figure 1 of Valcore, Jr et al change during operation. As to claim 7, the claimed measurement section can be read on either sensor 210 or sensor 212 shown in figure 1 of Valcore, Jr et al (or, alternatively, the claimed measurement section can be read on sensor 272 shown in figure 7 of Valcore, Jr et al), note that such sensors will inherently or obviously be configured to provide an output indicative of an impedance of a dynamic load presented to a generator, i.e., the impedance of plasma chamber 104 presented to generator 160 and/or 162, and note further that the unillustrated but inherent controller in Valcore, Jr et al's figure 1 will inherently or obviously be configured to control the above-noted variable reactive components within tunable matching circuit 106 based upon the output indicative of an impedance of the dynamic load, i.e., based on the outputs of sensors 210, 212 and/or 272, where such outputs are indicative of the impedance of the dynamic load 104. As to claims 8-13, all of the limitations of these method claims are rejected using the same analysis as set forth above in the rejection of claims 1-7. As to claims 14-16, all of the limitations of these apparatus claims are also rejected using the same analysis as set forth above in the rejection of claims 1-7 (note column 32, lines 31-44, of Valcore, Jr et al where this reference indicates that the figure 1 embodiment can be implemented as a non-transitory processor-readable medium, which will inherently or obviously comprise instructions for performing the source impedance to dynamic load impedance matching disclosed by this reference). As to claim 17, the limitations of this claim are rejected using the same analysis as indicated in the rejection of claim 7 above, i.e., the sensors 210, 212 and/or 272 disclosed by Valcore, Jr et al will inherently or obviously obtain a measure indicative of reflected power, and the disclosure by Valcore, Jr et al of changing between multiple frequencies output from power sources 160, 162 will inherently or obviously perform the function of sweeping the frequency of the power provided during the second power state based upon the reflected power until the power is at the second frequency, i.e., adjusting the frequency of the output of the power sources will inherently or obviously occur in figure 1 of Valcore, Jr et al during the different power states and such will be based on the reflected power measured by sensors 210, 212 and/or 272, and such will occur until the power is at the second frequency. As to claim 18, inherently or obviously in figure 1 of Valcore, Jr et al as modified by Backes et al, as noted above, the frequency output of power sources 160, 162 will be changed during the above-noted second power state until the reflected power measured by sensors 210, 212 and/or 272 is minimized at the above-noted second frequency. As to claims 19 and 20, to the extent that Valcore, Jr et al does not disclose the specific values of the first and second frequency of the power sources 160, 162, such would have been obvious to one of ordinary skill in the art who would have easily recognized that the frequency outputs of these two power sources can be set to any values desired, note that it has long been held that discovering an optimum value of a result effective variable involves only routine skill in the art, see In re Boesch, 617 F.2d 272, 205, 205 USPQ 215 (CCPA 1980). Conclusion 4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B WELLS whose telephone number is (571)272-1757. The examiner can normally be reached Monday-Friday, 8:30am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGIS J BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KENNETH B WELLS/Primary Examiner, Art Unit 2836 April 21, 2026
Read full office action

Prosecution Timeline

Show 1 earlier event
Apr 10, 2025
Non-Final Rejection mailed — §103
Aug 29, 2025
Response Filed
Aug 29, 2025
Response after Non-Final Action
Oct 28, 2025
Response Filed
Nov 10, 2025
Final Rejection mailed — §103
Apr 10, 2026
Request for Continued Examination
Apr 20, 2026
Response after Non-Final Action
Apr 23, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
89%
With Interview (+2.4%)
1y 10m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1413 resolved cases by this examiner. Grant probability derived from career allowance rate.

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