DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/13/2026 has been entered.
Response to Amendment
Acknowledgment is made of the amendment filed 08/13/2026, in which: claim(s) 1 and 16 is/are amended; and the rejection of the claims are traversed. Claim(s) 1-20 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant's arguments filed 08/13/2026, with respect to the rejection(s) of claim(s) 1-9 and 16-20 have been fully considered but they are not persuasive.
In response to Applicant’s arguments that the cited references fail to disclose the collar structure as recited in amended claims 1 and 16 (see page 1-3), Examiner respectfully disagrees. The amended claims limit the collar structure such that a top surface of the bond pad and top surfaces of the semiconductor die are left exposed. As previously set forth, L1 discloses patterning the first non-conductive layer 134 exposes portions of contact pads 132, which are at the top surface of and considered part of the semiconductor die 124, which is an interpretation supported by Applicant’s specification, which states that bond pad 204 is included in semiconductor die 202 ([0008]). Since bond pads are considered a part of the semiconductor die, exposing bond pads is both “leaving exposed the top surface of the bond pad and portions of the top side of the semiconductor die”, as claimed. Additionally, L2’s discloses – in L2 FIG. 22f and associated text – of insulating layer 580 being formed over the collar structure of 516 and top surfaces of bond pads 512 (although 580 is not explicitly shown directly on 512, L2 (215) states that openings 582, which are on 512, are formed in 580, thus 580 is formed on 512). For the same reasons stated above, this is equivalent to “forming a second non-conductive layer over the collar structure, the top surface of the bond pad, and the exposed portions of the top side of the semiconductor die”, as claimed, where 512 is both “a top surface of the bond pad” and “exposed portions of the top side of the semiconductor die”. Therefore, L1, as modified by L2, discloses the limitations of amended claims 1 and 16 under the broadest reasonable interpretation of the claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective fiL1g date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-9, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20120112340 A1, hereinafter L1), and further in view of Lin et al. (US 10777528 B2, hereinafter L2).
Regarding independent claim 1, L1 discloses in L1 FIG. 4d and 4f and associated text A method comprising: forming a first non-conductive layer (134) over a top side a semiconductor die (124); patterning the first non-conductive layer (L1 [0062]) to form a collar structure (as shown) surrounding an opening exposing a top surface of a bond pad of the semiconductor die (132), the collar structure extending over a portion of the top side and leaving exposed the top surface of the bond pad and portions of the top side of the semiconductor die (patterning the first non-conductive layer 134 exposes portions of contact pads 132, which are at the top surface of and considered part of the semiconductor die 124 in accordance with the applicant’s specification ([0008] of the instant application states that bond pad 204 is included in semiconductor die 202), therefore top surfaces of 132 are interpreted as both “the top surface of the bond pad” and “portions of the top side of the semiconductor die”); forming a second non-conductive layer (136), the second non-conductive layer different from the first non-conductive layer (L1 [0056]-[0057], first (134) and second (136) non-conductive layers are different in at least that they are formed in separate steps, at different heights, with different shapes and dimensions, and while the list of disclosed materials for each layer has overlap, the layers are not limited to be the same material by L1, therefore disclosing embodiments in which the materials used are different); patterning the second non-conductive layer to expose the top surface of the bond pad and inner sidewalls of the of the collar structure surrounding the opening such that the second non-conductive layer does not contact the bond pad (L1 [0062]; collar structure, exposed bond pad 132 and inner sidewalls, and lack of contact between second non-conductive layer 136 and bond pad 132 visibly disclosed; please refer to the following figure); and forming a metal redistribution layer (RDL) (152) over the second non-conductive layer and exposed top surface of the bond pad. L1 does not explicitly disclose forming the second non-conductive layer over the collar structure and the exposed portions of the top side of the semiconductor die.
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However, in the same field of endeavor, L2 discloses in L2 FIG. 22a and 22f and associated text forming a second non-conductive layer over the collar structure, the top surface of the bond pad, and the exposed portions of the top side of the semiconductor die (L2 FIG. 22a shows insulating layer 516, which is analogous to 134 of L1 and the claimed first non-conductive layer, is patterned, forming a collar structure prior to the formation of insulating layer 580 over insulating layer 516 and conductive layer 512, which is exposed by openings 522 and analogous to the claimed exposed portions disclosed by L1 as interpreted above (L2 FIG. 22f and (215)), where forming 580 over 512 is interpreted as forming the second-non-conductive layer over both “the top surface of the bond pad” and “the exposed portions of the top side of the semiconductor die”).
L1 teaches a base method of manufacturing a collar structure and insulating layers on a semiconductor die which the claimed invention can be seen as an improvement in that formation of the collar structure by patterning the first non-conductive layer before forming the second non-conductive layer over the collar structure and performing a second patterning step allows for finer control over the resulting patterned collar structure and second non-conductive layer. L2 teaches a known technique of forming a collar structure and forming and patterning a second non-conductive layer over the collar structure that is comparable to the base process/product.
L2’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base method of L1 and the results would have been predictable and resulted in more granular control over the resulting structure of the collar and second non-conductive layer which results in an improved semiconductor device.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding dependent claim 3, L1, as modified by L2, discloses in L1 FIG. 4d and 4f and associated text the method of claim 1. The combined reference does not explicitly disclose that the RDL is characterized as a thick metal RDL having a thickness approximately equal to or greater than 8 microns. However, L1 discloses that the thickness of the second non-conductive layer 136 is 2-30 microns (L1 [0057]). L1 also discloses in L1 FIG. 4h and associated text that the UBM 152 is above the top surface of second non-conductive layer 136 and second non-conductive layer 136 is above the top surface of bond pad 132, which is coincident with the bottom surface of RDL 152. Therefore, it is obvious, if not inherent, that the minimum thickness of RDL 152 corresponds with the disclosed thickness of the second non-conductive layer 136, at least 2-30 microns (overlapping with the claimed range), because doing so would provide a thicker redistribution layer which can have increased surface area for UBMs or RDL traces by expanding horizontally over the top surface of second non-conductive layer 136, improving the versatility of the semiconductor package and durability of the RDL. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to try a range of RDL thicknesses to optimize for properties such as package durability and yield, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding dependent claim 4, L1, as modified by L2, further discloses in L1 FIG. 4d and associated text the collar structure surrounding the opening has an inner portion that directly contacts the top surface of the bond pad and an outer portion that extends beyond an outer perimeter of the bond pad. Please refer to the following figure:
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Regarding dependent claim 5, L1, as modified by L2, discloses in L1 FIG. 4d and associated text the method of claim 1, wherein a portion of the collar structure is formed over a passivation layer (lower portion of first non-conductive layer 134, which contains one or more layers (L1 [0056]), at least one of which is interpreted as a passivation layer; please refer to the figure below) of the semiconductor die. The combined reference does not explicitly disclose that this portion has a thickness approximately equal to or greater than 5 microns. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to try a range of collar structure thicknesses to optimize for properties such as package durability and yield, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
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Regarding dependent claim 6, L1, as modified by L2, further discloses in L1 FIG. 4f and associated text the forming the RDL includes forming a plurality of patterned RDL interconnection traces, a first RDL interconnection trace of the plurality includes a first portion directly connected to the top surface of the bond pad (L1 [0065], redistribution layer 152 may comprise multiple layers; a portion of 152 is electrically connected to 132).
Regarding dependent claim 7, L1, as modified by L2, further discloses in L1 FIG. 4h and associated text forming an under-bump metallization (UBM) structure on a second portion of the first RDL interconnection trace, the UBM structure conductively interconnected with the bond pad by way of the first RDL interconnection trace. Please refer to the following figure:
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Regarding dependent claim 8, L1, as modified by L2, further discloses in L1 FIG. 4d and 4f and associated text the forming the RDL includes forming the RDL by way of sputtering or electroplating a copper material (L1 [0065]).
Regarding dependent claim 9, L1, as modified by L2, further discloses in L1 FIG. 4d and associated text the second non-conductive layer is formed having a thickness greater than that of the first non-conductive layer (second non-conductive layer 136 is thicker than first non-conductive layer 134 as visibly disclosed).
Regarding independent claim 16, L1, as modified by L2, discloses in L1 FIG. 4d and 4f and associated text A method comprising: forming a first non-conductive layer (134) over a top side of a semiconductor die (124); patterning the first non-conductive layer (L1 [0062]) to form a collar structure (as shown) surrounding an opening exposing a top surface of a bond pad of the semiconductor die (132), the collar structure extending over a portion of the top side and leaving exposed the top surface of the bond pad and portions of the top side of the semiconductor die (patterning the first non-conductive layer 134 exposes portions of contact pads 132, which are at the top surface of and considered part of the semiconductor die 124 in accordance with the applicant’s specification ([0008] of the instant application states that bond pad 204 is included in semiconductor die 202), therefore top surfaces of 132 are interpreted as both “the top surface of the bond pad” and “portions of the top side of the semiconductor die”); forming a second non-conductive layer (136), the second non-conductive layer having a mechanical property different from that of the first non-conductive layer (L1 [0056]-[0057], first (134) and second (136) non-conductive layers are different in at least that they are formed in separate steps, at different heights, with different shapes and dimensions, and while the list of disclosed materials for each layer has overlap, the layers are not limited to be the same material by L1, therefore disclosing embodiments in which the materials used are different, and each of these aforementioned differences results in inherent differences in mechanical properties such as dimensions, mass, layer adhesion, etc.); patterning the second non-conductive layer to expose the top surface of the bond pad and inner sidewalls of the of the collar structure surrounding the opening such that the second non-conductive layer does not contact the bond pad (L1 [0062]; collar structure, exposed bond pad 132 and inner sidewalls, and lack of contact between second non-conductive layer 136 and bond pad 132 visibly disclosed; please refer to the following figure); and forming a metal redistribution layer (RDL) (152) over the second non-conductive layer and exposed top surface of the bond pad. L1 does not explicitly disclose forming the second non-conductive layer over the collar structure, the top surface of the bond pad, and the exposed portions of the top side of the semiconductor die.
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However, in the same field of endeavor, L2 discloses in L2 FIG. 22a and 22f and associated text forming a second non-conductive layer over the collar structure, the top surface of the bond pad, and the exposed portions of the top side of the semiconductor die (L2 FIG. 22a shows insulating layer 516, which is analogous to 134 of L1 and the claimed first non-conductive layer, is patterned, forming a collar structure prior to the formation of insulating layer 580 over insulating layer 516 and conductive layer 512, which is exposed by openings 522 and analogous to the claimed exposed portions disclosed by L1 as interpreted above (L2 FIG. 22f and (215)), where forming 580 over 512 is interpreted as forming the second-non-conductive layer over both “the top surface of the bond pad” and “the exposed portions of the top side of the semiconductor die”).
L1 teaches a base method of manufacturing a collar structure and insulating layers on a semiconductor die which the claimed invention can be seen as an improvement in that formation of the collar structure by patterning the first non-conductive layer before forming the second non-conductive layer over the collar structure and performing a second patterning step allows for finer control over the resulting patterned collar structure and second non-conductive layer. L2 teaches a known technique of forming a collar structure and forming and patterning a second non-conductive layer over the collar structure that is comparable to the base process/product.
L2’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base method of L1 and the results would have been predictable and resulted in more granular control over the resulting structure of the collar and second non-conductive layer which results in an improved semiconductor device.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding dependent claim 17, L1, as modified by L2, further discloses in L1 FIG. 4f and associated text forming the RDL includes forming a plurality of patterned RDL interconnection traces, a first RDL interconnection trace of the plurality having a first portion directly connected to the top surface of the bond pad (L1 [0065], redistribution layer 152 may comprise multiple layers; a portion of 152 is electrically connected to 132).
Regarding dependent claim 18, L1, as modified by L2, further discloses in L1 FIG. 4h and associated text forming an under-bump metallization (UBM) structure on a second portion of the first RDL interconnection trace, the UBM structure conductively interconnected with the bond pad by way of the first RDL interconnection trace. Please refer to the following figure:
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Regarding dependent claim 19, L1, as modified by L2, further discloses in L1 FIG. 4d and 4f and associated text the collar structure has an inner portion that directly contacts the top surface of the bond pad and an outer portion that extends beyond an outer perimeter of the bond pad, the collar structure configured to serve as an isolation barrier preventing the second non-conductive layer from directly contacting the top surface of the bond pad (second layer 136 does not contact bond pad 132 as visibly disclosed). Please refer to the following figure:
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Regarding dependent claim 20, L1, as modified by L2, discloses in L1 FIG. 4d and 4f and associated text the method of claim 16, but does not explicitly disclose the further limitations of claim 20. However, L1 discloses that the elongation property of second non-conductive layer 136 is 20-150% and that this value is considered a “high elongation”, implying that its elongation is high with respect to analogous structures in L1’s disclosure, such as that of first non-conductive layer 134 and/or that this range of elongation properties is considered high with respect to those of other materials. While L1 does not explicitly disclose the elongation of first non-conductive layer 134, it would have been obvious to one having ordinary skill in the art at the time the invention was made to try multiple materials with varying elongation properties, including those which would result in the second non-conductive layer having an elongation property higher than that of the first non-conductive layer, to optimize for package durability and yield, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over L1, and further in view of L2 and Sasaki et al. (hereinafter S1).
Regarding dependent claim 20, L1, as modified by L2, discloses the method of claim 16, wherein the first non-conductive layer is characterized as a polyimide material (L1 [0056]). The combined reference does not explicitly disclose the first non-conductive layer is characterized as a polyimide material formulated without sulfur.
However, in the same field of endeavor, S1 discloses the use of polyimide BL-301 in semiconductor package dielectric layers (Section 4) and that BL-301 is formulated without sulfur (Section 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective fiL1g date of the claimed invention to have used a polyimide formulated without sulfur, such as BL-301, for the first non-conductive layer because doing so would provide a layer with high chemical resistance (Section 3.4) and low cure temperature (Section 3.2) to improve the durability of the layer while minimizing thermal stress on the semiconductor package, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20120187584 A1, a patent application with very similar matter to that of L1, but with some variations that may prove pertinent to embodiments of the disclosed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu: 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
