Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the application filed on 07/27/2023.
Claims 1-20 are pending.
Examiner’s Note
Please note that Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
Correction is required. See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 14-16,18 and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Claim 14, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a method claim under Step 1.
14. A method for processing a piece of software, the method comprising:
processing the piece of software to identify a placement of one or more instructions for triggering creation of a hardware tracing record; and
inserting into the piece of software, for each instruction of the one or more instructions, a pre-defined identifier at a pre-defined memory address range relative to a memory address within a deterministic distance of the instruction.
Regarding claim 14, the limitations “processing the piece of software to identify a placement of one or more instructions for triggering creation of a hardware tracing record” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. For example, a person is capable of with the aid of pen and paper to identify instructions and that triggers a tracing record to monitor software execution. Therefore, these limitations encompass a human mind carrying out the function through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2A, the additional elements “inserting into the piece of software, for each instruction of the one or more instructions, a pre-defined identifier at a pre-defined memory address range relative to a memory address within a deterministic distance of the instruction” do nothing more than to add insignificant extra solution activity to the judicial exception of merely storing/gathering data for automation. See MPEP § 2106.05(h).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “inserting into the piece of software, for each instruction of the one or more instructions, a pre-defined identifier at a pre-defined memory address range relative to a memory address within a deterministic distance of the instruction”” the courts have recognized storing and retrieving information in memory as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity. See for example, Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018). See MPEP 2106.05(d). Accordingly, the claims are not patent eligible under 35 USC 101.
15. The method according to claim 14, wherein the placement of the one or more instructions is identified by identifying at least one pre-defined instruction in an assembly code representation of the piece of software.
The limitations for this claim further recite an additional mental process under Step 2A, Prong 1.
16. The method according to claim 14, wherein the placement of the one or more instructions is identified by identifying a pre-defined application programming interface call in a source code representation of the piece of software during compilation of the piece of software.
The limitations for this claim further recite an additional mental process under Step 2A, Prong 1.
17. An apparatus comprising interface circuitry, machine-readable instructions and processor circuitry to execute the machine-readable instructions to perform the method according to claim 1.
The limitation “An apparatus comprising interface circuitry, machine-readable instructions and processor circuitry to execute the machine-readable instructions” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under Step 2A, Prong 2. See MPEP 2106.05(g).
18. An apparatus comprising interface circuitry, machine-readable instructions and processor circuitry to execute the machine-readable instructions to perform the method according to claim 14.
The limitation “An apparatus comprising interface circuitry, machine-readable instructions and processor circuitry to execute the machine-readable instructions” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under Step 2A, Prong 2. See MPEP 2106.05(g).
19. A non-transitory, computer-readable medium comprising a program code that, when the program code is executed on a processor, a computer, or a programmable hardware component, causes the processor, computer, or programmable hardware component to perform the method of claim 1.
The limitation “A non-transitory, computer-readable medium comprising a program code that, when the program code is executed on a processor, a computer, or a programmable hardware component, causes the processor, computer, or programmable hardware component” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under Step 2A, Prong 2. See MPEP 2106.05(g).
20. A non-transitory, computer-readable medium comprising a program code that, when the program code is executed on a processor, a computer, or a programmable hardware component, causes the processor, computer, or programmable hardware component to perform the method of claim 14.
The limitation “A non-transitory, computer-readable medium comprising a program code that, when the program code is executed on a processor, a computer, or a programmable hardware component, causes the processor, computer, or programmable hardware component” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under Step 2A, Prong 2. See MPEP 2106.05(g).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 12-13, 17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by USPN 20060184836 to Al-Omari et al.
Per Claim 1:
Al-Omari discloses:
1. A method for evaluating one or more hardware tracing records related to a hardware tracing operation, the method comprising:
obtaining a hardware tracing record (Paragraph [0073] “collecting raw traces from different sources”), the hardware tracing record comprising a custom information and a memory address within a deterministic distance of (Paragraph [0044] “HTM includes registers for storing a base address of the allocated memory, size (i.e. deterministic distance) of the allocated memory… whether memory is currently allocated to the HTM for storing trace data, and whether the allocated memory is located in this processor's node or another node”) an instruction having triggered the hardware tracing record (Paragraph [0045] “a control routine sends a notice to a hypervisor that is included within the data processing system telling the hypervisor to enable the HTM for tracing”; Paragraph [0090] “Trace triggers 326 include a start trigger, stop trigger, pause trigger, reset trigger, freeze trigger, and an insert mark trigger. The start trigger is used for starting a trace”);
identifying, based on the memory address within the deterministic distance of the instruction (Paragraph [0045] “control routine also indicates a specified size (i.e. deterministic distance) of memory to request to be allocated to the HTM”) having triggered the hardware tracing record (Paragraph [0043,0044] “initial program load (IPL) (i.e., triggered) and completed booting… HTM includes registers for storing a base address of the allocated memory, size of the allocated memory”), a binary module containing the instruction (Paragraph [0044] “bits (i.e., binary) for indicating whether the HTM is enabled for tracing”);
determining, whether a pre-defined identifier is stored at a pre-defined memory address range relative to the memory address (Paragraph [0044] “HTM includes… bits (i.e., pre-defined identifier) for indicating whether the HTM is enabled for tracing”; Paragraph [0093] “a configurable sequential address range, controlled by one or more of the memory controllers, is configured to be allocated to the trace function”) within the deterministic distance of the instruction in the binary module (Paragraph [0046] “hypervisor then enables the HTM for tracing by setting the trace enable bit within the HTM. The hypervisor stores the size (i.e., range) of memory to be allocated in a register that is included within the scan communications (SCOM) bus stage in the HTM”); and
processing information on the hardware tracing record if the pre-defined identifier is stored at the pre-defined memory address range relative to the memory address within the deterministic distance of the instruction (Paragraph [0047] “the trace enable bit is set (i.e., pre-defined identifier is stored), the HTM then requests the hypervisor to allocate the particular size of memory that is specified in its memory control SCOM register. The hypervisor then dynamically allocates memory by selecting locations within its system memory”).
Per Claim 2:
Al-Omari discloses:
2. The method of claim 1, wherein the memory address within the deterministic distance of the instruction is one of the exact address of the instruction that triggered the hardware tracing record (Paragraph [0045] “a control routine sends a notice to a hypervisor that is included within the data processing system telling the hypervisor to enable the HTM for tracing”; Paragraph [0090] “Trace triggers 326 include a start trigger, stop trigger, pause trigger, reset trigger, freeze trigger, and an insert mark trigger. The start trigger is used for starting a trace”), the address of the instruction that follows the instruction that triggered the hardware tracing record, or the address of an instruction at a pre-defined distance to the instruction that triggered the hardware tracing record (Since this appears to be Markush type language requiring at a minimum just one from the list, Al-Omari teaches Paragraph [0083] “Multiple different types of stamps are generated by stamps 320. A start stamp is created in the trace buffer whenever there is a transition from a paused state to a tracing state. This transition is detected using the start trace trigger”).
Per Claim 3:
Al-Omari discloses:
3. The method according to claim 1, wherein the method comprises skipping a hardware tracing record if the determination, whether the pre-defined identifier is stored at the pre-defined memory address range, is negative (Paragraph [0047] “locations are then marked as “defective” (i.e., negative). The contents of these registers are copied to a new location (i.e., skip to new location) before trace data is stored in the selected location”).
Per Claim 4:
Al-Omari discloses:
4. The method according to claim 1, wherein the information on the hardware tracing record is processed with the custom information and with information on the binary module (Paragraph [0086] “Time stamps are generated and inserted in the trace data when certain conditions occur”).
Per Claim 5:
Al-Omari discloses:
5. The method according to claim 1, wherein the hardware tracing record further comprises a timestamp, with the act of identifying the binary module being further based on the timestamp (Paragraph [0083,0086] “Multiple different types of stamps are generated by stamps 320. A start stamp is created in the trace buffer whenever there is a transition from a paused state to a tracing state. This transition is detected using the start trace trigger… Time stamps are generated and inserted in the trace data”).
Per Claim 6:
Al-Omari discloses:
6. The method according to claim 1, wherein pre-defined identifier uniquely identifies a specific hardware tracing operation (Paragraph [0088,0089] “receives instructions that describe all of the information that is needed in order to perform a trace… generates a trace enable signal 322 and signals 324”).
Per Claim 12:
Al-Omari discloses:
12. The method according to claim 1, wherein the method is applied to at least one of a plurality of hardware tracing records retrieved over a transmission channel (Paragraph [0051] “hardware trace data is being transmitted to the system bus. A standard bus protocol is used by these processing units to communication with each other via the standard existing system bus”), and a plurality of hardware tracing records stored in a memory or storage device (Paragraph [0051] “HTM captures hardware trace data in the processor and transmits it to a system memory utilizing a system bus”).
Per Claim 13:
Al-Omari discloses:
13. The method according to claim 1, wherein the hardware tracing record comprises information on a branch type, with the method comprising skipping the hardware tracing record unless the information on the branch type indicates an indirect branch (Paragraph [0047] “contents of these registers are copied to a new location before trace data is stored in the selected locations… the HTM, that access these locations are then redirected to the new locations”) .
Per Claim 17:
Al-Omari discloses:
17. An apparatus comprising interface circuitry, machine-readable instructions and processor circuitry to execute the machine-readable instructions to perform the method according to claim 1 (Fig. 1, element 64 and related discussion).
Per Claim 19:
Al-Omari discloses:
19. A non-transitory, computer-readable medium comprising a program code that, when the program code is executed on a processor, a computer, or a programmable hardware component, causes the processor, computer, or programmable hardware component to perform the method of claim 1 (Paragraph [0139] “a computer readable medium of instructions and a variety of forms and that the present invention applies… such as a floppy disk, a hard disk drive, a RAM, CD-ROMs, DVD-ROMs”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-11, 14, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over USPN 20060184836 to Al-Omari et al. in view of USPN 5446876 to Levine et al.
Per Claim 7:
The rejection of claim 1 is incorporated and further Al-Omari does not explicitly disclose wherein pre-defined identifier uniquely identifies a piece of software.
However, Levine discloses in an analogous computer system wherein pre-defined identifier uniquely identifies a piece of software (Col. 4, line 33-37 “bit field that can be tested to determine if the last architecturally successfully executed instruction was a load or store”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the method of wherein pre-defined identifier uniquely identifies a piece of software as taught by Levine into the method of tracing and allocating memory as taught by Al-Omari. The modification would be obvious because of one of ordinary skill in the art would be motivated to add/incorporate the features of wherein pre-defined identifier uniquely identifies a piece of software to provide an efficient technique for identifying software for uniquely so as to improve tracing of instruction much faster and more efficiently as suggested by Levine (col. 2, lines 51-65).
Per Claim 8:
The rejection of claim 7 is incorporated and further Al-Omari does not explicitly disclose wherein pre-defined identifier uniquely identifies a binary module of a piece of software.
However, Levine discloses in an analogous computer system wherein pre-defined identifier uniquely identifies a binary module of a piece of software (Col. 4, line 39-43 “bit field is provided that can be tested to determine if the last architecturally successfully executed instruction altered the effective to virtual address map”).
The feature of providing wherein pre-defined identifier uniquely identifies a binary module of a piece of software would be obvious for the reasons set forth in the rejection of claim 7.
Per Claim 9:
The rejection of claim 1 is incorporated and further Al-Omari does not explicitly disclose wherein the method is applied to a plurality of hardware tracing records stored in a pre-defined memory region.
However, Levine discloses in an analogous computer system wherein the method is applied to a plurality of hardware tracing records (Col. 3, line 29-30 “tracing tools are used to evaluate program applications (plurality) running on a particular computer system…”) stored in a pre-defined memory region (Col. 9, line 24-44 “memory location at which the data that was operated on by the instructions is logged in the trace buffer 119… if register 113 contains a binary "1" then an address mapping change has occurred”).
The feature of providing wherein the method is applied to a plurality of hardware tracing records stored in a pre-defined memory region would be obvious for the reasons set forth in the rejection of claim 7.
Per Claim 10:
The rejection of claim 9 is incorporated and further Al-Omari does not explicitly disclose wherein the pre-defined memory region is a processor-specific hardware tracing buffer.
However, Levine discloses in an analogous computer system wherein the pre-defined memory region is a processor-specific hardware tracing buffer (Col. 4, line 62-64 “race information includes instructions that executed on the processor and when these instructions executed”).
The feature of providing wherein the pre-defined memory region is a processor-specific hardware tracing buffer would be obvious for the reasons set forth in the rejection of claim 1.
Per Claim 11:
Al-Omari discloses:
11. The method according to claim 9, wherein the pre-defined memory region is specified by the instruction having triggered the hardware tracing record, the method comprising skipping a hardware tracing record if the hardware tracing record is stored outside the pre-defined memory region (Paragraph [0047] “locations are then marked as “defective” (i.e., negative). The contents of these registers are copied to a new location (i.e., skip to new location) before trace data is stored in the selected location”).
Per Claim 14:
Al-Omari discloses:
14. A method for processing a piece of software, the method comprising:
processing the piece of software to identify a placement of one or more instructions (Paragraph [0084] “HTM is enabled and in the run state, a mark stamp will be inserted into the trace data when a mark trigger occurs”) for triggering creation of a hardware tracing record (Paragraph [0045] “a control routine sends a notice to a hypervisor that is included within the data processing system telling the hypervisor to enable the HTM for tracing”; Paragraph [0090] “Trace triggers 326 include a start trigger, stop trigger, pause trigger, reset trigger, freeze trigger, and an insert mark trigger. The start trigger is used for starting a trace”).
at a pre-defined memory address range relative to a memory address within a deterministic distance of the instruction (Paragraph [0044] “HTM includes… bits (i.e., pre-defined identifier) for indicating whether the HTM is enabled for tracing”; (Paragraph [0093] “a configurable sequential address range, controlled by one or more of the memory controllers, is configured to be allocated to the trace function”)).
Al-Omari does not explicitly disclose inserting into the piece of software, for each instruction of the one or more instructions, a pre-defined identifier.
However, Levine discloses in an analogous computer system inserting into the piece of software, for each instruction of the one or more instructions (Col. 3, line 63-65 “trace information includes instructions that executed on the processor and when these instructions executed”), a pre-defined identifier (Col. 4, line 59-60“ a pointer will indicate the address of the next instruction to be executed”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the method of inserting into the piece of software, for each instruction of the one or more instructions, a pre-defined identifier as taught by Levine into the method of tracing and allocating memory as taught by Al-Omari. The modification would be obvious because of one of ordinary skill in the art would be motivated to add/incorporate the features of inserting into the piece of software, for each instruction of the one or more instructions, a pre-defined identifier to provide an efficient technique for identifying software for uniquely so as to improve tracing of instruction much faster and more efficiently as suggested by Levine (col. 2, lines 51-65).
Per Claim 18:
Al-Omari discloses:
18. An apparatus comprising interface circuitry, machine-readable instructions and processor circuitry to execute the machine-readable instructions to perform the method according to claim 14(Fig. 1, element 64 and related discussion).
Per Claim 20:
Al-Omari discloses:
20. A non-transitory, computer-readable medium comprising a program code that, when the program code is executed on a processor, a computer, or a programmable hardware component, causes the processor, computer, or programmable hardware component to perform the method of claim 14 (Paragraph [0139] “a computer readable medium of instructions and a variety of forms and that the present invention applies… such as a floppy disk, a hard disk drive, a RAM, CD-ROMs, DVD-ROMs”).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over USPN 20060184836 to Al-Omari et al. in view of USPN 5446876 to Levine et al. and further in view of USPN 20020040470 to Guthrie et al.
Per Claim 15:
The rejection of claim 14 is incorporated and further neither Al-Omari nor Levine explicitly disclose wherein the placement of the one or more instructions is identified by identifying at least one pre-defined instruction in an assembly code representation of the piece of software.
However, Guthrie discloses in an analogous computer system wherein the placement of the one or more instructions is identified by identifying at least one pre-defined instruction in an assembly code representation of the piece of software (Paragraph [0504-0513] “a unique identifier for the destination interface… pseudo assembler sequence”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the method of wherein the placement of the one or more instructions is identified by identifying at least one pre-defined instruction in an assembly code representation of the piece of software as taught by Guthrie into the method of tracing and allocating memory as taught by the combination system of Al-Omari and Levine. The modification would be obvious because of one of ordinary skill in the art would be motivated to add/incorporate the features of wherein the placement of the one or more instructions is identified by identifying at least one pre-defined instruction in an assembly code representation of the piece of software to provide an efficient technique for hardware tracing capabilities to improvements in the performance of various operations within the system as suggested by Guthrie (paragraph [0002-0005]).
Per Claim 16:
The rejection of claim 14 is incorporated and further neither Al-Omari nor Levine explicitly disclose wherein the placement of the one or more instructions is identified by identifying a pre-defined application programming interface call in a source code representation of the piece of software during compilation of the piece of software.
However, Guthrie discloses in an analogous computer system wherein the placement of the one or more instructions is identified by identifying a pre-defined application programming interface call in a source code representation of the piece of software during compilation of the piece of software (Paragraph [0344] “the execution history recorder 2002 notifies the compiler manager 2004… compiler also determines whether there are any possible exceptions which may occur in the dominant path fragment to be compiled. If so, the necessary pre-exception condition checks are inserted at the beginning of the compiled fragment of code”).
The feature of providing wherein the placement of the one or more instructions is identified by identifying a pre-defined application programming interface call in a source code representation of the piece of software during compilation of the piece of software would be obvious for the reasons set forth in the rejection of claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Related cited arts:
Uhlig, Richard A., and Trevor N. Mudge. "Trace-driven memory simulation: A survey." ACM Computing Surveys (CSUR) 29.2 (1997): pp. 128-170.
Asadi, Hossein, and Hamid Sarbazi-Azad. "DiskAccel: Accelerating disk-based experiments by representative sampling." Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems. 2015. pp. 297-308.
Goldschmidt, Stephen R., and John L. Hennessy. "The accuracy of trace-driven simulations of multiprocessors." ACM SIGMETRICS Performance Evaluation Review 21.1 (1993): pp. 146-157.
US10650174 - The present disclosure relates to a system and method for use in an electronic design environment. Embodiments may include receiving, using at least one processor, an electronic design and generating a unique name for each hardware state element associated with the electronic design. Embodiments may further include generating a unique name for each software state element associated with the electronic design. Embodiments may also include combining a plurality of unique names into an arbitrary expression, wherein the plurality of unique names includes at least one software state unique name and at least one hardware state unique name. Embodiments may further include evaluating the arbitrary expression at one or more discrete time points. Embodiments may also include recording an evaluated expression in an electronic design database.
US20060184835 - A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol. Trigger events are transmitted to the hardware trace facilities utilizing the same standard system bus, where the trigger events are also formatted according to the standard system bus protocol.
US20200371843 - A system and method for evaluating optimization of a hardware engine are described herein. In an example embodiment, a first operation of a desired application is performed using one or more hardware resources each associated with one or more task graphs of a plurality of task graphs. A first result is recorded from a first simulation based on a first task graph of the plurality of task graphs implemented using a first configuration of a first hardware resource associated with the first task graph. A second result is recorded from a second simulation based on a second task graph of the plurality of task graphs implemented using a second configuration of a second hardware resource associated with the second task graph. An interface is generated based on the first result and the second result for rendering by a display device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Satish Rampuria whose telephone number is 571-272-3732. The examiner can normally be reached on Monday-Friday from 8:30 AM to 5:00 PM.
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/Satish Rampuria/Primary Examiner, Art Unit 2193
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