DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on 05/26/2026 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Response to Arguments
The previously issued claim objections are hereby withdrawn in view of the amended claims.
Applicant’s arguments with respect to claim(s) 1 and 20 have been considered but are
moot in view of new grounds of rejection.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-9, 11, 13-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0217765 A1), hereafter “Kim”, and further in view of Lee et al. (US 2022/0085048 A1), hereafter “Lee”.
As to claim 1, Kim teaches a semiconductor memory device comprising:
a peripheral region (Fig. 4A, PS, ⁋ [0027]) including
a lower substrate (SUB, ⁋ [0031]),
higher voltage transistors (PTR, ⁋ [0036]) on the lower substrate,
first lower lines (INL1+INLD1, ⁋⁋ [0038], [0041]) electrically connected to the higher voltage transistors (⁋ [0038]), and
second lower lines (INL3+INLD3, ⁋⁋ [0038], [0041]) electrically connected to the first lower lines over the first lower lines; and
a cell region (CS, ⁋ [0027]) on the peripheral region,
the first lower lines and the second lower lines extending along a first direction (D2, Fig. 4A) parallel to an upper surface of the lower substrate,
the first lower lines including first higher voltage lines (INL1) and first lower voltage lines (INLD1),
the second lower lines including second higher voltage lines (INL3) and second lower voltage lines (INLD3),
the second higher voltage lines (INL3) and the first lower voltage lines (INLD1) being separated in a second direction (D1) parallel to the upper surface of the lower substrate and a third direction (D3) perpendicular to the upper surface of the lower substrate (Fig. 4A),
the second lower voltage lines (INLD3) and the first higher voltage lines (INL1) being separated in the second direction and the third direction (Fig. 4A), and
a vertical plane facing the first direction (D2) and perpendicular to the upper surface of the lower substrate intersects each of the first lower lines (INL1+INLD1) and the second lower lines (INL3+INLD3) (Fig. 4B shows the vertical plane looking into D2 direction and perpendicular to upper surface of SUB).
Kim fails to teach the transistors as higher voltage transistors and the first and second lower lines as higher voltage lines or lower voltage lines.
Lee teaches a similar device wherein the peripheral region contains (⁋ [0044], PERI, Fig. 7B) higher voltage transistors (HVR, ⁋ [0117]) and lower voltage transistors (LVR) with connected metal layers (comparable to applicant’s higher voltage lines or lower voltage lines) (⁋ [0070], 230A+230B+230C+240A+240B+240C).
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute the higher voltage transistors and respective higher voltage lines of Lee into the device of Kim for the purpose of applying a high voltage during a program or erase operation of a memory cell included in the memory cell array. One skilled in the art would understand that a write or erase operation is needed to transfer date properly within a memory device.
Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date to substitute the lower voltage transistors and respective lower voltage lines of Lee into the device of Kim for the purpose of improvements of high-speed operation characteristics and reliability (⁋ [0135]).
As to claim 2, Kim in view of Lee teaches the semiconductor memory device of claim 1, wherein Kim shows the first higher voltage lines face each of the second higher voltage lines along the third direction (Fig. 4A shows INL1 facing INL3 along D3).
As to claim 3, Kim in view of Lee teaches the semiconductor memory device of claim 1, wherein Kim shows the first lower voltage lines face each of the second lower voltage lines along the third direction (Fig. 4A shows INLd1 facing INLd3 along D3).
As to claim 4, Kim in view of Lee teaches the semiconductor memory device of claim 1, wherein Kim shows a gap between the first lower lines and the second lower lines is smaller than a gap between the first lower lines and a gap between the second lower lines (Fig. 4A shows the gap between INL1 and INL3, and the gap between INLd1 and INLd3 are smaller than the gap between INL1 and INLd3, as well as INL3 and INLd3).
As to claim 5, Kim in view of Lee teaches the semiconductor memory device of claim 1, wherein Kim shows the first lower lines further include first dummy lines between the first higher voltage lines and the first lower voltage lines (first lower voltage lines INLd1 are dummy lines).
As to claim 7, Kim in view of Lee teaches the semiconductor memory device of claim 5, wherein Kim shows a first higher voltage line and a first lower voltage line closest adjacent to each other among the first higher voltage lines and the first lower voltage lines are separated from each other with at least one of the first dummy lines interposed therebetween (first lower voltage lines INLd1 are dummy lines, also see objection above).
As to claim 8, Kim in view of Lee teaches the semiconductor memory device of claim 5, wherein Kim shows a gap between the first lower lines and the second lower lines is smaller than a gap between the first lower lines (see claim 4).
As to claim 9, Kim in view of Lee teaches the semiconductor memory device of claim 1, wherein Kim shows the second lower lines further include second dummy lines between the second higher voltage lines and the second lower voltage lines (second lower voltage lines INLd3 are dummy lines).
As to claim 11, Kim in view of Lee teaches the semiconductor memory device of claim 9, wherein Kim shows a second higher voltage line and a second lower voltage line closest adjacent to each other among the second higher voltage lines and the second lower voltage lines are separated from each other with at least one of the second dummy lines interposed therebetween (second lower voltage lines INLd3 are dummy lines, also see objection above).
As to claim 12, Kim in view of Lee teaches the semiconductor memory device of claim 9, Kim fails to teach, wherein a gap between the first lower lines and the second lower lines is greater than a gap between the second lower lines. Kim teaches the gap between the first lower lines and the second lower lines are smaller than a gap between the second lower lines (see claim 4).
Examiner notes the Applicant has not specified a criticality to the dimensions.
If the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device: In re Gardner v. TEC Systems, Inc., 220 USPQ 777.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the device of Kim in view of Lee such that the gap between the first lower lines and the second lower lines is greater than the gap between the second lower lines, as recited in claim 12, because selecting and adjusting relative dimensions to achieve the claimed arrangement would have been a matter within the ordinary skill of the artisan and would not have required undue experimentation or yielded an unexpected result.
As to claim 13, Kim in view Lee teaches the semiconductor memory device of claim 1, wherein Kim shows the peripheral region (PS) further includes middle lines (INL2+INLd2, ⁋⁋ [0038], [0041]) electrically connected to the second lower lines (INL3+INLd3), and the middle lines extend along the second direction (D2) on the second lower lines.
As to claim 14, Kim in view of Lee teaches the semiconductor memory device of claim 13, wherein Kim shows the peripheral region further includes upper lines electrically (Vid3, ⁋ [0042]) connected to the middle lines, and wherein the upper lines extend along the first direction (D2) on the middle lines.
As to claim 15, Kim in view of Lee teaches the semiconductor memory device of claim 14, wherein Kim show the cell region further includes: a cell array comprising a gate stack (⁋ [0069], “The electrodes EL of the electrode structure ST may be used as gate electrodes of transistors”) and vertical channels (VS, ⁋ [0061]) and vertical channels (VS, ⁋ [0061]) penetrating the gate stack along the third direction (D3); and bit lines (Fig. 4B, BL, ⁋ [0074]) extending along the first direction (D1) on the cell array, the bit lines electrically connected to the vertical channels (⁋ [0074], “Each of the bit lines BL may be electrically connected to the vertical semiconductor pattern SP through the bit line contact plug BPLG”) and the upper lines (⁋ [0076]).
As to claim 17, Kim in view of Lee teach the semiconductor memory device of claim 1, wherein Kim fails to show the peripheral region further includes lower voltage transistors on the lower substrate, and the higher voltage transistors and the lower voltage transistors are separated from each other along the first direction.
Lee teaches a similar memory device with a peripheral region (PCS, Fig. 2, ⁋ [0044]) contains a higher voltage and lower voltage transistors separated from each other (⁋ [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the high-voltage and low-voltage transistors as taught by Lee into the semiconductor device of Kim since this configuration would’ve already been known in the art to be used in a peripheral region.
As to claim 19, Kim in view of Lee teaches the semiconductor memory device of claim 1, wherein Kim shows the first higher voltage lines (INL1), the second higher voltage lines, the first lower voltage lines, or the second lower voltage lines are arranged to be immediately adjacent to each other along the second direction (D2) (Fig. 4A shows INL1 to be immediately adjacent in the D2 direction with nothing directly between).
As to claim 20, Kim teaches a semiconductor memory device comprising:
a lower substrate (Fig. 4B, SUB, ⁋ [0031]);
higher voltage transistors (PTR, ⁋ [0036]) on the lower substrate;
first higher voltage lines electrically connected to a higher voltage source/drain region of the higher voltage transistors (see annotated Fig. 4B);
second higher voltage lines electrically connected to the first higher voltage lines on the first higher voltage lines (see annotated Fig. 4B);
first lower voltage lines electrically connected to a lower voltage source/drain region of the higher voltage transistors (see annotated Fig. 4B);
second lower voltage lines electrically connected to the first lower voltage lines on the first lower voltage lines (see annotated Fig. 4B);
a cell array (CS, ⁋ [0027]) on the second lower voltage lines and including a gate stack (⁋ [0069], “The electrodes EL of the electrode structure ST may be used as gate electrodes of transistors”) and vertical channels (VS, ⁋ [0061]) penetrating the gate stack along a vertical direction; and
bit lines (Fig. 4B, BL, ⁋ [0074]) electrically connected to the vertical channels (VS) (⁋ [0074], “Each of the bit lines BL may be electrically connected to the vertical semiconductor pattern SP through the bit line contact plug BPLG”) and the second higher voltage lines (⁋ [0076]),
the first higher voltage lines, the second higher voltage lines, the first lower voltage lines, the second lower voltage lines, and the bit lines extending along a first direction parallel (D1) to an upper surface of the lower substrate, and
a vertical plane perpendicular to the upper surface of the lower substrate intersects each of the first lower voltage lines (see annotated Fig. 4B below) and the second lower voltage lines (see annotated Fig. 4B below) (Fig. 4B shows the vertical plane looking perpendicular to upper surface of SUB).
Kim fails to teach the transistor as a higher voltage transistor and fails to teach higher voltage lines electrically connected to a higher voltage source/drain region of the higher voltage transistor and lower voltage lines electrically connected to a lower voltage source/drain region of the lower of the higher voltage transistors.
Lee teaches a similar device wherein the peripheral region contains (⁋ [0044], PERI, Fig. 7B) higher voltage transistors (HVR, ⁋ [0117]) with source/drain region (236, ⁋ [0129], FIG. 7C) containing an impurity region (236a) containing a first dopant concentration and a second impurity region (236b) containing a greater dopant concentration and connected metal layers (⁋ [0070], 230C+240C).
It would have been obvious to one of ordinary skill in the art before the effective filing date to substitute the high voltage transistors of Lee into the device of Kim because it was already known in the art that Lee’s high voltage configuration may have a reduction in gate induced drain leakage current and thus exhibit good operation characteristics (⁋ [0130]).
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Indication of Allowable Subject Matter
Claims 6, 10, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 6, Kim is the closest prior art and fails to teach wherein a first group of the second higher voltage lines face each of the first higher voltage lines along the third direction, and a second group of the second higher voltage lines face each of the first dummy lines along the third direction.
As to claim 10, Kim is the closest prior art and fails to teach wherein a first group of the first lower voltage lines face each of the second lower voltage lines along the third direction, and a second group of the first lower voltage lines face each of the second dummy lines along the third direction.
As to claim 16, Kim is the closest prior art and fails to teach wherein each of the higher voltage transistors includes a higher voltage source/drain region and a lower voltage source/drain region, and the first higher voltage lines are electrically connected to the higher voltage source/drain region of the higher voltage transistors.
As to claim 18, Kim is the closest prior art and fails to teach wherein each of the higher voltage transistors includes a higher voltage source/drain region and a lower voltage source/drain region, and the first lower voltage lines and the second lower voltage lines are electrically connected to the lower voltage source/drain region of the higher voltage transistors and one of a pair of source/drain regions of the lower voltage transistors.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARNELL HUNTER whose telephone number is (571)270-1796. The examiner can normally be reached Monday - Friday 7:30 am - 4:30pm.
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
