DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to the correspondence filed on 07/27/23. Claims 1-20 are still pending and have been considered below.
Claim Objections
Claim 17 is objected to because of the following informalities: line 9 of the instant claim should be amended to recite, “…and a first group of the memories in a first group…”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 8, 9, 12-15, 17 and 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choquette et al. (2023/0236878).
Claim 1: Choquette et al. discloses a neural network operation apparatus comprising:
memories storing data to perform a neural network operation(parallel processor can be intelligence processing unit, neural processing unit and/or a neural network processor) [pages 2-3, paragraphs 0022-0023];
processors configured to generate a neural network operation result by performing a neural network operation by reading the data(executing tasks) [page 5, paragraphs 0048-0050]; and
crossbars processing data transmission between the processors and the memories [figure 2 | page 5, paragraph 0046], wherein the crossbars comprise:
a first crossbar of a first group processing data transmission between a first group of the processors and a first group of the memories in the first group(streaming multiprocessors are connected via intermediate units/crossbars and memory crossbars to associated cache and/or any other type of memory) [page 6, paragraphs 0055-0057],
a second crossbar of a second group processing data transmission between a second group of the processors and a second group of the memories in the second group(there are no limitations to the number of units in the processing hierarchy and/or memory hierarchy; thus, at least a second processing group having a respective SM and associated memory exists), wherein the first group of processors does not include any processors that are in the second group of processors and wherein the first group of memories does not include any memories that are in the second group of memories(each group has their own respective SM and a corresponding cache/memory portion) [page 6, paragraphs 0055-0057], and
a third crossbar connecting the first crossbar to the second crossbar(intermediate units/crossbars include, without limitation, any number and/or types of units and/or communication paths for routing information between various units in the parallel processor and/or the PP memory…including any number of modular pipe control units acting as an intermediary) [page 6, paragraphs 0055-0057].
Claim 2: Choquette et al. discloses the neural network operation apparatus of claim 1, wherein the number of processors is the same as the number of memories [page 6, paragraphs 0055-0057].
Claim 3: Choquette et al. discloses the neural network operation apparatus of claim 1, wherein the first crossbar is fully connected to the first processors and the first memories comprised in the first group, and wherein the second crossbar is fully connected to the second processors and the second memories in the second group [page 6, paragraphs 0055-0057].
Claim 4: Choquette et al. discloses the neural network operation apparatus of claim 1, wherein the third crossbar connects a first processor in the first group to a second processor in the second group [page 6, paragraphs 0055-0057].
Claim 8: Choquette et al. discloses a neural network operation apparatus comprising:
memories storing data to perform a neural network operation [pages 2-3, paragraphs 0022-0023];
processors configured to generate a neural network operation result by performing a neural network operation by reading the data [page 5, paragraphs 0048-0050]; and
crossbars processing data transmission between the processors and the memories [figure 2 | page 5, paragraph 0046], wherein the crossbars comprise:
a first crossbar processing data transmission between a first group of the processors and a first group of the memories in a first group [page 6, paragraphs 0055-0057],
a second crossbar processing data transmission between a second group of the processors and a second group of the memories in a second group, wherein the first group of processors does not include any processors that are in the second group of processors and wherein the first group of memories does not include any memories that are in the second group of memories [page 6, paragraphs 0055-0057], and
a third crossbar connecting the first crossbar to the second crossbar, wherein a portion of the processors are each directly connected to the third crossbar [page 6, paragraphs 0055-0057].
Claim 9: Choquette et al. discloses the neural network operation apparatus of claim 8, wherein the portion of the processors is different from a processor comprised in the first group or a processor comprised in the second group [page 6, paragraphs 0055-0057].
Claim 12: Choquette et al. discloses the neural network operation apparatus of claim 8, wherein the number of processors is the same as the number of memories [page 6, paragraphs 0055-0057].
Claim 13: Choquette et al. discloses the neural network operation apparatus of claim 8, wherein the first crossbar is fully connected to the processors and the memories in the first group, and wherein the second crossbar is fully connected to the processors and the memories in the second group [page 6, paragraphs 0055-0057].
Claim 14: Choquette et al. discloses the neural network operation apparatus of claim 8, wherein the third crossbar connects a first processor in the first group to a second processor in the second group [page 6, paragraphs 0055-0057].
Claim 15: Choquette et al. discloses the neural network operation apparatus of claim 8, wherein the portion of the processors is configured to: read some of the data from a first memory in the first group through the third crossbar and the first crossbar, and write some of the neural network operation result into a second memory in the second group through the third crossbar and the second crossbar [page 6, paragraphs 0057-0058].
Claim 17: Choquette et al. discloses a neural network operation method comprising:
reading data to perform a neural network operation from memories through at least one crossbar [pages 2-3, paragraphs 0022-0023];
generating a neural network operation result by performing a neural network operation using the data through processors [page 5, paragraphs 0048-0050]; and
writing the neural network operation result in the memories through crossbars [figure 2 | page 5, paragraph 0046],
wherein the crossbars comprise:
a first crossbar processing data transmission between a first group of the processors and a second group of the memories in a first group [page 6, paragraphs 0055-0057],
a second crossbar processing data transmission between a second group of the processors and a second group of the memories, wherein the first group of processors does not include any processors that are in the second group of processors and wherein the first group of memories does not include any memories that are in the second group of memories [page 6, paragraphs 0055-0057], and
a third crossbar connecting the first crossbar to the second crossbar [page 6, paragraphs 0055-0057].
Claim 18: Choquette et al. discloses the neural network operation method of claim 17, wherein the third crossbar connects a first processor in the first group to a second processor in the second group [page 6, paragraphs 0055-0057].
Allowable Subject Matter
Claims 5-7, 10, 11, 16, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhao et al. (2022/0261650).
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/EDWARD ZEE/Primary Examiner, Art Unit 2435