Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the arguments do not apply to the combination of references being used in the current rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites the limitation "the printed" in line 7. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites the limitation "the connector" in line 7. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim (s) 1-3, 5-7, 13-18 and 20 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Koide (US 8289728).
Regarding claim 1, Koide discloses an apparatus (100;Fig.1) comprising: a substrate (30;Fig.1); a printed circuit board (10) coupled to the substrate; and a member (20) disposed between the substrate and the printed circuit board and configured to restrain at least one of the substrate or the printed circuit board ( 20 is a stiffening member between 10 and 30), the member comprising a via (see vias 24 connecting between 10 and 30) in , the via being coupled to the printed circuit board and to the substrate ( vias 24 electrically connect between 10 and 30).
Regarding claim 2, Koide discloses wherein an area of a first surface of the member adjacent to a first surface of the substrate is characterized by about a same area size as an area of the first surface of the substrate (see foot print of 20 on top of 30;Fig.1).
Regarding claim 3, Koide discloses wherein the member is configured to uniformly restrain the substrate across the area of the first surface of the substrate (see 20 is a stiffening member for 30).
Regarding claim 5, the Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP §2114. The recitation of “, wherein the member is configured to reduce out-of-plane warpage of the semiconductor device by at least 50% relative to an equivalent apparatus lacking the member” does not distinguish the present invention over the prior art of Koide who teaches the structure as claimed.
Regarding claim 6, Koide discloses wherein an area of a second surface of the member adjacent to a first surface of the printed circuit board is characterized by about a same area size as an area of the first surface of the printed circuit board (see Fig.1).
Regarding claim 7, Koide discloses the member is formed from at least one of a polymer (20 is made from a polyimide).
Regarding claim 13, Koide discloses, in Fig.6, a semiconductor device comprising: a substrate comprising an interconnect (interconnects within 10a that connect 11a with 20a;Fig.6) ; a printed circuit board (30a) configured to couple to the interconnect of the substrate; and a member (20a) between the substrate (10a) and the printed circuit board (30a) and configured to restrain at least one of the substrate or the printed circuit board, the member comprising a via (24a) coupling the interconnect of the substrate (interconnects within 10a) to the printed circuit board (30a).
Regarding claim 14, Koide discloses wherein a first surface of the member (top surface of 20a ) adjacent to a first surface of the substrate (bottom of 10a) uniformly restrains the substrate across the first surface of the substrate (see bottom of 10a).
Regarding claim 15, Koide discloses wherein an area of a first surface of the member adjacent to a first surface of the substrate is larger than an area of the first surface of the substrate ( see area of top surface of 20a compared to area of bottom surface of 10a;Fig.6).
Regarding claim 16, Koide discloses, wherein the member is a single layer of material, and wherein the single layer of material is formed from at least one of copper ( metal plates 22-1 and 22-2 are made from copper).
Regarding claim 17, Koide discloses wherein a second surface of the member (bottom surface of 20a) adjacent to a first surface of the printed circuit board (top surface of 30a) uniformly restrains the printed circuit board across the first surface of the printed circuit board (top surface of 30a).
Regarding claim 18, Koide discloses, wherein the member (20) is a single layer of material, and wherein, and wherein the single layer of material is formed from polymer (20 is made from a polyimide).
Regarding claim 20 , Koide discloses ,in Fig.6, a method comprising: providing a substrate (10a); providing a printed circuit board (30a); and coupling a member (20a) to between the substrate and the printed circuit board, the member configured to restrain at least one of the substrate or the printed circuit board (see Fig.6), wherein the member is between the substrate (10a) and the connector (30a) and comprises a via (24a), the via being coupled to the printed circuit board and to the substrate (24a electrically connects 10a with 30a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103(a) as being unpatentable over Koide, as applied to claim 1 above, and further in view of Turner (US2022/0029606 A1).
Regarding claim 4 Koide fails to specifically disclose wherein an area of a first surface of the member adjacent to a first surface of the substrate is smaller than a second surface of the member adjacent to a first surface of the printed circuit board.
Turner discloses , in Fig. 4B, wherein an area of a first surface of the member (top surface area of 450 that faces 405) adjacent to a first surface of the substrate (405) is smaller than a second surface (bottom surface of 450 that faces 490) of the member adjacent to a first surface of the printed circuit board ( top surface of 490).
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to use teachings of Turner to modify the member of Koide in order to accommodate more electronic components to perform various circuit operations.
Claim 8 and 12 is rejected under 35 U.S.C. 103(a) as being unpatentable over Koide, as applied to claim 1 above, and further in view of Wang et al. (US 2024/0014147 A1) hereinafter Wang.
Regarding claim 8, Koide fails to specifically disclose wherein the member is formed from at least one of aluminum, steel, stainless steel, or Teflon.
Wang discloses aluminum (see 150 made of aluminum; [0056]).
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to use teachings of Wang to modify the member of Koide in order to provide structural support to a substrate device.
Regarding claim 12, Koide discloses the member is formed comprises a polymer (20 is made from a polyimide).
Koide fails to specifically disclose the via comprises at least one of copper, aluminum, gold, silver, tin, nickel, or lead.
Wang discloses a via having copper ([0076]).
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to use teachings of Wang to modify the member of Koide in order to provide superior conductivity to the circuit.
Claims 9,11, and 19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Koide, as applied to claim 1 and 13 above, and further in view of Colgan et al. (US 2024/0203822 A1) hereinafter referred to as Colgan.
Regarding claim 9, Koide fails to specifically disclose wherein the member has a about a same coefficient of thermal expansion as the substrate.
Colgan teaches “coefficient of thermal expansion (CTE)” [0005] ln 01-02, and “interposers fabricated from CTE-matched to silicon” [0039] ln 10-11. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the member of Koide to have a CTE matched to silicon as taught by Colgan to be a member (interposer) CTE-matched to a substrate (about the same coefficient of thermal expansion as a substrate) because silicon is an abundant and cost effective material that is commonly used for substrates in semiconductor manufacturing.
Regarding claim 11, Koide fails to specifically disclose wherein a ratio between a length of the member and a thickness of the member is equal or greater than 10:1.
However, Colgan teaches that in particular embodiments interposers can have dimensions of 77mm in length, 87mm in width, and 0.5mm in thickness (“interposers are 77 x 87 x 0.5 mm in size” ([0039] ln 6-7). With these values Colgan teaches a ratio greater than 10:1. For example, a member (interposer) length of 77mm and a member (interposer) thickness of 0.5mm results in a ratio of 154:1 between member (interposer) length and thickness.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the member (interposer) of Koide to have particular dimensions as taught by Colgan in a particular embodiment in order to arrive at a ratio greater than 10:1 between the length and thickness of the member(interposer) because thinned interposers provide an improved method in etching through-silicon vias (“interposers are generally thin, about 0.05-0.2mm thick, due to the etching process to form through-silicon vias” [0006] ln 14-16).
Regarding claim 19, Koide fails to specifically disclose wherein the via is located in a first layer of the member, and the member further comprises a second redistribution layer electrically coupled to the via.
Colgan discloses the semiconductor device of claim 13, wherein the via (fig 1, 124) is located in a first layer of the member (114), and the member further comprises a second redistribution layer (120 and 122) electrically coupled to the via (“interposer 114 includes redistribution wiring layers (RDLs) 120 and 122 with vias 124 connecting the RDLs”, [0030] ln 12-14).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the teachings of Colgan to modify the member of Koide in order to perform circuit operations.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Koide , as applied to claim 1 above, and in view of Xu et al. (US 2024/0121884 A1) hereinafter referred to as Xu.
Regarding claim 10, Koide discloses wherein the member (20) comprises at least two adjacent vias (24).
However, Koide does not disclose wherein a ratio between a distance between the at least two adjacent vias and a width of each via of the at least two adjacent vias is at least 2:1.
Xu teaches the “distance 128 between adjacent vias 114 may be selected based on the wavelength of the electromagnetic field received through the vias”, [0037] ln 12-14.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a member (interposer) with adjacent vias as disclosed by Koide to vary the distance between adjacent vias as taught by Xu in order to arrive at a ratio of 2:1 between distance (between adjacent vias) and width (of each via) because electromagnetic field requirements (such as loss and interference) can be achieved by varying the separation of metallic conductors such as vias passing through an member (interposer).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached on (571) 272-5359. The fax phone number for the organization where this application or proceeding is assigned is 571-272-2229. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2847
