ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 13-14, 16-17, 19-20 are rejected under 35 U.S.C. 102(a)(2) as being unpatentable over Colgan et al. (US 2024/0203822 A1) hereinafter referred to as Colgan.
Regarding claims 1, Colgan discloses an apparatus (fig 1, processor module 100) comprising: a substrate (wafer 128); a connector (chips 102 inherently have “connectors”) coupled to the substrate; and a member (interposer 114) disposed between the substrate (128) and the connector (102) and configured to restrain at least one of the substrate or the connector (member 114 is inherently providing restraint to the substrate 128 or the connector 102), the member (114) comprising a via (124), the via being coupled to the connector (102) and to the substrate (128).
Regarding claim 2, Colgan discloses the apparatus of claim 1, wherein an area of a first surface of the member (interposer 114) adjacent to a first surface of the substrate (wafer 128) is characterized by about a same area size as an area of the first surface of the substrate (“interposer can be mounted onto a handler wafer with a removable adhesive layer” [0030] ln 28-29). Examiner interprets prior art as member (interposer 114) and substrate (wafer 128) are about a same area size since they can be attached to each other by adhesive in order to provide mechanical support, and also fig 1 shows member 114 and substrate 128 being of approximate size and hence about a same area size.
Regarding claim 3, Colgan discloses the apparatus of claim 2, wherein the member (interposer 114) is configured to uniformly restrain the substrate (wafer 128) across the area of the first surface of the substrate (“interposer can be mounted onto a handler wafer with a removable adhesive layer” [0030] ln 28-29). Examiner interprets prior art as member (114) uniformly restraining substrate (128) across a surface area since the adhesive is applied across the entire surface area, thus resulting in a uniform restraint).
Regarding claim 5, Colgan discloses the apparatus of claim 1, wherein the connector (chips 102 inherently contains connectors) comprises a printed circuit board (“chips 102 are processors or computational units” [0030] ln 5-6). Examiner interprets prior art as printed circuit boards (chips/processors/computational units) as being inherent present in printed circuit boards.
Regarding claim 13, Colgan discloses a semiconductor device (fig 1, 100) comprising: a substrate (128) comprising an interconnect (land grid array LGA 126); a connector (chips 102 inherently have “connectors”) configured to couple to the interconnect of the substrate (examiner interprets connector 102 being coupled to interconnect (126) by means of vias 124); and a member (114) between the substrate (128) and the connector (102) and configured to restrain at least one of the substrate or the connector (examiner interprets member 114 is inherently restraining substrate 128 and connector 102 as shown if fig 1), the member (114) comprising a via (124) coupling the interconnect (126) of the substrate (128) to the connector (102). As additional support, Colgan states “chips 102 attached to the interposer 114 by connectors” [0030] ln 9-11, and “interposer mounted onto handler wafer” [0030] ln 28-29).
Regarding claim 14, Colgan discloses the semiconductor device of claim 13, wherein a first surface of the member (fig 1, interposer 114) adjacent to a first surface of the substrate (wafer 128) uniformly restrains the substrate across the first surface of the substrate (“interposer can be mounted onto a handler wafer with a removable adhesive layer” [0030] ln 28-29). Examiner interprets that member (114) is inherently restraining the substrate (128) across its surface due to adhesive being utilized.
Regarding claim 16, Colgan discloses the semiconductor device of claim 13, wherein the connector (chips 102 inherently contain connectors) comprises a printed circuit board (“chips 102 are processors or computational units” [0030] ln 5-6). Examiner interprets that connector 102 contains processors/computational units which are inherently present in printed circuit boards.
Regarding claim 17, Colgan discloses the semiconductor device of claim 16, wherein a second surface of the member (fig 1, interposer 114) adjacent to a first surface of the printed circuit board (chips 102 inherently present in printed circuit boards) uniformly restrains the printed circuit board across the first surface of the printed circuit board. Examiner interprets that Fig 1 shows member (114) inherently restraining the printed circuit board (102) across a surface.
Regarding claim 19, Colgan discloses the semiconductor device of claim 13, wherein the via (fig 1, 124) is located in a first layer of the member (114), and the member further comprises a second redistribution layer (120 and 122) electrically coupled to the via (“interposer 114 includes redistribution wiring layers (RDLs) 120 and 122 with vias 124 connecting the RDLs”, [0030] ln 12-14).
Regarding claim 20, Colgan discloses a method comprising: providing a substrate (fig 1, wafer 128); providing a connector (chips 102 inherently have connectors); and coupling a member (interposer 114) to the substrate (128) and the connector (102), the member configured to restrain at least one of the substrate or the connector (examiner interprets that member 114 is inherently providing restraint to substrate 128 and connector 102), wherein the member (114) is between the substrate (128) and the connector (102) and comprises a via (124), the via being coupled to the connector (102) and to the substrate (128). As additional support, Colgan discloses “chips 102 attached to the interposer 114 by connectors” [0030] ln 9-11, and “interposer mounted onto handler wafer” [0030] ln 28-29).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Colgan et al. (US 2024/0203822 A1) in view of Turner et al. (US 2022/0029606 A1) hereinafter referred to as Turner.
Regarding claim 4, Colgan discloses the apparatus of claim 1. Colgan discloses a member (114) adjacent to a substrate (128) and adjacent to a connector (102). However, Colgan does not disclose wherein an area of a first surface of the member adjacent to a first surface of the substrate is smaller than a second surface of the member adjacent to a first surface of the connector.
Note: examiner is interpreting this claim as the surface area of the member (interposer) on the side adjacent to the substrate is smaller than the surface area of the member on the side adjacent to the connector. Examiner interprets that this reduced surface area on only one side of the member is taught by Turner below where the member (interposer) has a recess on only one side.
Turner teaches an interposer with a recess on only one side (“Fig 4A, interposer 450 includes recesses 455”, [0052] ln 01). Examiner interprets that this inherently reduces the surface area on only one side of the member (interposer).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a member (interposer) adjacent to a substrate and adjacent to a connector as disclosed by Colgan and then to add a recess as taught by Turner to only one side of the interposer (such as side adjacent to the substrate as in Colgan) in order to produce an member (interposer) with smaller surface area on the side adjacent to the substrate because recesses in interposers can be used to allow space for different components. For example, Turner discloses “such recesses may be required to ensure sufficient spacing between diaphragms” [0052] ln 6-7.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Colgan et al. (US 2024/0203822 A1) in view of Lin et al. (US 2024/0063128 A1) hereinafter referred to as Lin.
Regarding claim 6, Colgan discloses the apparatus of claim 5. Colgan discloses a member (114) adjacent to a printed circuit board (chips 102). However, Colgan does not disclose wherein an area of a second surface of the member adjacent to a first surface of the printed circuit board is characterized by about a same area size as an area of the first surface of the printed circuit board.
Lin discloses a member (fig 1B, interposer 108) adjacent to a printed circuit board (multi die frame 202). Examiner interprets fig 1B as showing surface of member (interposer 108) and surface of printed circuit board (202) as being about the same area size since they are about the same length.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ an member (interposer) adjacent to a printed circuit board as disclosed by Colgan and to employ a member/printed circuit board combination of about the same surface area as taught by Lin because redistribution layers within an interposer (darker gray lines within interposer 108 in fig 1B) allow an interposer to connect elements in a printed circuit board across the entire surface area of the interposer/printed circuit board combination.
Claim 7-9, 11, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Colgan et al. (US 2024/0203822 A1) hereinafter referred to as Colgan.
Regarding claim 7, Colgan discloses the apparatus of claim 1. Colgan discloses a connector (fig 1, chips 102). However, Colgan’s embodiment of figure 1 does not disclose wherein the connector comprises at least one of an optical connector, a high-speed data connector, a high-power connector, or a backplane connector.
However, Colgan’s discloses and alternate embodiment with a high-power connector (“active interposer can include active devices for power conversion” [0031] ln 4-6).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify a connector embodiment as taught by Colgan to contain an active interposer with a high-power connector as proposed in Colgan’s alternate embodiment because power conversion is useful in order to couple to other chips on the handler wafer.
Regarding claim 8, Colgan discloses the apparatus of claim 7, wherein an area of a second surface of the member (interposer 114) adjacent to a first surface of the connector (chips 102 inherently have connectors) is characterized by about a same area size or larger area size as an area of the first surface of the connector (“if devices are added to interposer they could be formed on top, bottom, or both surfaces” [0031] ln 8-9). Examiner interprets that adding devices to a surface of the member (114) inherently results in the surface area of the member (114) adjacent to the connector (102) being larger than the surface area of the connector when the connector (102) does not span the entire surface area of the member (114) as shown by Colgan in Fig 1.
Regarding claim 9, Colgan discloses the apparatus of claim 1. Colgan discloses a member (interposer 114) and a substrate (128), but does not disclose wherein the member has a about a same coefficient of thermal expansion as the substrate
However, Colgan teaches “coefficient of thermal expansion (CTE)” [0005] ln 01-02, and “interposers fabricated from CTE-matched to silicon” [0039] ln 10-11.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the member (interposer) CTE-matched to silicon as taught by Colgan to be a member (interposer) CTE-matched to a substrate (about the same coefficient of thermal expansion as a substrate) because silicon is an abundant and cost effective material that is commonly used for substrates in semiconductor manufacturing.
Regarding claim 11, Colgan discloses the apparatus of claim 1. Colgan discloses a member (interposer 114) but does not disclose wherein a ratio between a length of the member and a thickness of the member is equal or greater than 10:1.
However, Colgan teaches that in particular embodiments interposers can have dimensions of 77mm in length, 87mm in width, and 0.5mm in thickness (“interposers are 77 x 87 x 0.5 mm in size” ([0039] ln 6-7). With these values Colgan teaches a ratio greater than 10:1. For example, a member (interposer) length of 77mm and a member (interposer) thickness of 0.5mm results in a ratio of 154:1 between member (interposer) length and thickness.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the member (interposer) as taught by Colgan to have particular dimensions as taught by Colgan in a particular embodiment in order to arrive at a ratio greater than 10:1 between the length and thickness of the member(interposer) because thinned interposers provide an improved method in etching through-silicon vias (“interposers are generally thin, about 0.05-0.2mm thick, due to the etching process to form through-silicon vias” [0006] ln 14-16).
Regarding claim 18, Colgan discloses the semiconductor device of claim 13. Colgan’s embodiment of figure 1 does not disclose wherein the connector comprises at least one of an optical connector, a high-speed data connector, a high-power connector, or a backplane connector.
However, Colgan’s teaches an alternate embodiment with a high-power connector (“active interposer can include active devices for power conversion” [0031] ln 4-6).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify a first embodiment containing a connector as taught by Colgan to contain a high-power connector (devices for power conversion) as proposed in Colgan’s alternate embodiment because power conversion is useful in order to couple to other chips on the handler wafer.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Colgan et al. (US 2024/0203822 A1) in view of Xu et al. (US 2024/0121884 A1) hereinafter referred to as Xu.
Regarding claim 10, Colgan discloses the apparatus of claim 1. Colgan also discloses wherein the member (114) comprises at least two adjacent vias (124).
However, Colgan does not disclose wherein a ratio between a distance between the at least two adjacent vias and a width of each via of the at least two adjacent vias is at least 2:1.
Xu teaches the “distance 128 between adjacent vias 114 may be selected based on the wavelength of the electromagnetic field received through the vias”, [0037] ln 12-14.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a member (interposer) with adjacent vias as disclosed by Colgan and to vary the distance between adjacent vias as taught by Xu in order to arrive at a ratio of 2:1 between distance (between adjacent vias) and width (of each via) because electromagnetic field requirements (such as loss and interference) can be achieved by varying the separation of metallic conductors such as vias passing through an member (interposer).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Colgan et al. (US 2024/0203822 A1) in view of Nair et al. (US 10,475,750 B2) hereinafter referred to as Nair.
Regarding claim 12, Colgan discloses the apparatus of claim 1, wherein the member (114) comprises at least one of copper, aluminum, ceramic, steel, stainless steel, Teflon, silicon, or polymer. Colgan teaches that member (114) can be made of silicon (“silicon carriers, also called interposers” [0006] ln 8-9). Colgan does not disclose wherein the via comprises at least one of copper, aluminum, gold, silver, tin, nickel, or lead
Nair teaches a via (fig 6, 625) made from copper.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify a via as disclosed by Colgan to contain a copper via as taught by Nair because copper offers very low resistance to electrical current and therefore reduces parasitic resistance and inductance in a connection to other electronic devices.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Colgan et al. (US 2024/0203822 A1) in view of Pasdast et al. (US 2023/0197676 A1) hereinafter referred to as Pasdast.
Regarding claim 15, Colgan discloses the semiconductor device of claim 13. Colgan discloses a member (114) adjacent to substrate (128) but Colgan not disclose wherein an area of a first surface of the member adjacent to a first surface of the substrate is larger than an area of the first surface of the substrate.
Pasdast teaches a member (“106 containing one or more interposers 122” [0080] ln 1-2, fig 1) adjacent to a substrate (134), and also teaches that the surface area of the member (106) is larger than the surface area of the substrate (134) by showing in fig 1 that the member (106) is longer in length than substrate (134).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a member (interposer) and substrate combination as disclosed by Colgan to have a member (106 containing one or more interposers) that has surface area larger than the surface area of the substrate as taught by Pasdast because a substrate partially covering an interposer can used to expose interposer vias in order to establish a less resistive connection without going through the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN OSCAR RIVAS whose telephone number is (571)272-5529. The examiner can normally be reached M-F 0900-0500.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached on (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R./Examiner
Art Unit 2812
05 Dec. 2025
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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