DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment dated 01/05/2026 has been acknowledged. Claims 1, 4-8 and 11-20 are amended. No claims are canceled and no new claims are added. Claims 1-20 remain pending in applications.
Response to Arguments
Arguments dated 01/05/2026 has been acknowledged but are moot as a new ground of rejection has been made in view of the same primary reference OKADA and none of the arguments apply to the new rejection (see claim 1 rejection below).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OKADA (US 2021/0082897 A1)
Regarding claim 1, OKADA teaches,
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A semiconductor storage device (FIG. 24 as annotated above), comprising:
a first chip (C1, para [0066]) including a substrate (including 300, 301 & 302, para [0096]);
and a second chip (C2, para [0066]) contacting the first chip, the second chip including a memory cell array (MCA, para [0078]) including a plurality of first wiring layers (conductive layers 110, para [0080]) spaced apart from each other in a first direction (direction Z)
and a memory pillar (including semiconductor layer 120 and gate insulating film & a charge storage film formed between 120 and 110, see para [0080]) that penetrates the plurality of first wiring layers in the first direction, wherein the device includes:
a plurality of first connection pads (bonding electrodes Pl1, para [0066] as marked) in a boundary region between the first chip (C2) and the second chip (C1) in the first direction;
a plurality of first contacts (as marked) extending in the first direction (direction Z) from the plurality of first connection pads;
a first insulator layer (220, para [0087]) surrounding the plurality of first contacts in a first plane parallel to the substrate (as seen);
and a first insulating member (501, para [0139]) adjacent to the first insulator layer (220) in the first plane, the first insulator layer (220) separating the first member (501) from the plurality of first contacts (as seen), and the first insulating member having a stress value different from a stress value of the first insulator layer (501 may be formed of stacked layer of silicon oxide and silicon nitride, para [0140], and 220 may be formed of silicon oxide, para, [0087]. Silicon nitride has a different stress value than silicon oxide similar to the disclosure where insulating member (BE) made of silicon nitride has different stress value than insulating layer 58 made of silicon oxide, see para [0118], para [0071], para [0130] of the disclosure).
Regarding claim 2, OKADA teaches the semiconductor storage device of claim 1 and further teaches, wherein the plurality of first connection pads (PI1) are on a first chip (C1) side of the boundary region, a plurality of second connection pads (PI2, para [0066]) are further included in the boundary region on a second chip side (C2) of the boundary region, first surfaces (bottom surfaces) of the first connection pads (Pl1) are in direct contact with the second connection pads (Pl2), and the plurality of first contacts are in contact with second surfaces (top surfaces) of the first connection pads (Pl1) opposite of the first surfaces.
Regarding claim 3, OKADA teaches the semiconductor storage device of claim 1 and further teaches , wherein the plurality of first connection pads (reinterpreting Pl2 as “a plurality of first connection pads” as marked below) are on a second chip (C2) side of the boundary region, a plurality of second connection pads (Pl1, para [0066])) are further included in the boundary region on a first chip (C1) side of the boundary region, first surfaces (top surfaces) of the first connection pads (Pl2) are in direct contact with the second connection pads (Pl1), and the plurality of first contacts (redefining ‘a plurality of first contacts” as marked below, the plurality of first contacts are in contact with second surfaces (bottom surfaces) of the first connection pads (Pl2) opposite of the first surfaces.
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Regarding claim 4, OKADA teaches the semiconductor storage device of claim 1 and further teaches ,wherein the first insulating member (501, FIG. 1) has a portion overlapping with the memory cell array (MCA) along the first direction(direction Z).
Regarding claim 5, OKADA teaches the semiconductor storage device of claim 1 and further teaches ,wherein the first insulating member is silicon nitride (considering silicon nitride portion of the stack 501 as first insulating member, the first insulating member is silicon nitride) formed by physical vapor deposition (the limitation "formed by physical vapor deposition." is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966 ) to have a compressive stress greater than a compressive stress of the first insulator layer (silicon nitride has a greater compressive stress than that of silicon oxide).
Regarding claim 6, OKADA teaches the semiconductor storage device of claim 1 and further teaches , wherein the first insulating member is silicon nitride (considering silicon nitride portion of the stack 501 as first insulating member, the first insulating member is silicon nitride) formed by chemical vapor deposition(the limitation "formed by chemical vapor deposition." is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966) to have a tensile stress
Regarding claim 7, OKADA teaches the semiconductor storage device of claim 1 and further teaches, wherein the first insulator layer comprises silicon oxide (220 is made of silicon oxide, para [0087]), and the first insulating member comprises silicon nitride (501 is made of silicon nitride as per claim 8 rejection above).
Regarding claim 16, OKADA teaches,
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A semiconductor storage device(FIG. 24 as annotated above), comprising:
a first chip(C1, para [0066]) including a substrate(including 300, 301 & 302, para [0096];
and a second chip (C2, para [0066]) contacting the first chip, the second chip including a memory cell array (MCA, para [0078]) including a plurality of first wiring layers(conductive layers 110, para [0080]) spaced apart from each other in a first direction (Z) and a memory pillar that penetrates the plurality of first wiring layers in the first direction,
wherein the device includes: a plurality of first connection pads (bonding electrodes Pl1, para [0066] as marked) in a boundary region between the first chip and the second chip in the first direction (Z);
a plurality of first contacts (as marked) in contact with the plurality of first connection pads, each extending in the first direction (Z);
a first insulator layer (220, para [0087]) surrounding the plurality of first contacts in a first plane parallel to the substrate (as seen);
and a plurality of first insulating members (501 and 101 ,para [0139])) adjacent to the first insulator layer in the first plane,
the first insulator layer (220) separating the plurality of first insulating members from the plurality of first contacts,
the first insulating members (501) each extending lengthwise in a second direction (Y) parallel to the substrate in the first plane,
and the first insulating members having a stress value different from a stress value of the first insulator layer (501 may be formed of stacked layer of silicon oxide and silicon nitride, para [0140], and 220 may be formed of silicon oxide, para, [0087]. Silicon nitride has a different stress value than silicon oxide similar to the disclosure where insulating member (BE) made of silicon nitride has different stress value than insulating layer 58 made of silicon oxide, see para [0118], para [0071], para [0130] of the disclosure).
Regarding claim 17, OKADA teaches the semiconductor storage device of claim 16 and further teaches ,wherein the plurality of first insulating members have a portion (501) overlapping with the memory cell array (MCA) along the first direction (Z).
Regarding claim 18, OKADA teaches the semiconductor storage device of claim 16 and further teaches, wherein the first insulating members have a compressive stress greater than a compressive stress of the first insulator layer(as per claim 16 rejection above).
Regarding claim 19, OKADA teaches the semiconductor storage device of claim 16 and further teaches ,wherein the first members are silicon nitride formed by physical vapor deposition to have a tensile stress (the limitation "formed by physical vapor deposition….." is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966 ).
Regarding claim 20, OKADA teaches the semiconductor storage device of claim 16 and further teaches ,wherein the first insulator layer comprises silicon oxide (220 is made of silicon oxide, para [0087]) and the first insulating members comprise silicon nitride (501 is made of silicon nitride as per claim 16 rejection above).
Allowable Subject Matter
Claims 8-15 are allowed.
With respect to claim 8, the prior art made of record does not teach or suggest either alone or in combination “…the first insulating members extending lengthwise in a second direction parallel to the substrate spaced apart from each other in a third direction perpendicular to the first and second directions” in further combination with the additionally claimed limitations, as they are claimed by the Applicant.
Regarding claim 8, OKADA teaches,
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A semiconductor storage device (FIG. 24 as annotated above) , comprising:
a first chip (C1, para [0066]) including a substrate(including 300, 301 & 302, para [0096]);
and a second chip (C2, para [0066]) contacting the first chip, the second chip including a memory cell array (MCA, para [0078]) including a plurality of first wiring layers (conductive layers 110, para [0080]) spaced apart from each other in a first direction (direction Z).
and a plurality of memory pillars (including semiconductor layer 120 and gate insulating film & a charge storage film formed between 120 and 110, see para [0080]) that penetrate the plurality of first wiring layers in the first direction, wherein the device includes:
a plurality of first contacts (as marked) that extend in the first direction to electrically connect the first chip and the second chip (via Pl1 & Pl2);
a first insulator layer (220, para [0087]) surrounding the plurality of first contacts in a first plane parallel to the substrate (as seen);
and a plurality of first insulating members (including 501, 101, para [0139], [0074]) adjacent to the first insulator layer (220) in the first plane,
the first insulator layer (220) separating the plurality of first insulating members from the plurality of first contacts(as seen),
…….and the first insulating members having a stress value different from a stress value of the first insulator layer (501 may be formed of stacked layer of silicon oxide and silicon nitride, para [0140], and 220 may be formed of silicon oxide, para, [0087]. Silicon nitride has a different stress value than silicon oxide similar to the disclosure where insulating member (BE) made of silicon nitride has different stress value than insulating layer 58 made of silicon oxide, see para [0118], para [0071], para [0130] of the disclosure).
But OKADA fails to teach,
the first insulating members extending lengthwise in a second direction parallel to the substrate spaced apart from each other in a third direction perpendicular to the first and second directions
The other cited arts, either alone or in combination, fails to cure deficiencies of OKADA.
Claim 9-15 are allowed being dependent on claim 8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. (FP 7.40)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Gauthier, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2813
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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