Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
In claim 1, lines 7 and 8, each recites “a gate” should read as --a first gate-- and --a second gate--, respectively.
In claim 1, lines 14 and 16 each recites “first bias voltage applied to the gate”, it is not clear whether “the gate” is the same gate as the first and/or second transistor or the third and fourth transistors having different gates, respectively. Clarification is needed.
In claim 1, lines 9 and 10, each recites “a drain”, should read as --a first drain-- and --a second drain--, respectively.
In claim 1, line 14, “a first bias voltage” should read as --the first bias voltage--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pham et al (US 20190305810 A1), hereafter referred to as “Pham”.
Regarding claims 1 and 10, in the embodiment of Figures 6 and 8, Pham discloses:
An equalizer circuit (Figs. 6 and 8, continuous time linear/adaptive equalizer), being integrally mounted on one semiconductor substrate (paragraph [0002], lines 6-13, equalizer occupies a die or chip area, a die or chip is known in the art as a semiconductor substrate, as per claim 10), comprising:
a variable gain equalizer circuit (paragraph [0030], lines 9-13, control voltage VCTRL is used to adjust the peaking and low frequency gain); and
a first bias circuit (resistors 465 and 470 form the bias circuit) structured to generate a first bias voltage (voltages through 465 and 472 are used to bias transistors 610 and 615);
the variable gain equalizer circuit comprising:`
a first input terminal (Fig. 6, input voltage VIN+);
a second input terminal (Fig. 6, input voltage VIN-);
a first transistor (Fig. 6, transistor 600) having a gate (600 gate) coupled to the first input terminal (as shown in Fig. 6);
a second transistor (Fig. 6, transistor 605) having a gate (605 gate) coupled to the second input terminal (as shown in Fig. 6);
a first resistor coupled (resistor 425) to a drain of the first transistor (as shown in Fig. 6);
a second resistor (resistor 430) coupled to a drain of the second transistor (as shown in Fig. 6);
a first current source (current source 415);
a second current source (current source 420);
a third transistor (Fig. 6, transistor 610) coupled between a source of the first transistor (600 source) and the first current source (415), with a first bias voltage (bias voltage through resistor 465) applied to the gate (610 gate);
a fourth transistor (Fig. 6, transistor 615) coupled between a source of the second transistor (615 source) and the second current source (current source 420), with the first bias (bias voltage through resistor 470) voltage applied to the gate (615 gate);
a third resistor (resistor 475) coupled between a connection node of the third transistor and the first current source (node between 610 and 415, as shown in Fig. 6), and a connection node of the fourth transistor and the second current source (node between 615 and 420, as shown in Fig. 6); and
a capacitor (capacitor 480) coupled in parallel to the third resistor (as shown in Fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Pham et al (US 20190305810 A1) in view of Su et al (US 8335249 B1), hereafter referred to as “Pham” and “Su”, respectively.
Regarding claims 2, 5, and 7, Pham is silent in teaching the resistance of the third resistor is variable, as per claim 2, a plurality of the variable gain equalizer circuits is coupled in series, as per claim 5, and the capacitance of the capacitor is variable, as per claim 7.
Su teaches, in the embodiment of Figures 1 and 2,
the resistance of the third resistor and the capacitance of the capacitor is variable (FIG. 2, Variable resistor 50 and Variable capacitor 40). Furthermore, Su teaches a plurality of the variable gain equalizer circuits is coupled in series (EQ1, EQ2, and EQ3 (or 30a, 30b, and 30c), in series as shown in FIG. 1).
Accordingly, with respect to claims 2 and 7, it would have been obvious in view of the references, taken as a whole, to replace the generic resistor and capacitor in Pham with any art recognized variable resistor and capacitor, such as the resistor and capacitor taught by Su (FIG. 2), especially since the equivalent resistor and capacitor in Su would have performed the equivalent function as the generic resistor and capacitor in Pham, thereby suggesting the obviousness of such a combination. Moreover, with respect to claim 5, it would have been further obvious in view of the references, taken as a whole, to have modified the equalizer as taught in Pham to include a plurality of gain equalizer circuits coupled in series as taught in Su (FIG. 1, equalizer block 14), to provide 9-dB gain at half data rate frequency, and up to 15-dB gain by appropriately tuning the variable resistor and capacitor (i.e. Rz and Cz) (Su, column 4 lines 12-15), thereby suggesting the obviousness of such a modification.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Pham et al Su et al in view of Cao (US 7598811 B2), hereafter referred to as “Pham and Su” and “Cao”, respectively.
Pham and Su discloses the third resistor (Su, Fig. 6, 475), however, Su and Pham does not disclose third resistor is constituted by a combination of a plurality of resistors and a plurality of switches, making the resistance of the third resistor digitally controllable.
Cao teaches, in the embodiment of Figure 7 and 9A:
the third resistor is constituted by a combination of a plurality of resistors (Fig. 9A) and a plurality of switches (column 10, lines 27-29, resistors are connected to MOS switches), making the resistance of the third resistor digitally controllable (column 10, lines 30-32, the switches are connected to digital control signals).
Accordingly, with respect to claim 3, it would have been obvious in view of the references, taken as a whole, to replace the generic resistor as taught by Pham and Su with the switchable resistors as taught by Cao (Fig. 9A), to provide for great ability of selection for a wide variety of application with different equalization needs, which in turn is connected to digital control signals to select different RC value so that the frequency response of the circuit can be readily programmed (column 10 lines 21-32), thereby suggesting the obviousness of such a combination.
Allowable Subject Matter
Claims 4, 6, 8, and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4 and 6:
The cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “the equalizer circuit further comprises a second bias circuit structured to supply a second bias voltage to a gate of the fifth transistor” per claim 4, and “the equalizer circuit further comprises a second bias circuit structured to supply a second bias voltage commonly to a gate of each field effect transistor that constitutes the third resistor in each of the variable gain equalizer circuits” per claim 6.
Regarding claims 8 and 9:
The cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, the first and second bias circuit comprising “at least one current D/A converter structured to convert a digital input into a gradated current output; and an I/V conversion circuit structured to convert an output current from the at least one current D/A converter to the first bias voltage.”
Conclusion
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/MALANE LIENG/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843