Prosecution Insights
Last updated: July 17, 2026
Application No. 18/361,302

Radio-frequency Mixer with Shared Bias Current

Non-Final OA §103
Filed
Jul 28, 2023
Examiner
YUN, EUGENE
Art Unit
2648
Tech Center
2600 — Communications
Assignee
Apple Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
854 granted / 1002 resolved
+23.2% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
1036
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
62.5%
+22.5% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
1.6%
-38.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1002 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 8, 13-17, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiramizu (US 2009/0221259) in view of Belson (US 4,254,459). Referring to Claim 1, Shiramizu teaches mixer circuitry comprising: a transformer having a first winding and a second winding (see device in fig. 11 which shows first and second windings in box 42); a first input transistor coupled to a first terminal of the first winding and configured to receive an input signal (see Q40 with RFIN+ input connected to first winding in 42 in fig. 11); a second input transistor coupled to a second terminal of the first winding and configured to receive the input signal (see Q41 with RFIN- input connected to first winding in 42 in fig. 11); a first pair of mixer transistors coupled to a first terminal of the second winding and configured to receive an oscillating signal (see pair Q42 and Q43 with LO input connected to second winding in 42 in fig. 11); a second pair of mixer transistors coupled to a second terminal of the second winding and configured to receive the oscillating signal (see pair Q44 and Q45 with LO input connected to second winding in 42 in fig. 11); and the first and second windings having center taps (see center taps of both windings in box 42 in fig. 11). Shiramizu does not teach a conductive path that couples a center tap contact of the first winding to a center tap contact of the second winding. Belson teaches a conductive path that couples a center tap contact of the first winding to a center tap contact of the second winding (see windings 40 and 42 in fig. 1 both with center taps shown with nodes 46 which are connected together through a conductive path). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Belson to the device of Shiramizu in order to better operate at the required voltage levels. Referring to Claim 8, Shiramizu also teaches wherein the first pair of mixer transistors have first source-drain terminals coupled to the first terminal of the second winding (see drains of Q42 and Q43 connected to second winding in 42 in fig. 11), the first pair of mixer transistors have first gate terminals configured to receive the oscillating signal (see gates of Q42 and Q43 connected to LO inputs in fig. 11), the second pair of mixer transistors have second source-drain terminals coupled to the second terminal of the second winding (see drains of Q44 and Q45 connected to second winding in 42 in fig. 11), and the second pair of mixer transistors have second gate terminals configured to receive the oscillating signal (see gates of Q44 and Q45 connected to LO inputs in fig. 11). Referring to Claim 13, Shiramizu also teaches wherein the first pair of mixer transistors and the second pair of mixer transistors are configured to generate an output signal based on the oscillating signal and the input signal (see OUT+ and OUT- as outputs of mixer transistors Q42-Q45 in fig. 11), the output signal having a different frequency than the input signal (see paragraph 54 which shows different frequencies between the input and output signals), and the conductive path being configured to share a DC bias current between the first pair of mixer transistors, the second pair of mixer transistors, the first input transistor, and the second input transistor (see paragraph 47 which shows shared bias current). Referring to Claim 14, Shiramizu teaches mixer circuitry comprising: a transconductor 1 (fig. 1); mixer transistors Q42-Q45 (fig. 11); a transformer that couples an output of the transconductor to an input of the mixer transistors (see fig. 11 which shows LO input to transistors Q42-Q45), wherein the transformer includes a first coil having a first center tap contact, and a second coil magnetically coupled to the first coil (see 42 of fig. 11 which shows first and second coils magnetically coupled). Shiramizu does not teach the second coil having a second center tap contact that is coupled to the first center tap contact over a conductive path. Belson teaches the second coil having a second center tap contact that is coupled to the first center tap contact over a conductive path (see windings 40 and 42 in fig. 1 both with center taps shown with nodes 46 which are connected together through a conductive path). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Belson to the device of Shiramizu in order to better operate at the required voltage levels. Referring to Claim 15, Shiramizu also teaches the mixer transistors having first source-drain terminals coupled to first and second terminals of the second coil and have gate terminals configured to receive an oscillating signal (see Q42-Q45 in fig. 11 with drain terminals coupled to second coil in box 42 and gates with LO inputs). Referring to Claim 16, Shiramizu also teaches transistors with second source-drain terminals coupled to first and second terminals of the first coil (see Q40 and Q41 in fig. 11 with source terminals coupled to first coil in box 42). Referring to Claim 17, Shiramizu also teaches the transistors in the transconductor have third source-drain terminals coupled to a ground line (see drain terminals of Q40 and Q41 coupled to ground in fig. 11). Referring to Claim 21, Shiramizu teaches mixer circuitry comprising: a first pair of transistors having first gate terminals configured to receive an input signal and having first source-drain terminals (see transistors Q40 and Q41 in fig. 11 with RFIN inputs), a second pair of transistors having second gate terminals configured to receive a local oscillator (LO) signal and having second source-drain terminals (see transistors Q42 and Q43 in fig. 11 with LOIN inputs), a third pair of transistors having third gate terminals configured to receive the LO signal and having third source-drain terminals (see transistors Q44 and Q45 in fig. 11 with LOIN inputs), and a transformer having a first inductor and a second inductor, wherein the first inductor is coupled between the first source-drain terminals, the second inductor is coupled between the second source-drain terminals and the third source-drain terminals (see fig. 11 where the box 42 shows the first inductor coupled between the source terminals of Q40 and Q41 and the second inductor coupled between the drain terminals of Q42-Q45), and the first and second windings having center taps (see center taps of both windings in box 42 in fig. 11). Shiramizu does not teach a center tap of the first inductor is coupled to a center tap of the second inductor over a conductive path. Belson teaches a center tap of the first inductor is coupled to a center tap of the second inductor over a conductive path (see windings 40 and 42 in fig. 1 both with center taps shown with nodes 46 which are connected together through a conductive path). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Belson to the device of Shiramizu in order to better operate at the required voltage levels. Claim(s) 2-7, 12, 18, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiramizu and Belson and further in view of Kaila (US 11,316,476). Referring to Claim 2, Shiramizu teaches the first pair of mixer transistors being coupled between the output transformer and the first terminal of the second winding (see Q42 and Q43 between OUT- and the second coil in 42 in fig. 11), and the second pair of mixer transistors being coupled between the output transformer and the second terminal of the second winding (see Q44 and Q45 between OUT+ and the second coil in 42 in fig. 11). The combination of Shiramizu and Belson does not teach the output transformer having a third winding and a fourth winding and a positive power supply line coupled to a center tap contact of the third winding. Kaila teaches the output transformer having a third winding 134 (fig. 1A) and a fourth winding 136 (fig. 1A) and a positive power supply line coupled to a center tap contact of the third winding (see VDD in the center of winding 134 in fig. 1A). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Kaila to the modified device of Shiramizu and Belson in order to reduce unwanted interference and emission. Referring to Claim 3, Shiramizu also teaches the first input transistor Q40 (fig. 11) having a first source-drain terminal coupled to the first terminal of the first winding (see source of Q40 coupled to first coil in 42 in fig. 11), a second source-drain terminal coupled to a ground line (see drain of Q40 coupled to ground in fig. 11), and a first gate terminal configured to receive the input signal (see RFIN+ coupled to gate of Q40 in fig. 11). Referring to Claim 4, Shiramizu also teaches the second input transistor having a third source-drain terminal coupled to the second terminal of the first winding (see source of Q41 coupled to first coil in 42 in fig. 11), a fourth source-drain terminal coupled to the ground line (see drain of Q41 coupled to ground in fig. 11), and a second gate terminal configured to receive the input signal (see RFIN- coupled to gate of Q41 in fig. 11). Referring to Claim 5, Belson also teaches the positive power supply line and the ground line configured to produce a DC bias current that flows across the conductive path between the center tap contact of the first winding and the center tap contact of the second winding (see col. 9, line 32-col. 10, line 60 which shows the process of biasing current flowing through the conductive paths including the path between the center taps). Referring to Claim 6, Kaila also teaches a first impedance termination disposed on the conductive path (see impedance termination 604 in fig. 6 on conducting path connected to power). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Kaila to the modified device of Shiramizu and Belson in order to reduce unwanted interference and emission. Referring to Claim 7, Kaila also teaches a second impedance termination that couples the conductive path to a ground line (see impedance termination 139 in fig. 1B on conducting path connected to ground). Referring to Claim 12, Kaila also teaches an additional conductive path that couples a node on the conductive path to a ground line (see fig. 1B which shows conductive path with 139 leading to ground). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Kaila to the modified device of Shiramizu and Belson in order to reduce unwanted interference and emission. Referring to Claim 18, Shiramizu teaches the mixer transistors having fourth source-drain terminals (see sources of Q42-Q45 in fig. 11). The combination of Shiramizu and Belson does not teach a third coil, wherein the fourth source-drain terminals are coupled to first and second terminals of the third coil, the third coil having a third center tap contact coupled to a power supply line. Kaila teaches a third coil, wherein the fourth source-drain terminals are coupled to first and second terminals of the third coil, the third coil having a third center tap contact coupled to a power supply line (see fig. 1A which shows coil 134 coupled to source terminals and a voltage supply coupled to the center). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Kaila to the modified device of Shiramizu and Belson in order to reduce unwanted interference and emission. Referring to Claim 22, Shiramizu teaches wherein the first pair of transistors have fourth source-drain terminals (see drain terminals of Q40 and Q41 in fig. 11), the second pair of transistors having fifth source-drain terminals, the third pair of transistors having sixth source-drain terminals (see source terminals of Q42-Q45 in fig. 11), the second pair of transistors being configured to generate an output signal at the fifth source-drain terminals based on the input signal, the third pair of transistors being configured to generate the output signal at the sixth source-drain terminals based on the input signal (see OUT+ and OUT- signals in fig. 11), the output signal being at a different frequency than the input signal (see paragraph 54 which shows different frequencies between the input and output signals), and the electronic device further comprising a ground power supply line coupled to the fourth source-drain terminals (see drain terminals of Q40 and Q41 in fig. 11 connected to ground). Shitamizu does not teach a third inductor coupled between the fifth source-drain terminals and the sixth source-drain terminals, and a positive power supply line coupled to a center tap of the third inductor. Kaila teaches a third inductor coupled between the fifth source-drain terminals and the sixth source-drain terminals, and a positive power supply line coupled to a center tap of the third inductor (see fig. 1A which shows coil 134 coupled to source terminals and a voltage supply coupled to the center). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Kaila to the modified device of Shiramizu and Belson in order to reduce unwanted interference and emission. Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiramizu and Belson and further in view of Krishnamurthi (US 2019/0267945). Referring to Claim 9, the combination of Shiramizu and Belson does not teach a first impedance termination coupled between the first source-drain terminals and the first terminal of the second winding; and a second impedance termination coupled between the second source-drain terminals and the second terminal of the second winding. Krishnamurthi teaches a first impedance termination coupled between the first source-drain terminals and the first terminal of the second winding; and a second impedance termination coupled between the second source-drain terminals and the second terminal of the second winding (see Zin1 and Zin2 in fig. 7 as the impedance terminations between the terminals and winding). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Krishnamurthi to the modified device of Shiramizu and Belson in order to reduce the noise level during operation of the device. Referring to Claim 10, Krishnamurthi also teaches a third impedance termination disposed on the conductive path (see Zin.total applied to connection node 210a which is described in paragraph 104 as the impedance termination). Referring to Claim 11, Krishnamurthi also teaches wherein the first impedance termination comprises a first differential mode impedance termination, the second impedance termination comprises a second differential mode impedance termination (see paragraph 54 which shows the differential impedance), and the third impedance termination comprises a common mode impedance termination (see paragraph 20 which shows common impedance). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE YUN whose telephone number is (571)272-7860. The examiner can normally be reached 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wesley Kim can be reached at 5712727867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EUGENE YUN/ Primary Examiner, Art Unit 2648
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Prosecution Timeline

Jul 28, 2023
Application Filed
Jun 02, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
90%
With Interview (+4.4%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1002 resolved cases by this examiner. Grant probability derived from career allowance rate.

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