DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 & 3 are rejected under 35 U.S.C. 103 as being unpatentable over SAWADA (2022/0149174 A1) in view of Chao et al. (US 8,927,401 B2)
Regarding claim 1, SAWADA teaches,
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A Schottky barrier diode (FIG. 14), comprising:
a semiconductor layer of a first conductivity type (n type 202, para [0055]) comprising a wide-bandgap semiconductor (202/102 may be SiC, para [0029]).
and a trench (204, para [0054]) defining a mesa portion (as marked, FIG. 14, FIG. 13) on a first surface (top surface of 202) thereof;
a high-resistance region (bottom region of 202P below the surface region 202b. See para [0077], impurity concentration distribution at highest value at surface 202b , therefore the bottom region should have relatively lower dopant concentration than that at the surface 202b and hence should offer high resistance compared to surface region 202b) under the trench of the semiconductor layer,
the high-resistance region comprising an impurity of a second conductivity type (P type, para [0077]) different from the first conductivity type;
an insulating film or a semiconductor film (208 which maybe polysilicon, para [0069])……., the insulating film or semiconductor film (208) covering at least a bottom surface among inner surfaces of the trench (as seen);
an anode electrode (209b, para [0070]) on the semiconductor layer through the insulating film or the semiconductor film (209b penetrates through the semiconductor film 208 at its dip portion as marked above), the anode electrode being connected to the mesa portion (connected via 209a);
and a cathode electrode (210, para [0070]) directly or through another layer (201), para [0071] on a second surface (bottom surface of 202) of the semiconductor layer (202) on the opposite side to the first surface (as seen),
But SAWADA does not explicitly teach,
the semiconductor film (polysilicon film 208) is of the second conductivity type.
Meanwhile, Chao teaches,
the semiconductor film (polysilicon structure 44, Fig. 20) in a trench may be doped with P-type or N-type (see Col. 4, lines 21-25, boron or phosphorous ions maybe uniformly implanted in a certain depth of the polysilicon structure 44, so as to form a P-type or an N-type area in the polysilicon structure 44).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to dope the polysilicon film 208 with P-type dopant (such that 208 is formed of P doped poly-silicon to form a conductive body, e.g. gate electrode such that the semiconductor film 208 is of second conductivity type), according to the teaching of Chao, in order to make polysilicon 208 conductive to connect to surface electrode 209b, as taught by SWADA (see para [0070]), since it has been held that choosing from a finite number of identified, predictable solutions such as P-type or N-type impurity to dope a polysilicon in a trench, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 3, SAWADA & Chao teach the Schottky Barrier Diode of claim 1 and further teaches, wherein the wide-bandgap semiconductor comprises a gallium oxide-based semiconductor (102/202 may be gallium oxide, SAWADA, para [0029]), and wherein the first conductivity type and the second conductivity type are n-type and p-type, respectively (as asserted in claim 1 rejection above).
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over SAWADA in view Chao et al. and further in view of MIYAMOTO et al. (US 2020/0161445 A1).
Regarding claim 4, SAWADA & Chao teach the Schottky Barrier Diode of claim 1 but do not explicitly teach, wherein the impurity of the second conductivity type comprises nitrogen.
But Miyamoto teaches,
…P-type impurity such as nitrogen….. (para [0052]
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use nitrogen as a p-type impurity, according to the teaching of Miyamoto, in order to form P-type region 202P, since it has been held that choosing from a finite number of identified, predictable solutions such as nitrogen as a p-type impurity, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Allowable Subject Matter
Claims 2, 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 2, 5-7 the prior art of record does not appear to teaches , suggest, or provide motivation for combination to following limitation:
wherein a relationship W×Nd < D×Na is satisfied, where W is a width of a depletion layer formed in the semiconductor layer from the bottom surface of the trench in a depth direction when a reverse voltage is applied, Nd is a donor concentration in the high-resistance region, D is a depth of the high-resistance region from the bottom surface of the trench, and Na is an acceptor concentration in the high-resistance region(claim 2)
wherein the trench defines an annular protrusion surrounding a periphery of the mesa portion, and wherein an annular guard ring of the second conductivity type is provided on the protrusion (claim 5)
wherein a plane orientation of a principal surface of the semiconductor layer is (001), wherein the mesa portion comprises a line-shaped planar pattern with a length direction along [010], and wherein a surface of a side portion of the mesa portion comprises the impurity of the second conductivity type(claim 6)
wherein the mesa portion does not comprise an intentionally doped impurity of the first conductivity type (claim 7)
Conclusion
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/K.A.R/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813