DETAILED ACTION
This Office action is in response to the amendment filed on 26 May 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Response to Arguments
Applicant's arguments filed 26 May 2026 have been fully considered but they are not persuasive.
Applicant argues, “Harshey does not disclose that the PWM control circuit (210) receives power from a first voltage node in a first phase and then receives power from a second voltage node in a second phase, whereby the first and second voltage nodes are not the same. There is no discussion in Harshey of phase-dependent power sourcing to the PWM control circuit as disclosed by the digital controller of claim 1.” Remarks, p. 9, second full paragraph.
The argument is understood as being two-pronged: one, that Harshey does not disclose the switching circuitry that configures the PWM control circuit 210 to power (directly) from the input voltage node and then to receive power from the supply voltage node; that is, two different nodes that are “not the same”, from which the PWM control circuit receives power. Second, that Harshey’s power-sourcing is not “phase-dependent,” which is understood to mean that the switching circuit couples the PWM control circuit to the input voltage node during a first phase, or in other words a first interval of time, and couples the PWM control circuit to the supply voltage node during a second phase or second interval of time.
Examiner respectfully disagrees with the above arguments.
Regarding the first prong, please see the annotated Fig. 2 of Harshey, below. The annotations are made to show correspondence between the figure and Applicant’s independent claim 1 (and correspondingly, claim 20). It can be seen from the annotations that the “input voltage node”, 206, and the “supply voltage node, output of 202, are not the same node.
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Fig. 2 of Harshey, annotated by the examiner to show correspondence to claim 1
Based on the annotations and paragraphs [0032]-[0036] of Harshey, it is respectfully asserted that Harshey discloses switching circuitry, including “switch” 200 (replacing first voltage regulator 200 per [0036]) and switch 212, is configured to couple the PWM control circuit 210 directly (that is, directly through switch 200) to the input voltage node during a first, start-up phase. That is, PWM circuit receives power via power supply domain, or node, 208, which is directly coupled through switch 200 to input voltage supply node 206, and thus PWM control circuit 210 is considered as directly coupled to input voltage node 206. See Harshey at [0034]. Therefore, during the first or start-up phase, PWM control circuit 210 is coupled directly to, and receives power directly from, the input voltage node 206.
Next, during a second, or operation, phase, the switching circuitry of 200, 212 couples the PWM control circuit 210 to the supply voltage node, which is the output node of second voltage regulator 202. See Harshey at [0035]. Therefore, during the second or operation phase, the PWM control circuit is coupled to, and receives power from, the supply voltage node.
It is respectfully pointed out that this appears to be essentially the same configuration as Applicant points to in Fig. 3 of the application as providing the support for claim 1’s features (see Remarks, spanning pp. 7-8). That is, in Applicant’s disclosure, the PWM control circuit is coupled “directly” to the input voltage node NVIN through switch 316 (corresponding to Harshey’s “switch” 200) during the first phase, and is coupled to the supply voltage node Nsupply, output of LDO regulator 308 (corresponding to output of Harshey’s second regulator 202), through switch 318 (corresponding to Harshey’s switch 212) during the second phase.
Regarding the second prong, as explained above, Harshey discloses that the PWM control circuit is coupled directly to the input voltage node 206 to receive power therefrom during a first, start-up phase. Harshey at [0034]. Further, Harshey discloses that the PWM control circuit is coupled to the supply voltage node (output of 212) to receive power therefrom during a second, operational, phase. Harshey at [0035]. Therefore, it is respectfully submitted that Harshey discloses the same “phase-dependent” power-sourcing that is recited in independent claims 1 and 20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12, 14, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harshey et al. (US 2016/0380534; “Harshey”).
In re claims 1 and 20, Harshey discloses a digital controller and the corresponding control method for a switching converter (see Figs. 1-4) configured to receive an input voltage at an input voltage node (Figs. 1, 2: voltage received from power source 104, on node 106/206) and to generate an output voltage at an output voltage node (Figs. 1, 2: voltage to load 116/222, on node 114/220), the switching converter comprising one or more power switches (Figs. 1, 2: power switches within 112/218; Figs. 3, 4: shown in detail as the switches within 320) and an energy storage element (Figs. 1-4: inductor L1/L), the digital controller comprising:
a pulse width modulation control circuit (Figs. 1, 2: 102/210, 110/216, 214; shown in more detail in Figs. 3, 4: 316, 318) configured to receive the output voltage (see feedback from the output to detector 214/362 in Figs. 2 and 4) and to generate a PWM control signal to control the switching operation of the one or more power switches (Fig. 4: see PWM output of 316 and/or outputs from drivers 376 to the power switches in 320); and
switching circuitry (Figs. 1-3: 100/224/380, noting that at [0036] Harshey teaches that the first regulator 200/302 is replaced by a switch) configured to:
couple the pulse width modulation control circuit directly to the input voltage node during a first phase, such that the pulse width modulation control circuit receives power from the input voltage node during the first phase (drive controller 102/210/316 is coupled through the switch 200/302 directly to the input voltage from battery 104 during a startup phase: see [0034], [0045] and Fig. 5 during time period from t1-t3); and
ii) couple the pulse width modulation control circuit to a supply voltage node during a second phase, the supply voltage node being at a supply voltage, such that the pulse width modulation control circuit receives power from the supply voltage node during the second phase (drive controller 102/210/316 is coupled to receive a supply voltage at the output of second regulator/LDO 202/304 during a stabilized output phase following startup: see [0034], [0048]-[0049] and Fig. 5 after time t3).
In re claims 2-3, Harshey discloses wherein the switching converter is a buck converter (see Title, Abstract),
wherein the energy storage element is an inductor (Figs. 1-4: inductor L1/L).
In re claims 4-6, Harshey discloses wherein the pulse width modulation control circuit comprises an analog to digital converter coupled to the output voltage node and configured to digitize the output voltage to provide a digital representation of the output voltage (Fig. 4: detector blocks 362, 364 receive the output voltage feedback and output digital signals to the digital controller 316; see [0047]);
wherein the pulse width modulation control circuit comprises a digital loop circuit (for instance, the voltage and current control loops taught in [0047] as a whole may be considered digital loop circuits; or alternatively, the PI controller and LUT 368, understood as performing the function of a loop compensation circuit, may be considered as such); and
wherein the pulse width modulation control circuit comprises a digital PWM circuit (digital drive controller 316: see [0047]).
In re claims 7-9, Harshey discloses wherein the first phase precedes the second phase (as shown in Fig. 5);
wherein the first phase is a charging phase (Fig. 5: startup phase from t1-t3) and the second phase is a holding phase (stabilized output phase after time t3; see also [0009]-[0010]); and
wherein during the first phase, the supply voltage node is decoupled from the pulse width modulation control circuit (due to the switch 212/310 in Figs. 2-3 being open: see [0034] and [0048]-[0049]) and during the second phase the input voltage node is decoupled from the pulse width modulation control circuit (see [0049]: due at least to the difference in voltages produced by the switch 200/302 and regulator 202/304, the supply to digital controller 316 becomes cutoff from the power source 104 as no quiescent current is derived through the first regulator; see also [0031]: “the power supply controller may switch the supply to the second power supply domain 108 from the first power supply domain 106 to the buck converter output 114 once the voltage at the buck converter output 114 has reached a predetermined voltage level”).
In re claim 10, Harshey discloses wherein the switching circuitry comprises one or more first phase switches for coupling the pulse width modulation control circuit to the input voltage node during the first phase (in addition to the switch 200/302, Harshey also discloses at [0014] there may be a further switch coupled between the power source 104 and the digital controller) and one or more second phase switches for coupling the pulse width modulation control circuit to the supply voltage node during the second phase (Figs. 2, 3: switch 212/310; see [0034] and [0048]).
In re claim 11, Harshey discloses wherein during the first phase, the one or more second phase switches (Figs. 2, 3: 212/310) are open such that the supply voltage node is decoupled from the pulse width modulation control circuit (see Fig. 5, time during t1-t3; see [0034] and [0048]), and during the second phase, the one or more first phase switches (Figs. 2/3: 200/302; see [0036]) are open such that the input voltage node is decoupled from the pulse width modulation control circuit (see [0014]: “further switch may completely disconnect the second power supply domain from the first power supply domain once all the current can be supplied from the buck converter output”; that is, the input voltage from 104 is disconnected once the supply voltage at the buck converter output is powering the controller; see also [0036]).
In re claim 12, Harshey discloses wherein: the pulse width modulation control circuit comprises an analog to digital converter coupled to the output voltage node and configured to digitize the output voltage to provide a digital representation of the output voltage (Fig. 4: detector blocks 362, 364 receive the output voltage feedback and output digital signals to the digital controller 316; see [0047]); the one or more first phase switches comprises a first switch for coupling the analog to digital converter to the input voltage node during the first phase (Figs. 2-4: switch 200/302 ([0036]) and/or a further switch as taught in [0014] couple the input voltage from 104 to the digital controller which includes the A/D converter; see also Fig. 5 from t1-t3); and the one or more second phase switches comprises a second switch for coupling the analog to digital converter to the supply voltage node during the second phase (Figs. 2, 3: switch 212/310; see [0034] and [0048]).
In re claims 14, Harshey discloses wherein the pulse width modulation control circuit is configured to control the switching operation of the one or more switches during a first mode of operation (see Fig. 5 and [0034], [0045], [0048]-[0049]).
In re claims 17-19, Harshey discloses a voltage regulator or a power rail for providing the supply voltage at the supply voltage node (Figs. 1-3: 100/224/380 or 202/304); and
wherein the voltage regulator comprises a low dropout regulator (see [0011], [0037]) configured to receive the input voltage and to provide the supply voltage at the supply voltage node (Figs. 1-3: power circuit 100/224/380 comprises the LDO 202/304 and is connected to the input voltage from 104).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Harshey, as cited above, in view of Seiersen (US 2006/00044709; “Seiersen”).
In re claim 13, Harshey discloses the invention according to claim 12 as explained above, and further discloses a digital loop circuit (for instance, the voltage and current control loops taught in [0047] as a whole may be considered digital loop circuits; or alternatively, the PI controller and LUT 368, understood as performing the function of a loop compensation circuit, may be considered as such);
the one or more first phase switches coupling the digital loop circuit to the input voltage node during the first phase (Figs. 2-4: regulator 200/302 and/or a further switch as taught in [0014] couple the input voltage from 104 to the digital controller which includes the A/D converter; see also Fig. 5 from t1-t3); and
the one or more second phase switches coupling the digital loop circuit to the supply voltage node during the second phase (Figs. 2, 3: switch 212/310; see [0034] and [0048]).
Harshey does not disclose a third and fourth switch. However, it was known in the art to provide for multiple switches in parallel in certain instances, such as where an expected current draw through a circuit is above an absolute maximum rating for a single device that is to be used. This is demonstrated by Seiersen which shows a power controller switching circuit (Fig. 1) for connection between a power supply and a load (to be connected at terminals IN and OUT, respectively), which comprises several MOSFETs (1, 2… N) connected in parallel to share equally in the load current to increase the circuit capacity (Abstract, [0027]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the controller and switching converter of Harshey by incorporating third and fourth switches in addition to the first and second, in order to enable an increased circuit capacity while using smaller or less expensive switching devices (see Seiersen at [0026]-[0027]).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Harshey, as cited above, in view of Huang et al. (US 2011/0227549).
In re claims 15 and 16, Harshey discloses the invention according to claim 14 as explained above, but does not further disclose additional control circuitry comprising a pulse frequency modulation control circuit configured to control the switching operation of the one or more switches during a second mode of operation.
Whereas Huang discloses a buck converter (Figs. 1-2) wherein at light loads the controller includes circuitry for a PFM mode (222, 224 in Fig. 2), used for the purposes of maintaining high efficiency across a range of loads ([0013], [0014]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the controller and switching converter of Harshey by incorporating additional control circuitry comprising a pulse frequency modulation control circuit configured to control the switching operation of the one or more switches during a second mode of operation, such as a light load mode of operation, in order to maintain high efficiency across the range of loads as shown and taught by Huang.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
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