DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 7 are rejected under 35 U.S.C. 102 as being anticipated by Matsuyoshi et. al., (EP 122446,).
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Fig. 9 of Matsuyoshi reprinted for ease of reference.
Regarding claim 1, Li teaches A multiband power amplifier circuit comprising:
a first power transistor (111); a second power transistor (112);
a first matching circuit (115);
a second matching circuit (116);
a third matching circuit (107a-133-134); and
a combiner (107b and Balun 104), wherein the first power transistor (111) is coupled to a first input end of the combiner (top end of combiner) via the first matching circuit (115), wherein the second power transistor (112) is coupled to a second input end of the combiner (bottom end of the combiner) via the second matching circuit (116), wherein a first end of the third matching circuit (top end of 107a) is coupled to an output end of the first power transistor (111), a second end of the third matching circuit (bottom end of 107b) is coupled to an output end of the second power transistor (112), and wherein the third matching circuit (107b) is configured to directly connect the output end of the first power transistor (111) to the output end of the second power transistor (112).
wherein per claim 2, the third matching circuit is at least one of a microstrip (133, 134); and
wherein per claim 3, wherein the third matching circuit is a capacitor (107a).
wherein per claims 4 and 7, the third matching circuit is located outside packages of the first power transistor and the second power transistor because the power amplifier assembly is fabricated by mounting different components on a board or substrate with separate transistors and matching elements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-14 and 17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Matsuyoshi.
Regarding claims 9 and 17, Anderson teaches (Figs. 1-12 and Fig. 37 and Fig. 49) a multi-antenna (for different frequency transmission and reception as in Fig. 37 and for different modes of operation such as cellular, Bluetooth, GPS and WiFi) radio frequency transceiver (TRX) TX/RX as shown in Fig. 4) comprising:
a phase-locked loop (col. 11, line 23); a local oscillator (In a baseband signal processor 62 in Fig. 49 as discussed in lines 25-27 of col. 33 Anderson teaches a PLL which is critical component that ensures the stability and accuracy of the local oscillator (LO) signals. The PLL works in conjunction with the local oscillator to lock the output frequency of LO to a reference frequency, which is essential for generating clean, tunable, and stable signals); a digital baseband (col. 1, line 67); and
a plurality of radio frequency circuits (see Fig. 1), each of the plurality of radio frequency circuits comprising a transmitter (28, 40 of Fig. 1) analog baseband (separate baseband processor for each frequency band such as for 5 GHz and 2.4 GHz), a power amplifier (such as shown in Fig. 12A), an antenna (Antennas 1 and 2 in Fig. 37 and Antennas 92, 96, 100 and 104 of Fig. 49), and a frequency mixer (col. 40, line 53),
a radio frequency transceiver comprising: a multiband (two different bands namely 2.4 GHz (low) and 5 GHz (high), Fig. 1) power amplifier (PA, as exemplarily shown in Fig. 12A) circuit comprising a first power transistor (370), a second power transistor (396), a first matching circuit (382), a second matching circuit (388), a third matching circuit (384-386 because DC bias is provided through two chokes from the same DC source), and a combiner (288 as exemplarily shown in Fig. 11), wherein the first power transistor (370) is coupled to a first input end of the combiner via the first matching circuit (see Fig. 11, where the combiner is reached from the output of PA 292 (which is formed by the first (370) and second (396) transistors, Fig. 12A) via the matching circuit 294 while 294 has three segments namely 382, 388 and 384-386), wherein the second power transistor (396) is coupled to a second input end of the combiner via the second matching circuit (see Fig. 11, where the combiner is reached from the output of PA 292 (which is formed by the first (370) and second (396) transistors, Fig. 12A) via the matching circuit 294 while 294 has three segments namely 382, 388 and 384-386), wherein a first end (bottom end of 384) of the third matching circuit (384-386) is coupled to an output end (drain) of the first power transistor (370, Fig. 12A), a second end (bottom end of 386) of the third matching circuit (384-386) is coupled to an output end (drain) of the second power transistor (396), and wherein the third matching circuit (384-386) is configured to directly connect the output end of the first power transistor (370) to the output end of the second power transistor (396); and
an analog baseband (As illustrated in Fig. 2 the PA 132, which is detailed in Fig. 12A functions to amplify the TX signal output of the baseband circuit (see Fig. 2) for broadcast through the antenna, col. 9, lines 65-67), wherein the analog baseband is configured to output a multiband radio frequency signal (where the combining of multiple transmit signals is performed via signal processing in the baseband circuit, col. 10, lines 16-22) to the multiband power amplifier circuit (two different bands namely 2.4 GHz (low) and 5 GHz (high), Fig. 1), and the multiband power amplifier circuit is configured to amplify the multiband radio frequency signal.
Anderson (in Fig. 12A) is not explicit about the connection between the DC bias feeds for the first (370) and the second (396) transistors (although it is customary to use a single bias VDD voltage source for both transistors with isolation between the drains of the transistors (see Fig. 7 of Amano (US20050083133) and Fig. 2 of Wang (US20200259460), as teaching references).
Matsuyoshi teaches (as mentioned earlier in regards to claim 1) a third matching circuit (107a-133-134) with DC bias feed through l/4 microstrip transmission lines (in lieu of inductors, where it is a common knowledge that both transmission lines or inductors are used interchangeably for drain bias feeds in RF power amplifiers) and capacitor 107b used for isolation between the outputs of the first and second transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the current invention to combine the teaching of Matsuyoshi to the third matching circuit of Anderson such that the outputs of the first (370) and the second (396) transistors are isolated by a capacitor as part of the third match where a single DC bias source can be used for both drains taking advantage of the capacitive isolation. The obvious advantage would be to use a single drain supply for both transistors as well as providing suitable isolation between the transistors with an appropriate capacitive value based on frequency of operations. Thus, the modified third matching of Anderson in view of Matsuyoshi teaching all limitations of claim 9. Wherein per claims 10 and 19, the third matching circuit comprises inductors (see Fig. 12A of Anderson) and per claims 11 and 20, the third matching circuit is a capacitor (107b similar to the one shown in Fig. 9 of Matsuyoshi and per claims 12 and 13, the third matching circuit is located inside a package of the amplifier (in the form of an RF integrated circuit, i.e., in the package comprising the first and the second power transistors). Also, per claim 14, considering each of the four transistor dies (Fig. 12A) as separate packages, the third matching circuit i.e. integrated capacitor (similar 107b of Fig. 9 of Matsuyoshi implemented in the amplifier circuit of Fig. 12A of Anderson), and spiral inductors should be considered as outside of the packages of the first and/or the second power transistors.
Claims 6 and 8 are rejected under 35 USC 103 as being unpatentable over Matsuyoshi in view of Zhu et al. (US20170117856).
Regarding claim 6 and 8, Matsuyoshi teaches all limitations of claim 1, Matsuyoshi however, is not explicit that the third matching is inside the first and second transistor package.
Zhu in a similar field of interest of high power RF multi transistor package of amplifier teaches that the third matching circuit (642 in Figs. 6 and 7) is located inside packages (600) of the first power transistor and the second power transistor (in case of Zhu first (630), second(630) and third (630) transistor dies inside the package).
It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to adapt the compact packaging concept of Zhu for the multi transistor RF amplifier module of Matsuyoshi for compacting the size of the amplifier. Such a modification represents nothing more than the predictable use of prior art elements according to their established functions in the context of compact, modern RF amplifier designs.
Claims 15 and 16 are rejected under 35 USC 103 as being unpatentable over the combination of Anderson modified in view of Matsuyoshi and further in view of Zhu.
Regarding claims 15 and 16, Anderson modified in view of Matsuyoshi teaches all limitations of claim 9, Neither Matsuyoshi nor Anderson, is explicit about that the third matching the third matching circuit is located on an output pad of a die of the first and/or of the second power transistor.
Zhu in a similar field of interest of high-power RF multi transistor package of amplifier teaches that the third matching circuit (642 in Figs. 6 and 7) is located inside packages (600) on an output pad of a die of the first and/or of the second power transistor (in case of Zhu first (630), second (630) and third (630) transistor dies inside the package).
It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to adapt the compact packaging concept of Zhu for the multi transistor RF amplifier module of Matsuyoshi for compacting the size of the amplifier. Such a modification represents nothing more than the predictable use of prior art elements according to their established functions in the context of compact, modern RF amplifier designs.
Claim 18 is rejected under 35 U.S.C. § 103 as being unpatentable over Park et al. (U.S. Patent No. 7,542,731 B2) in view of Anderson, as further modified by Matsuyoshi, for the reasons set forth below and as previously discussed with respect to claim 17.
With reference to Park et al., Park discloses a radio frequency transceiver architecture in which a phase-locked loop (PLL 334) is employed to generate a local oscillator signal (332) that is supplied to frequency conversion circuitry for RF signal processing. As shown in Figure 1A of Park, the PLL 334 drives an oscillator 332, the output of which is selectively divided and phase-shifted (via elements 335, 336, and 0°/90° block 337) and provided to the down-conversion mixer 312 and the IQ demodulators 314 and 315, thereby supplying the requisite local oscillator signals for frequency translation.
In the transmit path, Park further teaches that digital baseband signals generated within the baseband modem 350 are converted to analog form by digital-to-analog converters (DACs 321 and 322). These analog baseband signals are then provided to IQ modulators 323 and 324, which combine the baseband signals with the local oscillator signal to produce an up-converted RF signal at the output of the up-converter 326. The up-converted RF signal is subsequently amplified by the transmit amplifier 327 and delivered through the RF front-end to the antenna 301, optionally via intervening filtering and duplexing elements (e.g., bandpass filter 302 and switch 303). Thus, Park clearly discloses a conventional transmit signal chain of PLL → local oscillator → mixer → power amplifier → antenna, wherein an analog baseband signal is introduced at the mixer stage, consistent with the limitations recited in claim 18.
However, Park does not explicitly describe a multiband, multi-antenna transceiver system employing multiple parallel transmit chains or power amplifiers configured for simultaneous operation across multiple frequency bands.
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Figure 1A transceiver system according to Park et al.
Anderson, as modified by Matsuyoshi, remedies this defi12ciency. As discussed in connection with claim 17, Anderson teaches a multiband RFIC architecture supporting multiple transmit paths and frequency bands (e.g., 2.4 GHz and 5 GHz bands as illustrated in Anderson’s Figures 1–12A and Figure 49), while Matsuyoshi teaches parallel power amplifier structures with multiple matching networks (see, e.g., Figure 9 of Matsuyoshi) to improve efficiency and linearity in multiband RF transmission.
Although neither Anderson nor Matsuyoshi individually reproduces the precise transmit chain configuration of Park, it would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to adapt the well-understood transmit chain of Park for use in a multiband, multi-antenna system as taught by Anderson, and to incorporate the parallel amplifier and matching techniques of Matsuyoshi to ensure efficient power amplification across multiple frequency bands. Such a combination represents nothing more than the predictable use of prior art elements according to their established functions in the context of compact, modern MIMO transceiver designs.
Accordingly, the combination of Park et al., Anderson, and Matsuyoshi teaches or renders obvious each limitation of claim 18. The claimed subject matter therefore lacks an inventive step and is unpatentable under 35 U.S.C. § 103.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.