DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment dated 05/28/2026 has been entered. Claim 1 and 18 are amended. Claims 14-17 were previously withdrawn. No new claims are added. Claims 1-20 remain pending in applications.
Response to Arguments
Arguments dated 05/28/2026 has been acknowledged but are moot since a new ground of rejection is made over Singh et al. in view of new secondary reference Wong et al. (US 2022/0328661 A1) and none of the arguments applies to combination of Singh and Wong reference used in current rejection (see rejections below).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Both claims 1 & 18 recite, “wherein the source comprises a first fin and the drain comprises a second fin, and wherein the first fin and the second fin include a protruding region compared to the channel and positioned within the channel in a direction between the source and the drain”. The limitation “wherein the first fin and the second fin ………positioned within the channel in a direction between the source and the drain” is not clearly understood. It may be interpretated as “the first fin and the second fin are positioned between the source and drain” or “the channel is in a direction between the source and drain”. For the former interpretation, it is unclear how the first fin (206, FIG. 2B ) and the second fin (208) are between the source and the drain since the source comprises the first fin and the drain comprises the second fin. For examination purpose, examiner is considering the later interpretation.
Claims 2-13 are rejected being dependent on claim 1.
Claims 19-20 are rejected being dependent on claim 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10, 12-13, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over SINGH (US 2015/0035053 A1) in view of Wong et al. (US 2022/0328661 A1)
Regarding claim 1, SINGH teaches,
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A semiconductor device (Fig. 1) comprising:
a source(110, para [0020]), a drain(112, para [0020]);
a first gate(116, para [0020]);
a second gate (118, para [0020], para [0021]), the second gate being electrically coupled to the first gate(via 122/120, para [0021]),
the first gate and the second gate positioned between the drain and the source(Fig. 1);
a connector(120, para [0021]) directly positioned on the first gate and the second gate;
and a channel (including portion of 106 & 104 in current path from source and the drain, para [0020]) being electrically coupled to the first gate and the second gate;
but Singh does not explicitly teach,
wherein the source comprises a first fin and the drain comprises a second fin, and wherein the first fin and the second fin include a protruding region compared to the channel and positioned within the channel in a direction between the source and the drain.
Meanwhile, Wong taches,
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wherein the source (82 on left, Fig. 15B as annotated above) comprises a first fin (as marked, see para [0035], source/drain region 82 are formed in the fin 52), and wherein the drain (82 on right) comprises a second fin (as marked, see para [0035], source/drain 82 are formed in the fin 52), and wherein the first fin and the second fin include a protruding region (region of 82 raised above top surface of fin 52 marked as A-B , see para [0036]) compared to the channel (56) and positioned within the channel (as seen 82 are within channel 56) in a direction between the source and the drain (as seen above the channel 56 is in a direction between the source and the drain).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify SINGH such that the source 110 comprises a fin 110 and drain comprises a fin 112 and wherein the first fin 110 and the second fin 112 protrudes above the channel (106 & 104) and positioned within the channel in a direction between the source and the drain (as per interpretation from 112(b) rejection above), according to teaching of WONG, in order to exert stress in the respective channel regions (106, 104), thereby improving performance, as taught by Wong (see para [0035]).
Regarding claim 2, Singh & Wong teach the semiconductor device of claim 1 and further teaches, wherein a first distance of the first gate in a direction from the source to the drain is longer than a second distance of the second gate in the direction from the source to the drain(redefining the first gate as 118 and the second gate as 116, distance of the first gate 118 in a lateral direction from the source to the drain, is longer than that of the second gate 116)..
Regarding claim 3, Singh & Wong teach the semiconductor device of claim 1 and further teaches, wherein the channel is electrically coupled to the second gate by being in contact with the second gate (redefining the first gate as 118 and the second gate as 116, the channel portion 106 is electrically coupled and in contact with the second gate 116).
Regarding claim 4, Singh & Wong teach the semiconductor device of claim 1 and further teaches, wherein the channel comprises a first channel (channel portion 106 in contact with source 110) and a second channel (channel portion formed in region 104 in contact with the drain 112 establishing electrical path from source to drain), wherein the first channel is in contact with the first gate (106 in contact with 116), wherein the second channel is in contact with the second gate (second portion of the channel in region 104 is in electrical contact with 118 via 106, 116, 122 & 120).
But SINGH does not explicitly teach,
and wherein the semiconductor device further comprises a fin positioned between the first channel and the second channel.
BUT SINGH additionally teaches,
a fin positioned (implant 126. Fig. 5, para [0024], [0025]) between the first channel and the second channel.
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify SINGH such that the semiconductor device further comprises an implanted region 126 (fin) positioned between the first channel and the second channel, according to teaching of SINGH, in order to electrically connect the gate electrode to external circuit
Regarding claim 5, SINGH & Wong teach the semiconductor device of claim 4 and further teaches, wherein the first gate (116) is positioned on the first channel (portion of channel in region 106), and wherein the second gate (118) is positioned on the second channel (channel portion formed in region 104 in contact with the drain 112 establishing electrical path from source to drain).
Regarding claim 6, SINGH & Wong teach the semiconductor device of claim 4 and further teaches, wherein the fin is positioned between the first gate and the second gate (as per SINGH Fig. 5, 126 is between 116 & 118).
Regarding claim 7, SINGH & Wong teach the semiconductor device of claim 1 and further teaches, wherein the channel consists of a single channel in contact with both of the first gate and the second gate (channel portions 106 & 104 as a whole functioning as a single channel between source 110 and drain 112 and in electrical contact with both 116 and 118 via 120 & 122).
Regarding claim 8, SINGH & Wong teach the semiconductor device of claim 1 and further teaches, further comprising: a second channel (channel portion in region 104 under 108 and contacting drain 112 establishing electrical path between source and drain), the channel and the second channel being positioned in parallel relatively to each other in a direction between the source and the drain (portion of channel 106 under gate 116 is relatively positioned in parallel to the portion of second channel 104 passing under 108).
Regarding claim 10, SINGH & Wong teach the semiconductor device of claim 1 and further teaches, wherein the source comprises a first fin, and wherein the drain comprises a second fin (as per claim 1 rejection above, source /drain 110/112 comprises fin).
Regarding claim 12, SINGH &Wong teach the semiconductor device of claim 1 and further teaches, further comprising: a substrate (102, para [0020]); a first well (114 on left, para [0020]) positioned on the substrate (102); and a second well (114 on right) positioned on the substrate, wherein the source (110) is positioned on the first well , wherein the drain (112) is positioned on the second well, wherein the channel is positioned on the first well (as seen) , and wherein the first gate (116) is positioned over the first well (114 on left).
Regarding claim 13, SINGH & Wong teach the semiconductor device of claim 12 and further teaches, wherein the second gate (118) is in contact (in electrical contact via 122/120/116) with the channel (106), and wherein the second gate (118) is positioned over at least one of the first well or the second well (as seen from Fig. 1).
Regarding claim 18, SINGH teaches,
A semiconductor device (Fig. 1) comprising:
a source (110),
a drain (112);
a first gate (116);
a second gate (118),
the first gate and the second gate positioned between the drain and the source (as seen);
a connector (including 122 & 120, para [0021]) directly positioned on the first gate and the second gate to physically connect the first gate to the second gate;
and a channel (106, para [0020]) being electrically coupled to the first gate and the second gate (the channel 106 is electrically coupled to both 116 and 118 since 116/118 are electrically coupled via 122/120),
the channel (106) being in contact (in electrical contact via 122/120) with the second gate (118).
But does not explicitly teach,
wherein the source comprises a first fin and the drain comprises a second fin, and
wherein the first fin and the second fin include a protruding region compared to the channel and positioned within the channel in a direction between the source and the drain.
Meanwhile, Wong taches,
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wherein the source (82 on left, Fig. 15B as annotated above) comprises a first fin (as marked, see para [0035], source/drain region 82 are formed in the fin 52), and wherein the drain (82 on right) comprises a second fin (as marked, see para [0035], source/drain 82 are formed in the fin 52), and wherein the first fin and the second fin include a protruding region (region of 82 raised above top surface of fin 52 marked as A-B , see para [0036]) compared to the channel (56) and positioned within the channel (as seen 82 are within channel 56) in a direction between the source and the drain (as seen above the channel 56 is in a direction between the source and the drain).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify SINGH such that the source 110 comprises a fin 110 and drain comprises a fin 112 and wherein the first fin 110 and the second fin 112 protrudes above the channel (106 & 104) and positioned within the channel in a direction between the source and the drain (as per interpretation from 112(b) rejection above), according to teaching of WONG, in order to exert stress in the respective channel regions (106, 104), thereby improving performance, as taught by Wong (see para [0035]).
Regarding claim 19, SINGH & Wong teach the semiconductor device of claim 18 and further teaches, wherein the channel comprises a first channel (channel portion 106 in contact with source 110) and a second channel(channel portion formed in region 104 in contact with the drain 112 establishing electrical path from source to drain), wherein the first channel is in contact with the first gate(106 in contact with 116), wherein the second channel is in contact with the second gate(second portion of the channel in region 104 is in electrical contact with 118 via 106, 116, 122 & 120),
But Singh & Wong does not explicitly teach,
and wherein the semiconductor device further comprises a fin positioned between the first channel and the second channel.
BUT SINGH additionally teaches,
a fin positioned (implant 126. Fig. 5, para [0024], [0025]) between the first channel and the second channel.
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify SINGH such that the semiconductor device further comprises an implanted region 126 (fin) positioned between the first channel and the second channel, according to teaching of SINGH, in order to electrically connect the gate electrode to external circuit
Regarding claim 20, SINGH & Wong teach the semiconductor device of claim 19 and further teaches ,wherein the fin is positioned between the first gate and the second gate(as per Fig. 5, 126 is between 116 & 118).
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over SINGH in view of Wong and further in view of Liaw (US 2022/0367659 A1)
Regarding claim 9, SINGH & Wong teach the semiconductor device of claim 1 but does not explicitly teach, wherein the channel comprises: silicon, silicon-germanium, or germanium.
But SINGH is silent about the material of the channel layer.
Meanwhile, Liaw teaches,
A channel layer may comprise germanium or silicon germanium (para [0031]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use SiGe as a material of the channel layer, according to the teaching of SINGH, in order to form the channel layer with a specific semiconductor material for electrical conduction from source to drain, since it has been held that choosing from a finite number of identified, predictable solutions such as SiGe or Ge as a material of channel layer, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).339
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over SINGH in view of Wong and further in view of Ciavatti (US 2019/0131406 A1)
Regarding claim 11, SINGH & Wong teach the semiconductor device of claim 10 and Wong further teaches, wherein the first fin and the second fin comprise an in-situ ……..doped epitaxy (the epitaxial source/drain regions 82 may be in-situ doped during growth, para [0038]).
But SINGH & WONG does not explicitly teach,
….. phosphorous or boron doped
Meanwhile, Ciavatti teaches,
Source and drain in fin 10, 11 epitaxially grown on well 18 (para [0022]) and well 18 may be doped with boron to provide P-type conductivity (para [0015]) s
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to make the in situ doped epitaxy as a in situ boron doped epitaxy , according to teaching of Ciavatti, in order to provide p-type conductivity to the source and drain, as taught by Ciavatti.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. (FP 7.40)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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