DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-13 and 18-20 without traverse in the reply filed on 02/02/2026 is acknowledged. Claims 14-17 are withdrawn by applicant. Claims 1-13, 18-20 remain pending in application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7-8, 12-13, 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SINGH (US 2015/0035053 A1)
Regarding claim 1, SINGH teaches,
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A semiconductor device (Fig. 1) comprising:
a source (110, para [0020]),
a drain (112, para [0020]);
a first gate (116, para [0020]);
a second gate (118, para [0020], para [0021]), the second gate being electrically coupled to the first gate (via 122/120, para [0021]),
the first gate and the second gate positioned between the drain and the source (Fig. 1);
a connector (120, para [0021]) directly positioned on the first gate and the second gate; and
a channel (channel portion 106, para [0020]) being electrically coupled to the first gate and the second gate (the channel portion 106 is electrically coupled to both 116 and 118 since 116/118 are electrically coupled via 122/120).
Regarding claim 2, SINGH teaches the semiconductor device of claim 1 and further teaches, wherein a first distance of the first gate in a direction from the source to the drain is longer than a second distance of the second gate in the direction from the source to the drain (redefining the first gate as 118 and the second gate as 116, distance of the first gate 118 in a lateral direction from the source to the drain, is longer than that of the second gate 116).
Regarding claim 3, SINGH teaches the semiconductor device of claim 1 and further teaches, wherein the channel is electrically coupled to the second gate by being in contact with the second gate (redefining the first gate as 118 and the second gate as 116, the channel portion 106 is electrically coupled and in contact with the second gate 116).
Regarding claim 7, SINGH teaches the semiconductor device of claim 1 and further teaches, wherein the channel consists of a single channel in contact with both of the first gate and the second gate (106 in electrical contact with both 116 and 118 via 120 & 122).
Regarding claim 8, SINGH teaches the semiconductor device of claim 1 and further teaches, further comprising: a second channel ( channel portion in region 104 under 108 and contacting drain 112 establishing electrical path between source and drain), the channel and the second channel being positioned in parallel relatively to each other in a direction between the source and the drain (portion of channel 106 under gate 116 is relatively positioned in parallel to the portion of second channel passing under 108 as defined).
Regarding claim 12, SINGH teaches the semiconductor device of claim 1 and further teaches, further comprising: a substrate (102, para [0020]); a first well (114 on left, para [0020]) positioned on the substrate (102); and a second well (114 on right) positioned on the substrate, wherein the source (110) is positioned on the first well , wherein the drain (112) is positioned on the second well, wherein the channel is positioned on the first well (as seen) , and wherein the first gate (116) is positioned over the first well (114 on left).
Regarding claim 13, SINGH teaches the semiconductor device of claim 12 and further teaches, wherein the second gate (118) is in contact (in electrical contact via 122/120/116) with the channel (106), and wherein the second gate (118) is positioned over at least one of the first well or the second well (as seen from Fig. 1).
Regarding claim 18, SINGH teaches,
A semiconductor device comprising:
a source (110),
a drain (112);
a first gate (116);
a second gate (118),
the first gate and the second gate positioned between the drain and the source (as seen);
a connector (including 122 & 120, para [0021]) directly positioned on the first gate and the second gate to physically connect the first gate to the second gate;
and a channel (106, para [0020]) being electrically coupled to the first gate and the second gate (the channel 106 is electrically coupled to both 116 and 118 since 116/118 are electrically coupled via 122/120),
the channel (106) being in contact (in electrical contact via 122/120) with the second gate (118).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over SINGH (US 2015/0035053 A1).
Regarding claim 4, SINGH teaches the semiconductor device of claim 1 and further teaches, wherein the channel comprises a first channel (channel portion 106 in contact with source 110) and a second channel (channel portion formed in region 104 in contact with the drain 112 establishing electrical path from source to drain along with 106), wherein the first channel is in contact with the first gate (106 in contact with 116), wherein the second channel is in contact with the second gate (second portion of the channel in region 104 is in electrical contact with 118 via 106, 116, 122 & 120).
But SINGH does not explicitly teach,
and wherein the semiconductor device further comprises a fin positioned between the first channel and the second channel.
BUT SINGH additionally teaches,
a fin positioned (implant 126. Fig. 5, para [0024], [0025]) between the first channel and the second channel.
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify SINGH such that the semiconductor device further comprises an implanted region 126 (fin) positioned between the first channel and the second channel, according to teaching of SINGH, in order to electrically connect the gate electrode to external circuit
Regarding claim 5, SINGH teaches the semiconductor device of claim 4 and further teaches, wherein the first gate (116) is positioned on the first channel (portion of channel in region 106), and wherein the second gate (118) is positioned on the second channel (channel portion formed in region 104 in contact with the drain 112 establishing electrical path from source to drain along with 106).
Regarding claim 6, SINGH teaches the semiconductor device of claim 4 and further teaches, wherein the fin is positioned between the first gate and the second gate (as per Fig. 5, 126 is between 116 & 118).
Regarding claim 19, SINGH teaches the semiconductor device of claim 18 and further teaches , wherein the channel comprises a first channel (channel portion in region 106 in contact with source 110) and a second channel (channel portion formed in region 104 in contact with the drain 112 establishing electrical path from source to drain along with 106), wherein the first channel is in contact with the first gate (106 in contact with 116), wherein the second channel is in contact with the second gate(second portion of the channel in region 104 is in electrical contact with 118 via 106,116,122 &120),
but SINGH does not explicitly teach,
and wherein the semiconductor device further comprises a fin positioned between the first channel and the second channel (Fig. 3).
BUT SINGH additionally teaches,
a fin positioned (126. Fig. 5, para [0025]) between the first channel and the second channel
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify SINGH such that the semiconductor device further comprises a fin (126) positioned between the first channel and the second channel, according to teaching of SINGH, in order to electrically connect the gate electrode to external circuit.
Regarding claim 20, SINGH teaches the semiconductor device of claim 19 and further teaches ,wherein the fin is positioned between the first gate and the second gate(as per Fig. 5, 126 is between 116 & 118).
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over SINGH and further in view of Liaw (US 2022/0367659 A1)
Regarding claim 9, SINGH teaches the semiconductor device of claim 1 but does not explicitly teach, wherein the channel comprises: silicon, silicon-germanium, or germanium.
But SINGH is silent about the material of the channel layer.
Meanwhile, Liaw teaches,
A channel layer may comprise germanium or silicon germanium (para [0031]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use SiGe as a material of the channel layer, according to the teaching of SINGH, in order to form the channel layer with a specific semiconductor material for electrical conduction from source to drain, since it has been held that choosing from a finite number of identified, predictable solutions such as SiGe or Ge as a material of channel layer, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over SINGH in view of Ciavatti et al. (US 2019/0131406 A1)
Regarding claim 10, SINGH teaches the semiconductor device of claim 1 but does not explicitly teach, wherein the source comprises a first fin, and wherein the drain comprises a second fin.
Meanwhile, Ciavatti teaches,
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wherein the source (34) comprises a first fin (10) , and wherein the drain comprises a second fin (11) (para [0021]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify SINGH such that the source 110 comprises a fin 10 and drain 112 comprises a fin 11, according to teaching of SINGH, in order to form improved fin-type-filed-effect transistor (FINFET) structure for LDMOS device to improve control over channel and reducing the leakage current, as taught by Ciavatti (para [0005], [0003]).
Regarding claim 11, SINGH & Ciavatti teach the semiconductor device of claim 10 and Ciavatti further teaches, wherein the first fin and the second fin comprise an in-situ phosphorous or boron doped epitaxy (18 maybe doped with boron , para [0015] and source and drain in fin 10, 11 epitaxially grown, para [0022]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Gauthier, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813