DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 07/28/2023 and 11/22/2024 are in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. They have been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claims 2, 6, 11, 13, 16, and 19 are objected to because of the following informalities:
Claim 2: Change to “…category of [[the]] that trace event; and…” (page 1/6).
Claim 6: Change to “…writing [[the]] that trace event to [[the]] that respective physical buffer according to [[the]] a respective pointer…” (page 2/6).
Claim 11: Change to “…a least recently used (LRU) [[,]] physical buffer…” (page 3/6).
Claim 13: Change to “…writing the trace event to the first physical buffer is according to [[the]] a respective pointer…” (page 4/6).
Claim 16: Change to “…is assigned to the respective category of [[the]] that trace event; and…” (page 5/6).
Claim 19: Change to “…writing [[the]] that trace event to [[the]] that respective physical buffer according to [[the]] a respective pointer…” (page 6/6).
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Claim 15: “…a trace assist unit to: receive…; write…; and unload…”
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 6, 8, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Cardinell et al. (U.S. Patent No. US 7,475,291 B2), hereinafter “Cardinell,” and further in view of McConnell et al. (U.S. Patent Application Publication No. US 2021/0303443 A1), hereinafter “McConnell.”
With regards to Claim 1, Cardinell teaches:
a trace assist unit (Fig. 2 and col. 3, lines 58-63; regarding, e.g., control chip 210 including trace data storage facility 215 which includes data buffers 220.) operable with a “processor,” (Fig. 2; col. 3, lines 45-49; Fig. 3; and col. 5, lines 40-43.) the trace assist unit comprising:
a plurality of physical buffers (Fig. 2; col. 3, lines 58-63; regarding, e.g., the data buffers 220; Fig. 3; and col. 5, lines 25-39.); and
loading circuitry (Fig. 2; col. 3, lines 58-63; and col. 4, lines 9-27; regarding, e.g., circuitry / hardware portions of the trace data storage facility 215 that control functions to write trace entries to destination buffers of the data buffers 220.) and unloading circuitry (Fig. 2; col. 3, lines 58-63; Fig. 3; and col. 6, lines 3-11; regarding, e.g., circuitry portions of the trace data storage facility 215 that control functions to execute a flush instruction to flush data from one or more full buffers of the data buffers 220 to memory 250.) that are communicatively coupled with the plurality of physical buffers (Fig. 2 and col. 3, lines 58-63.), the loading circuitry to:
receive trace events from “the processor,” (Fig. 3 and col. 5, lines 25-43.) each of the trace events having a respective category from a plurality of predefined categories (Fig. 3; col. 5, lines 25-43; Figs. 5A-5B; col. 4, lines 28-48; and col. 5, lines 4-12; regarding, e.g., port, general, and long term [predefined categories].);
write the trace events to respective ones of the plurality of physical buffers that are assigned to the respective categories of the plurality of predefined categories (col. 5, lines 4-12; Fig. 3; col. 5, lines 25-43; col. 5, lines 63-67; and col. 6, lines 1 and 2.); and
transmit, responsive to one or more predefined conditions, an unload signal to the unloading circuitry to unload contents of a selected physical buffer of the plurality of physical buffers to an external memory (Fig. 3 and col. 6, lines 3-11; regarding, e.g., the executed flush instruction [an unload signal].).
Cardinell does not explicitly teach:
operable with a plurality of processor cores;
receive trace events from various ones of the plurality of processor cores.
However, McConnell teaches:
operable with a plurality of processor cores (Fig. 10; ¶ 0127; Fig. 12; ¶ 0137-0140; Fig. 18; and ¶ 0270-0271.);
receive trace events from various ones of the plurality of processor cores (Fig. 18 and ¶ 0270-0271.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Cardinell with the generation of trace data from processor cores as taught by McConnell because a simple substitution of one known element (a processor – Cardinell: Fig. 2; Cardinell: col. 3, lines 45-49; Cardinell: Fig. 3; and Cardinell: col. 5, lines 40-43.) for another (processor cores) can be performed to obtain predictable results (providing known processing means for generating trace data).
With regards to Claim 5, Cardinell in view of McConnell teaches the TAU of Claim 1 as referenced above. Cardinell in view of McConnell further teaches:
wherein the one or more predefined conditions includes one or more of the following:
a physical buffer of the plurality of physical buffers is full (Cardinell: Fig. 3 and Cardinell: col. 6, lines 3-11.),
none of the plurality of physical buffers are unassigned, and
an error event has occurred (Cardinell: Fig. 3 and Cardinell: col. 6, lines 10-22.).
With regards to Claim 6, Cardinell in view of McConnell teaches the TAU of Claim 1 as referenced above. Cardinell in view of McConnell further teaches:
the loading circuitry further to:
maintain a plurality of pointers corresponding to the plurality of predefined categories (Cardinell: col. 4, lines 1-8; Cardinell: col. 4, lines 44-48; and Cardinell: col. 5, lines 13-16.),
wherein writing the trace events to respective ones of the plurality of physical buffers comprises, for each of the trace events:
writing the trace event to the respective physical buffer according to the respective pointer of the plurality of pointers that corresponds to the respective category (Cardinell: col. 4, lines 1-8; Cardinell: col. 4, lines 44-48; and Cardinell: col. 5, lines 13-16.); and
updating the respective pointer (Cardinell: col. 5, lines 13-16.).
With regards to Claim 8, Cardinell teaches:
a method of operating a hardware-based trace assist unit (TAU) (Fig. 2 and col. 3, lines 58-63; regarding, e.g., control chip 210 including trace data storage facility 215 which includes data buffers 220.), the method comprising:
receiving, using loading circuitry of the TAU (Fig. 2; col. 3, lines 58-63; and col. 4, lines 9-27; regarding, e.g., circuitry / hardware portions of the trace data storage facility 215 that control functions to write trace entries to destination buffers of the data buffers 220.), a trace event (Fig. 3 and col. 5, lines 25-43.) from “a processor,” (Fig. 2; col. 3, lines 45-49; Fig. 3; and col. 5, lines 40-43.) the trace event having a category from a plurality of predefined categories (Fig. 3; col. 5, lines 25-43; Figs. 5A-5B; col. 4, lines 28-48; and col. 5, lines 4-12; regarding, e.g., port, general, and long term [predefined categories].);
determining, using the loading circuitry, whether any of a plurality of physical buffers of the TAU are assigned to the category of the trace event (col. 5, lines 4-12.);
writing the trace event to a first physical buffer, of the plurality of physical buffers, that is assigned to the category (col. 5, lines 4-12; Fig. 3; col. 5, lines 25-43; col. 5, lines 63-67; and col. 6, lines 1 and 2.); and
transmitting, responsive to one or more predefined conditions, an unload signal (Fig. 3 and col. 6, lines 3-11; regarding, e.g., the executed flush instruction [an unload signal].) to unloading circuitry of the TAU (Fig. 2; col. 3, lines 58-63; Fig. 3; and col. 6, lines 3-11; regarding, e.g., circuitry portions of the trace data storage facility 215 that control functions to execute a flush instruction to flush data from one or more full buffers of the data buffers 220 to memory 250.) to unload contents of the first physical buffer to an external memory (Fig. 3 and col. 6, lines 3-11; regarding, e.g., the executed flush instruction [an unload signal].).
Cardinell does not explicitly teach:
receiving…a trace event from one of a plurality of processor cores.
However, McConnell teaches:
receiving…a trace event from one of a plurality of processor cores (Fig. 10; ¶ 0127; Fig. 12; ¶ 0137-0140; Fig. 18; and ¶ 0270-0271.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Cardinell with the generation of trace data from processor cores as taught by McConnell because a simple substitution of one known element (a processor – Cardinell: Fig. 2; Cardinell: col. 3, lines 45-49; Cardinell: Fig. 3; and Cardinell: col. 5, lines 40-43) for another (processor cores) can be performed to obtain predictable results (providing known processing means for generating trace data).
With regards to Claim 12, Cardinell in view of McConnell teaches the method of Claim 8 as referenced above. Cardinell in view of McConnell further teaches:
wherein the one or more predefined conditions includes one or more of the following:
a physical buffer of the plurality of physical buffers is full (Cardinell: Fig. 3 and Cardinell: col. 6, lines 3-11.),
none of the plurality of physical buffers are unassigned, and
an error event has occurred (Cardinell: Fig. 3 and Cardinell: col. 6, lines 10-22.).
With regards to Claim 13, Cardinell in view of McConnell teaches the method of Claim 8 as referenced above. Cardinell in view of McConnell further teaches:
maintaining a plurality of pointers corresponding to the plurality of predefined categories (Cardinell: col. 4, lines 1-8; Cardinell: col. 4, lines 44-48; and Cardinell: col. 5, lines 13-16.), wherein writing the trace event to the first physical buffer is according to the respective pointer of the plurality of pointers that corresponds to the category (Cardinell: col. 4, lines 1-8; Cardinell: col. 4, lines 44-48; and Cardinell: col. 5, lines 13-16.); and
updating the respective pointer (Cardinell: col. 5, lines 13-16.).
Claims 15, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cardinell, further in view of McConnell, and further in view of Chakra et al. (U.S. Patent No. US 10,802,947 B2), hereinafter “Chakra.”
With regards to Claim 15, Cardinell teaches:
a computing system comprising:
a “processor;” (Fig. 2; col. 3, lines 45-49; Fig. 3; and col. 5, lines 40-43.)
a “memory;” (Fig. 2 and col. 3, lines 45-49; regarding, e.g., memory 250.) and
a trace assist unit (Fig. 2 and col. 3, lines 58-63; regarding, e.g., control chip 210 including trace data storage facility 215 which includes data buffers 220.) to:
receive trace events from “the processor,” (Fig. 3 and col. 5, lines 25-43.) each of the trace events having a respective category from a plurality of predefined categories (Fig. 3; col. 5, lines 25-43; Figs. 5A-5B; col. 4, lines 28-48; and col. 5, lines 4-12; regarding, e.g., port, general, and long term [predefined categories].);
write the trace events to respective ones of a plurality of physical buffers of the trace assist unit (Fig. 2; col. 3, lines 58-63; regarding, e.g., the data buffers 220; Fig. 3; and col. 5, lines 25-39.), wherein the plurality of physical buffers are assigned to the respective categories of the plurality of predefined categories (col. 5, lines 4-12; Fig. 3; col. 5, lines 25-43; col. 5, lines 63-67; and col. 6, lines 1 and 2.); and
unload, responsive to one or more predefined conditions, contents of a selected physical buffer of the plurality of physical buffers to the “memory.” (Fig. 3 and col. 6, lines 3-11; regarding, e.g., executing a flush instruction to flush data from one or more full buffers of the data buffers 220 to the memory 250.)
Cardinell does not explicitly teach:
a plurality of processor cores;
receive trace events from various ones of the plurality of processor cores.
However, McConnell teaches:
a plurality of processor cores (Fig. 10; ¶ 0127; Fig. 12; ¶ 0137-0140; Fig. 18; and ¶ 0270-0271.);
receive trace events from various ones of the plurality of processor cores (Fig. 18 and ¶ 0270-0271.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Cardinell with the generation of trace data from processor cores as taught by McConnell because a simple substitution of one known element (a processor – Cardinell: Fig. 2; Cardinell: col. 3, lines 45-49; Cardinell: Fig. 3; and Cardinell: col. 5, lines 40-43) for another (processor cores) can be performed to obtain predictable results (providing known processing means for generating trace data).
Cardinell in view of McConnell does not explicitly teach:
a cache;
unload, responsive to one or more predefined conditions, contents of a selected physical buffer of the plurality of physical buffers to the cache.
However, Chakra teaches:
a cache (Fig. 4 and col. 5, lines 44-57.);
unload, responsive to one or more predefined conditions, contents of a selected physical buffer of the plurality of physical buffers to the cache (Fig. 4 and col. 5, lines 44-57.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Cardinell in view of McConnell with the saving of buffered data to a cache memory as taught by Chakra because a simple substitution of one known element (a memory – Cardinell: Fig. 2 and Cardinell: col. 3, lines 45-49) for another (a cache memory) can be performed to obtain predictable results (providing known storage means for storing trace data).
With regards to Claim 19, Cardinell in view of McConnell, further in view of Chakra, teaches the system of Claim 15 as referenced above. Cardinell in view of McConnell, further in view of Chakra, further teaches:
the trace assist unit further to:
maintain a plurality of pointers corresponding to the plurality of predefined categories (Cardinell: col. 4, lines 1-8; Cardinell: col. 4, lines 44-48; and Cardinell: col. 5, lines 13-16.),
wherein writing the trace events to respective ones of the plurality of physical buffers comprises, for each of the trace events:
writing the trace event to the respective physical buffer according to the respective pointer of the plurality of pointers that corresponds to the respective category (Cardinell: col. 4, lines 1-8; Cardinell: col. 4, lines 44-48; and Cardinell: col. 5, lines 13-16.); and
updating the respective pointer (Cardinell: col. 5, lines 13-16.).
With regards to Claim 20, Cardinell in view of McConnell, further in view of Chakra, teaches the system of Claim 15 as referenced above. Cardinell in view of McConnell, further in view of Chakra, further teaches:
a central processing complex comprising the plurality of processor cores, the cache, and the trace assist unit, the plurality of processor cores communicatively coupled with each other, and with the trace assist unit, by a communication fabric (McConnell: Fig. 10; McConnell: ¶ 0127; McConnell: Fig. 12; and McConnell: ¶ 0137-0140.); and
an input/output subsystem communicatively coupled with the central processing complex, the input/output subsystem comprising a plurality of input/output adapters to connect to an external network (McConnell: Fig. 10; McConnell: ¶ 0127; McConnell: Fig. 12; and McConnell: ¶ 0137-0140.).
Allowable Subject Matter
Claims 2-4, 7, 9-11, 14, and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Barnum et al. (U.S. Patent Application Publication No. US 2007/0220361 A1); teaching a way to offload trace data from a processor and store the trace data in external memory. By accumulating trace data in large buffers and sending them to a memory interface controller, the memory interface controller may write trace data to memory as the memory interface controller would execute a normal write to memory. In this manner, no additional I/O memory pins are required and processor memory storage for trace data is kept to a minimum. Furthermore, by using a special port to the memory interface controller the writing of trace data may be accomplished in a manner that does not affect the speed of the on-chip bus between the processor and the memory interface controller.
Cole et al. (U.S. Patent No. US 8,719,641 B2); teaching a method for priority buffering of trace data in a computing system including receiving instances of trace data by a priority assignment module, the trace data being generated by events that occur during execution of computer software in the computing system; assigning a priority to each instance of trace data, wherein the priority is assigned based on the event that generated the instance of trace data; and inserting the instances of trace data into a plurality of priority buffers based on their respective assigned priorities.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH KUDIRKA whose telephone number is (571)270-7126. The examiner can normally be reached M-F 7:30am - 5pm ET.
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/JOSEPH R KUDIRKA/Primary Patent Examiner, Art Unit 2114