Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0039], lines 3 and 6, the specification refers at each instance to “control circuit 140” in fig. 5; However, such label does not appear in fig. 5 and thus renders such a label vague in meaning.
In paragraph [0040], lines 5 and 7, and again in paragraph [0043], line 8, the specification refers at each instance to “external resistor 120” in fig. 5; However, such label does not appear in fig. 5 and thus renders such a label vague in meaning.
In paragraph [0040], lines 6 and line 7, the specification refers at each instance to “on-chip resistor 115” in fig. 5; However, such label does not appear in fig. 5 and thus renders such a label vague in meaning.
In paragraph [0043], line 11, the specification refers to “current source 150” in fig. 5; However, such label does not appear in fig. 5 and thus renders such a label vague in meaning.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 – 4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites that “the second amplifier comprises one or more inverters coupled in series”. That phrase is unclear because a series configuration requires at least two components. A single inverter (i.e. as characterized by “one” in the “one or more” limitation) cannot be properly characterized as being “coupled in series”. Therefore, the scope of the claim is ambiguous. Accordingly, clarification is needed.
Dependent claims 3 and 4 inherit the deficiencies of independent claim 2 and thus are also rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 12, 19, and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yen et al. (US Pat No. 7538605 B2).
Regarding Claim 1, Yen, fig. 3, discloses an apparatus comprising a multi-stage amplifier. Yen (fig. 3) discloses a first amplifier (input stage circuit 302) having a first input (first input end 3020), a second input (second input end 3022), and output (output end 3024) (column 4, lines 24 – 30). Yen further discloses a second amplifier (output stage circuit 304) having an input (3040) and an output (3044), wherein the input of the second amplifier is coupled to the output of the first amplifier. For example, the output 3024 of the first amplifier is coupled to the input end 3040 of output stage circuit 304, which includes transistor PMOS1 and resistors R1 and R2 and produces an output at 3044 (fig. 3; column 4, lines 36-41).
Yen also discloses a third amplifier (pseudo output stage circuit 306), having an input (3060) and an output (3062), wherein the input of the third amplifier is coupled to the output of the first amplifier. For example, the output 3024 of the first amplifier is coupled to input end 3060 of pseudo output stage circuit 306, which includes transistor PMOS2 and current source CS1, and produces an output at 3062 (fig. 3; column 4, lines 41-47). Yen further discloses a feedback switch (S14) coupled between the output of the third amplifier (306) and the second input of the first amplifier (3022). For example, switch circuit 308, including switch S14, selectively couples the output 3062 of the pseudo output stage circuit 306 to the second input 3022 of the input stage circuit 302 through feedback voltage output end 3062 (fig. 3; column 4, lines 41-47, and column 5, lines 55-65).
Accordingly, Yen discloses each element of claim 1 arranged as recited in the claim.
Regarding Claim 6, Yen, (fig. 3, column 4, lines 41 – 49), discloses the switches (S13, S14) of circuit 308 are closed, a feedback path is formed between the output (3062) of the third amplifier (306) and the second input (3022) of the first amplifier (302), thereby forming a closed loop as recited in the claim 6. Further, the second amplifier (output stage circuit 304) is not included in this feedback path and therefore lies outside the closed loop. Accordingly, Yen teaches the limitation of claim 6.
Regarding claim 12, (Yen, fig. 3; column 4, lines 24 – 47), discloses a method of operating a multi-stage amplifier, including a first amplifier (input stage circuit 302), a second amplifier (output stage circuit 304), and a third amplifier (pseudo output stage circuit 306)
Yen (fig. 3, column 4, line 50 – 67; column5, line 1), further discloses that the amplifier operates in offset storing mode and offset voltage cancellation mode, which correspond to different phases of operation. Yen, column 3, lines 39-40, describes the offset voltage storing mode as occurring “firstly”. However, Yen overall describes the storing mode and cancellation mode as distinct operational modes selectable by the switch circuit, rather than strictly sequential phases.
In the offset storing mode, Yen teaches coupling an output of the third amplifier to the second input of the first amplifier. In this configuration, the output 3062 of the third amplifier 306 is coupled to the second input 3022 of the first amplifier 302, as recited. Further, during this stage the output 3024 of the first amplifier 302 is provided to the input 3060 of the third stage 306, thereby driving an input of the third amplifier using an output of the first amplifier.
During the offset voltage cancellation mode, Yen discloses driving an input of the second amplifier using the output of the first amplifier. For example, the output end 3024 of first amplifier 302 provides the front-stage amplified signal (Vam_F) to input end 3040 of second amplifier 304, and produces an output at 3044 (Yen, fig. 3; column 4, lines 36 -41).
Accordingly, Yen teaches each step of the method recited in claim 12, and is therefore, anticipated by Yen.
Regarding claim 19, Yen (fig. 3, column 4, lines 30 - 31) discloses switch circuit 308, including switches S13 and S14, which selectively couple the output 3062 of pseudo output stage circuit 306 (third amplifier) to the second input 3022 of input stage circuit 302 (first amplifier). According to Yen, (column 4, lines 47 - 49), when switches S13 and S14 are closed, the output of the third amplifier is coupled to the second input of the first amplifier via the switch as recited in claim 19.
Regarding claim 20, Yen discloses that switches S13 and S14 are turned on .
Allowable Subject Matter
Claims 5, 7, 8, 9, 10, 11, 13 - 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATASHA Y MARANO whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren-Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATASHA Y. MARANO
Examiner
Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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