DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed on 05 December 2025. Claims 1-20 are pending in this application. Claims 1-9, 19-20 are directed to the elected embodiment and are examined in this application. Claims 10-18 are directed to the unelected embodiment and are withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the semiconductor device of Invention I in the reply filed on 05 December 2025 is acknowledged.
Drawings
The drawings are objected to because they appear to have mislabeled the gate caps (112) and the self-aligned contact (118). The gate caps (112) are shown above the second source/drain regions (114b) and the self-aligned contacts (118), which are supposed to connect to the source/drain regions (See [00107]) are shown above the gate regions 110. It appears these should be reversed.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 128, 130, 132A, 2020.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 2012.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3-4, 19-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "each of the source and drain regions" in Lines 1-2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Regarding Claim 3, Claim 3 claims “a source/drain contact above each of the source and drain regions”. However, only a first source and drain region has been claimed (in line 4 of Claim 1 from which Claim 3 depends). It is unclear what source and drain regions the limitation in Claim 3 is referring to.
For purposes of examination, examiner is treating the claim as reciting “each of a plurality of second source and drain regions” in place of “each of the source and drain regions”.
Examiner is making this interpretation in view of the drawings applicant has submitted. Applicant’s drawing show a dielectric cap 124 over the first source and drain region 114a, which connects to the backside power rail. There is no self-aligned contact 118 shown connecting through the dielectric cap 124 to the first source/drain regions 114a. Only the second source/drain regions 114b show the SAC contacts 118 (examiner believes mis-labelled as 112) (See Fig. 13a, showing SAC contacts 1310 only over the second source/drain regions).
Regarding Claim 4, Claim 4 depends from Claim 3 and is rejected for the same reasons.
Claim 19 recites the limitation " the backside contact is surrounded by a backside interlayer dielectric (BILD), a backside power rail (BSPR), a backend dielectric isolation (BDI), and the source and drain region." in Lines 6-7 of the claim. There is insufficient antecedent basis for the limitation “the source and drain region” in the claim. The claim previously claimed “a first and second source and drain regions”. It is unclear which source/drain region is referenced by “the source and drain region”. For purposes of examination, “the source and drain region” is being interpreted as “the first source and drain region” in order to be consistent with applicant’s drawings.
Regarding Claim 20, Claim 20 depends from Claim 19 and is rejected for the same reasons.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Yu et. al (US 2022/0115510 A1).
Regarding Claim 1, Yu discloses (as shown in Fig. 1A-C) A semiconductor device ([0015] FIG. 1A illustrates an isometric view of a BPR semiconductor device 100 with capacitance reduction using an air gap 126, in accordance with some embodiments.), comprising:
a plurality of gate caps ([0027] a gate capping structure 134) over a plurality of gate regions ([0016] gate structures 112); ([0031] Gate capping structure 134 can be disposed on gate structures 112 and configured to protect underlying structures and/or layers during processing of BPR semiconductor device 100.)
gate spacers ([0026] Referring to FIGS. 1B and 1C, gate spacers 116) over sidewalls of the plurality of gate regions (112) and the plurality of gate caps (134); ([0026] Referring to FIGS. 1B and 1C, gate spacers 116 can be disposed along sidewalls of gate structures 112) (See Fig. 1B, showing the gate spacers 116 on the sidewall of the ate capping layer 134 on the bottom portion of the t-shaped structure)
a backside contact ([0015] A second interconnect structure 104 (also referred to as “backside interconnect structure 104”)) under a first source and drain region ([0027] second S/D region 110B), ([0027] Backside contact structure 148 and backside interconnect structure 104 can connect second S/D region 110B to backside power rails 103)
wherein the first source and drain region (110B) is located between two adjacent gate regions (112) of the plurality of gate regions (112); (See Fig. 1B, showing the second S?D region 110B between 2 adjacent gate regions 112)
and a dielectric cap ([0030] second capping structure 136B) over the first source and drain region. (110B) ([0032] second capping structure 136B can be disposed above air gap 126) ([0030] As shown in FIGS. 1B and 1C, air gap 126 can be disposed between second capping structure 136B and second S/D region 110B.)
Regarding Claim 3, Yu further discloses (as shown in Figs. 1A-C) a source/drain contact ([0027] front-side interconnect structure 114) above each of a plurality of second source and drain regions ([0022] first S/D region 110A), ([0017] Though FIGS. 1A-1C show one finFET, BPR semiconductor device 100 can have any number of finFETs.) ([0027] As shown in FIGS. 1A-1C, front-side S/D contact structure 132A and front-side interconnect structure 114 can connect first S/D region 110A to front-side power rails 105.) ([0033] Referring to FIGS. 1A-1C, front-side interconnect structure 114 can connect to front-side S/D contact structure 132A and extends through first capping structure 136A, second etch stop layer (ESL) 138, and front-side ILD layer 140.)
wherein the source/drain contact (114) is surrounded by an interlayer dielectric layer (ILD) ([0027] a front-side interlayer dielectric (ILD) layer 140). ([0033] Referring to FIGS. 1A-1C, front-side interconnect structure 114 … extends through first capping structure 136A, second etch stop layer (ESL) 138, and front-side ILD layer 140.)
Claim interpretation note: See 112b rejection to explain why the claim is being interpreted as reciting the underlined limitation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to Claim 1 above.
Regarding Claim 2, Yu fails to disclose wherein the dielectric cap (136B) is made of a same material as the plurality of gate caps (134) and the gate spacers (116).
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the dielectric cap be made of a same material as the plurality of gate caps and the gate spacers based on the teaching of Yu. Yu teaches a number of possible materials for:
the dielectric cap (136B) ([0032] In some embodiments, first and second capping structures 136A and 136B can include insulating materials, such as silicon oxide (SiO.sub.x), silicon oxycarbide (SiOC), aluminum oxide (AlO.sub.x), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon nitride (SiN.sub.x), silicon oxynitricarbide (SiOCN), zirconium nitride (ZrN), silicon carbonitride (SiCN), and other suitable materials.)
the gate caps (134) ([0031] Gate capping structure 134 can include one or more insulating materials. In some embodiments, the insulating materials can include silicon oxide (SiO.sub.x), hafnium silicide (HfSi), silicon oxycarbide (SiOC), aluminum oxide (AlO.sub.x), zirconium silicide (ZrSi), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon nitride (SiN.sub.x), silicon oxynitricarbide (SiOCN), silicon (Si), zirconium nitride (ZrN), silicon carbonitride (SiCN), or other suitable materials.)
and the gate spacers (116) ([0026] Each of gate spacers 116 and inner spacer structures 127 can include a dielectric material, such as silicon oxide (SiO.sub.x), silicon oxynitride (SiO.sub.yN), silicon nitride (SiN.sub.x), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxynitricarbide (SiOCN), and a combination thereof.)
Yu teaches that each of the dielectric cap (136B), gate caps (134), and the gate spacers (116) can be made from as silicon oxide (SiO.sub.x), silicon nitride (SiN.sub.x), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), or silicon oxynitricarbide (SiOCN). Therefore, it would have been obvious to make each of the dielectric cap (136B), gate caps (134), and the gate spacers (116) from any of these materials, including the same materials.
Regarding Claim 8, Yu further discloses (as shown in Figs. 1A-C) a backside interlayer dielectric (BILD) ([0027] a backside ILD layer 146) located under a backend liner ([0027] liner 144); ([0037] Liner 144 can be disposed between backside ILD layer 146 and first and second S/D regions 110A and 110B)
and a backside power rail (BSPR) ([0015] backside power rails 103).
However, Yu fails to disclose that the backend liner (144) is a dielectric layer;
And the backside power rail (BSPR) is over a backside power delivery network (BSPDN).
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the backend liner (144) be a dielectric layer and the backside power rail (BSPR) be over a backside power delivery network (BSPDN). Yu teaches a backside liner (144) to protect the gate and S/D regions during deposition of the backside IDL layer (140) ([0037] In some embodiments, liner 144 can provide protection to gate structures 112 and first and second S/D regions 110A and 110B during the formation of backside ILD layer 146) Dielectric liners are commonly used in transistors, and it would have been obvious for the liner to be dielectric to not create undesired current paths to between the gates and S/D regions.
It also would have been obvious to a person having ordinary skill in the art before the effective filing date of the application for the backside power rail (BSPR) (103) is over a backside power delivery network (BSPDN). This is a typical arrangement in the construction of backside power rails in transistor design.
Regarding Claim 9, Yu further discloses (as shown in Fig. 1B) wherein the backside contact (104) is surrounded by the BILD (146), the BSPR (103), the BDI (144), and the first source and drain region (110B) (See Fig. 1B, showing the backside interconnect structure 104 surrounded by: on the top, second S/D region 110B; on the bottom, backside power rail 103; and on the sides, liner 144 and IDL 140)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to Claim 3 above.
Regarding Claim 4, Yu fails to disclose wherein the dielectric cap (136B) and the ILD (140) are made of different materials.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the dielectric cap and ILD to be made of different materials based on the teaching of Yu. Yu teaches a number of possible materials for:
the dielectric cap (136B) ([0032] In some embodiments, first and second capping structures 136A and 136B can include insulating materials, such as silicon oxide (SiO.sub.x), silicon oxycarbide (SiOC), aluminum oxide (AlO.sub.x), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon nitride (SiN.sub.x), silicon oxynitricarbide (SiOCN), zirconium nitride (ZrN), silicon carbonitride (SiCN), and other suitable materials.)
and the ILD ([0036Front-side ILD layer 140 can include a dielectric material to isolate front-side interconnect structure 114 and other interconnect structures. The dielectric material can be deposited using a deposition method suitable for flowable dielectric materials (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide).)
It would have been obvious to make the dielectric cap (136B) and the ILD (140) from any of the materials listed in either list, such as making the ILD layer (140) from flowable silicon oxynitride, which is not listed as a material for the dielectric caps (136B).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et. al (US 2022/0115510 A1).
Regarding Claim 19, Yu discloses (as shown in Figs. 1A-C) A semiconductor device ([0015] FIG. 1A illustrates an isometric view of a BPR semiconductor device 100 with capacitance reduction using an air gap 126, in accordance with some embodiments.), comprising:
a plurality of nanosheet gates ([0024] Referring to FIGS. 1A-1C, gate structures 112 can be multi-layered structures and can be wrapped around semiconductor layers 122 of fin structure 108. In some embodiments, each of semiconductor layers 122 of fin structure 108 can be wrapped around by one or more layers of gate structures 112, respectively, and gate structures 112 can be referred to as “gate-all-around (GAA) structures” and FET 102 can be referred to as “GAA FET” or “GAA finFET.”) located between a first ([0021] second S/D regions … 110B) and second ([0021] first … S/D regions 110A) source and drain regions; (See Fig. 1B, showing the gate structures 112 between the first (110B) and second (110A) source/drain regions)
a backside contact ([0015] A second interconnect structure 104 (also referred to as “backside interconnect structure 104”)) under a first source and drain region ([0027] second S/D region 110B), ([0027] Backside contact structure 148 and backside interconnect structure 104 can connect second S/D region 110B to backside power rails 103)
and a dielectric cap ([0030] second capping structure 136B) located over the first source and drain region. (110B) ([0032] second capping structure 136B can be disposed above air gap 126) ([0030] As shown in FIGS. 1B and 1C, air gap 126 can be disposed between second capping structure 136B and second S/D region 110B.)
wherein: the backside contact (104) is surrounded by a backside interlayer dielectric (BILD) ([0027] a backside ILD layer 146), a backside power rail (BSPR) ([0015] backside power rails 103), a backend liner ([0027] liner 144), and the first source and drain region (110B) (See Fig. 1B, showing the backside interconnect structure 104 surrounded by: on the top, second S/D region 110B; on the bottom, backside power rail 103; and on the sides, liner 144 and IDL 140)
However, Yu fails to disclose that the backend liner (144) is a dielectric layer;
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the backend liner (144) be a dielectric layer and the backside power rail (BSPR) be over a backside power delivery network (BSPDN). Yu teaches a backside liner (144) to protect the gate and S/D regions during deposition of the backside IDL layer (140) ([0037] In some embodiments, liner 144 can provide protection to gate structures 112 and first and second S/D regions 110A and 110B during the formation of backside ILD layer 146) Dielectric liners are commonly used in transistors, and it would have been obvious for the liner to be dielectric to not create undesired current paths to between the gates and S/D regions.
Regarding Claim 20, Yu further discloses (as shown in Fig. 1B) a gate cap ([0027] a gate capping structure 134) over a gate region ([0016] gate structures 112); ([0031] Gate capping structure 134 can be disposed on gate structures 112 and configured to protect underlying structures and/or layers during processing of BPR semiconductor device 100.)
and gate spacers ([0026] Referring to FIGS. 1B and 1C, gate spacers 116) over sidewalls of the gate region (112); ([0026] Referring to FIGS. 1B and 1C, gate spacers 116 can be disposed along sidewalls of gate structures 112)
Allowable Subject Matter
Claim 5-7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 5, Yu fails to disclose wherein the plurality of gate regions (112) is so arranged in a staggered arrangement such that there is an overlap region between two adjacent gate regions (112) of the plurality of gate regions (112), and the gate spacers (116) pinch off the overlap region.
Other relevant prior art includes Wang et. al (US 2021/0305262 A1). Wang discloses (as shown in Fig. 3A, 8):
wherein the plurality of gate regions ([0032] the gate 708) ([0029] For one memory cell 301, the location of the transistors PG1, PD1, PU2, PU1, PD2, and PG2 are shown. The transistors are formed where a gate structure crosses an active region.) is so arranged in a staggered arrangement such that there is an overlap region between two adjacent gate regions (708) of the plurality of gate regions (708) (See Fig. 3, showing the gate of the pass-gate transistor PG1 is staggered with the combined gate of the pull-down transistor PD1 and the pull-Up Transistor PU2; and the combined gate of the pull-down transistor PD1 and the pull-Up Transistor PU2 is staggered with the combined gate of the pull-down transistor PD2 and the pull-Up Transistor PU1; and the combined gate of the pull-down transistor PD1 and the pull-Up Transistor PU2 is staggered with the gate of the pass-gate transistor PG2)
However, Wang fails to disclose the gate spacers (116) pinch off the overlap region.
Other relevant prior art includes Chuang et. al (US 2023/0018869 A1. Chuang discloses (as shown in Fig. 3): a plurality of vertical transistors ([0025] the transistor array 170 includes a plurality of transistors 200)
wherein the plurality of gate regions ([0032] In some embodiments, the gate pattern 270 includes gate sections 272) is so arranged in a staggered arrangement such that there is an overlap region between two adjacent gate regions (272) of the plurality of gate regions (272)
However, Chuang fails to disclose and the gate spacers (272) pinch off the overlap region.
Since the prior art does not contain every limitation of the claim, Claim 5 contains allowable subject matter.
Regarding Claims 6-7, Claims 6-7 depend from Claim 5 and contain allowable subject matter for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Horiguchi et. al (“Backside Power Delivery: How to power chips from the Backside: Benefits and building blocks of a backside power delivery network; https://www.imec-int.com/en/articles/how-power-chips-backside)
Horiguchi discloses a backside power delivery system with the buried power rail above the power delivery network. ([Page 10 Lines 3-9] The potential of the BPRs can be fully exploited when combined with nTSVs, high-aspect-ratio vias processed in the thinned wafer’s backside. Together, they allow for delivering the power from the wafer’s backside to the active devices in the front-end in the most efficient way, i.e., with the largest gains in terms of IR drop reduction.)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.J.G./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893