Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 11 have been fully considered, a new ground for rejection has been made in view of amendment. Claims 1 and 11 are rejected under 35 U.S.C 103 (See 103 rejection of claim 1 below).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 8-10, 11-13 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20130046886 A1 (hereinafter Pannell), in view of US 20110018711 A1 (hereinafter Harel) and US 20140365629 A1 (hereinafter Umezawa).
Regarding claim 1, Pannell teaches A network device, comprising (Pannell [0022] physical layer
devices (e.g., Ethernet PHY devices) and switches.):
a plurality of ports (Pannell [0022] physical layer devices (e.g., Ethernet PHY devices) and
switches support generation of one or more LED controls (e.g., current I.sub.O control via LED generation logic 202) on each physical port on the device.);
a plurality of optical indicators (Pannell [0003] Light-emitting diodes (LEDs) are used to indicate
various status information by blinking or maintaining an on or off state. [0022] physical layer devices (e.g., Ethernet PHY devices) and switches support generation of one or more LED controls (e.g., current I.sub.O control via LED generation logic 202) on each physical port on the device.);
two or more packet processing circuits, to process packets communicated over the ports, each
packet processing circuit to control a subset of the optical indicators to display status information relating to a subset of the ports, wherein at least some of the status information is represented by blinking of the optical indicators (Pannell Fig. 2 and Fig. 3;
[0022] FIG. 2 illustrates an example 200 of a light-emitting diode (LED) controller system. Many physical layer devices (e.g., Ethernet PHY devices) and switches support generation of one or more LED controls (e.g., current I.sub.O control via LED generation logic 202) on each physical port on the device. For example, one LED communication function is to indicate that a link or a successful connection of a cable from one device/box to another device/box has been established such that data can flow over that network cable. Another LED communication function is to indicate an activity, such as transmission or reception of data over the cable. For example, these functions can be combined into a single LED 204 operation, as shown below in Table 1.
TABLE-US-00001 TABLE 1
LED State: Communication Function:
Off No link established
On Link established, but no data flowing
Blinking at X rate Link established and data flowing
[0025] FIG. 3 illustrates an example 300 of an LED controller configured for network protocols. This particular example illustrates a network protocol filtering or restriction mode approach whereby timing protocol related frames and/or other existing and future IEEE 802.1 protocol frames can be restricted from participating in LED operation. In this example, LED filtering logic 312 is configured to mask selected protocol related frames from LED activity generation. while examples herein are related to protocols, the described embodiments may also be used in any system that checks or monitors link or connection activity that can be related to or indicated by the activity of an LED or other status indicator.
[0029] The LED activity generation logic 202 can be implemented in a network port's physical layer (PHY) device. Alternatively, the LED activity generation logic 202 can be implemented via the port's switch media access control (MAC) logic. LED 204 can be implemented to blink when receive or transmit activity is detected at the port by the PHY, MAC, or any other suitable logic or other circuitry.
Note: A LED controller system in Fig. 2 and 3 is a packet processing circuit.); and
Pannell does not explicitly teach synchronization circuitry, to synchronize at least one operational characteristic of the optical indicators among the two or more packet processing circuits, wherein the synchronization circuitry comprises a synchronization source circuit connected to the packet processing circuits, directly or indirectly, by at least one bus, and wherein the synchronization source circuit is to send a synchronization indication to the packet processing circuits by sending bits indicative of the synchronization indication over the at least one bus.
Harel in the same or similar field of endeavor teaches synchronization circuitry, to synchronize at least one operational characteristic of the optical indicators among the two or more packet processing circuits, and wherein send a synchronization indication to the packet processing circuits by sending bits indicative of the synchronization indication (Harel Fig. 1; [0003] in data networks, such as Ethernet networks, the display is used to indicate the status of certain conditions, such as whether there is activity at a certain port of a network switch, whether there is transmit or receive activity at a port, the indication of a collision of data frames, and the like. One of the most common display devices in electronic systems is a Light Emitting Diode (LED) display.
[0007] the multiple element display can comprise a plurality of individual light-emitting diodes (LEDs). The plurality of devices can include ports of a communication device. the communication device can include a network switch. for the ports of a network switch, the characteristic of the plurality of devices can include at least one of a port speed, one of full duplex and half duplex, one of communications link up and down, port activity, port disabled, packet collision, and erroneous frame receiving.
[0032]"indicator information" is any type of data that can indicate the state, condition, status, characteristics, or the like about an electronic device or devices. For example, the indicator information can be comprised of a series of bits, with each bit representing, for example, status information of a specific characteristic of the device or devices. For example, the devices can be the ports of a network switch or the like. The stream of bits that can comprise the indicator information can be used, for example, to illuminate Light Emitting Diodes (LEDs) according to desired patterns to visually communicate the status of the ports of the network switch to the user.
[0033] FIG. 1 is a block diagram illustrating a system 100 for customizing indicator information for displaying status information to a user.
[0042] the system 100 can include a plurality of blinking mechanisms configured to cause blinking of the indicator information. Each of the plurality of blinking mechanism can be associated with a duty cycle and a rate.
[0052] Exemplary embodiments of the present invention can be used to display status information from multiple streams of indicator information, where each stream of indicator information includes status information from a different device. the serializer 130 can include a synchronizer 135 for synchronizing different serial streams of bits of indicator information to synchronize the blinking rate of information included in the different serial streams of bits of indicator information.
Note: synchronize LED blink rate for different devices (i.e. ports).).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Pannell with Harel’s above teachings. The motivation is customizing the LED display of a network switch (Harel [0002-0003]).
Harel does not explicitly teach wherein the synchronization circuitry comprises a synchronization source circuit connected to the packet processing circuits, directly or indirectly, by at least one bus, the synchronization source circuit is to send a synchronization indication over the at least one bus.
Umezawa in the same or similar field of endeavor teaches wherein the synchronization circuitry comprises a synchronization source circuit connected to the packet processing circuits, directly or indirectly, by at least one bus, the synchronization source circuit is to send a synchronization indication over the at least one bus (Umezawa Fig. 1; [0021] FIG. 1 shows an example of a configuration diagram of an information processing system using synchronous control through an FPGA (control device: control device using a field-programmable gate array) in an information processing device.
[0026] The FPGA 106a is connected to the processor 101a, the chipset 103a, the VRs 107a, the LED 111a, and the temperature sensor 112a using general-purpose input/output pins (GPIO). Further, the FPGA 106a is mutually connected to an FPGA 106b of another information processing device 100b having the same configuration as the information processing device 100a through a front plane 117 using a full-duplex serial I/F transmission channel 123.
[0029] The FPGA 106a transmits synchronous packets of data of a state input from the general-purpose I/F or the general-purpose input/output pins to the FPGA 106b of the information processing device 100b using the transmission channel 123 at predetermined time intervals. Further, the FPGA 106b having received the synchronous packets decodes the received data to be reflected on the state of the general-purpose input/output pins.
Note: as shown in Fig. 1, The FPGA 106a is connected to the processor 101a; The FPGA 106a is connected to the FPGA 106b. The FPGA 106b is connected to the processor 101b.).
By modifying Pannell with Harel’s teachings of synchronization circuitry, to synchronize at least one operational characteristic of the optical indicators among the two or more packet processing circuits, and wherein send a synchronization indication to the packet processing circuits by sending bits indicative of the synchronization indication with Umezawa’s teachings of wherein the synchronization circuitry comprises a synchronization source circuit connected to the packet processing circuits, directly or indirectly, by at least one bus, the synchronization source circuit is to send a synchronization indication over the at least one bus, the modification results in
synchronization circuitry, to synchronize at least one operational characteristic of the optical indicators among the two or more packet processing circuits, wherein the synchronization circuitry comprises a synchronization source circuit connected to the packet processing circuits, directly or indirectly, by at least one bus, and wherein the synchronization source circuit is to send a synchronization indication to the packet processing circuits by sending bits indicative of the synchronization indication over the at least one bus.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Pannell as modified by Harel with Umezawa’s above teachings. The motivation is having a synchronous control mechanism among plural information processing devices (Umezawa [0002]).
Claim 11 recites similar limitations of claim 1, is thus rejected under similar rational.
Regarding claim 2, Pannell in view of Harel and Umezawa (hereinafter combination)
teaches The network device according to claim 1.
Pannell does not explicitly teach wherein the synchronization source circuit is to generate the
synchronization indication.
Umezawa teaches wherein the synchronization source circuit is to generate the synchronization indication (Umezawa Fig. 1; [0021] FIG. 1 shows an example of a configuration diagram of an information processing system using synchronous control through an FPGA (control device: control device using a field-programmable gate array) in an information processing device.
[0029] The FPGA 106a transmits synchronous packets of data of a state input from the general-purpose I/F or the general-purpose input/output pins to the FPGA 106b of the information processing device 100b using the transmission channel 123 at predetermined time intervals.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Umezawa’s above teachings. The motivation is having a synchronous control mechanism among plural information processing devices (Umezawa [0002]).
Regarding claim 3, the combination teaches The network device according to claim 2.
Pannell does not explicitly teach wherein the synchronization source circuit is connected to the packet processing circuits, directly or indirectly, by two or more buses.
Umezawa teaches wherein the synchronization source circuit is connected to the packet processing circuits, directly or indirectly, by two or more buses (Umezawa Fig. 1; [0021] FIG. 1 shows an example of a configuration diagram of an information processing system using synchronous control through an FPGA (control device: control device using a field-programmable gate array) in an information processing device.
Note: as shown in Fig. 1, The FPGA 106a is connected to the processor 101a; The FPGA 106a is connected to the FPGA 106b. The FPGA 106b is connected to the processor 101b. i.e. The FPGA 106a is connected to the processor 101b via 2 links (2 buses).).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Umezawa’s above teachings. The motivation is having a synchronous control mechanism among plural information processing devices (Umezawa [0002]).
Claim 12, 13 recites similar limitations of claim 2, 3 respectively, is thus rejected under similar rational.
Regarding claim 8, the combination teaches The network device according to claim 1.
Pannel does not explicitly teach wherein the synchronization circuitry is to synchronize a phase
of the blinking among the two or more packet processing circuits.
Harel teaches wherein the synchronization circuitry is to synchronize a phase of the blinking among the two or more packet processing circuits (Harel [0042] the system 100 can include a plurality of blinking mechanisms configured to cause blinking of the indicator information. Each of the plurality of blinking mechanism can be associated with a duty cycle and a rate.
[0052] Exemplary embodiments of the present invention can be used to display status information from multiple streams of indicator information, where each stream of indicator information includes status information from a different device. the serializer 130 can include a synchronizer 135 for synchronizing different serial streams of bits of indicator information to synchronize the blinking rate of information included in the different serial streams of bits of indicator information. Alternatively, the synchronizer 135 can analyze the phase relation between a core clock and the data to determine the magnitude of the phase difference between the streams of indicator information. The synchronizer 135 can then cause the serializer 130 to manipulate the resulting serial stream of bits of indicator information to alter the phase relation between the input streams.
[0032] the devices can be the ports of a network switch.
Note: synchronize phase of blink for different devices (i.e. ports).).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Harel’s above teachings. The motivation is customizing the LED display of a network switch (Harel [0002-0003]).
Regarding claim 9, the combination teaches The network device according to claim 1.
Pannel does not explicitly teach wherein the synchronization circuitry is to synchronize a
frequency of the blinking among the two or more packet processing circuits.
Harel teaches wherein the synchronization circuitry is to synchronize a frequency of the blinking
among the two or more packet processing circuits (Harel [0042] the system 100 can include a plurality of blinking mechanisms configured to cause blinking of the indicator information. Each of the plurality of blinking mechanism can be associated with a rate.
[0052] Exemplary embodiments of the present invention can be used to display status information from multiple streams of indicator information, where each stream of indicator information includes status information from a different device. the serializer 130 can include a synchronizer 135 for synchronizing different serial streams of bits of indicator information to synchronize the blinking rate of information included in the different serial streams of bits of indicator information.
[0032] the devices can be the ports of a network switch.
Note: synchronize blink rate (i.e. frequency of blinking) for different devices (i.e. ports).).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Harel’s above teachings. The motivation is customizing the LED display of a network switch (Harel [0002-0003]).
Regarding claim 10, the combination teaches The network device according to claim 1.
Pannel does not explicitly teach wherein the synchronization circuitry is to synchronize a duty-
cycle of the blinking among the two or more packet processing circuits.
Harel teaches wherein the synchronization circuitry is to synchronize a duty-cycle of the blinking
among the two or more packet processing circuits (Harel 0042] the system 100 can include a plurality of blinking mechanisms configured to cause blinking of the indicator information. Each of the plurality of blinking mechanism can be associated with a duty cycle. At least one class of the plurality of classes can be associated with one of the plurality of blinking mechanisms. Thus, a user can specify that none, any, or all classes are associated with a blinking mechanism. According to exemplary embodiments, all classes associated with a blinking mechanism blink at the duty cycle specified for that blinking mechanism.
[0052] Exemplary embodiments of the present invention can be used to display status information from multiple streams of indicator information, where each stream of indicator information includes status information from a different device. the serializer 130 can include a synchronizer 135 for synchronizing different serial streams of bits of indicator information.
[0032] the devices can be the ports of a network switch.
Note: synchronize duty cycle of the blinking for different devices (i.e. ports). ).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Harel’s above teachings. The motivation is customizing the LED display of a network switch (Harel [0002-0003]).
Claim 18, 19, 20 recites similar limitations of claim 8, 9, 10 respectively, is thus rejected under similar rational.
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pannell in view of Harel and Umezawa as applied to claims 3 and 13 above, and further in view of US 20140215084 A1 (hereinafter Lei).
Regarding claim 4, the combination teaches The network device according to claim 3.
Although Umezawa teaches two or more buses (See Umezawa cited above for rejection of
claim 3.),
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination with Umezawa’s above teachings. The motivation is having a synchronous control mechanism among plural information processing devices (Umezawa [0002]).
Umezawa does not explicitly teach buses are serial buses.
Lei in the same or similar field of endeavor teaches buses are serial buses (Lei [0033] FIG. 2 illustrates a typical hardware configuration of a workstation having a central processing unit (CPU) 210, such as a microprocessor, and a number of other units interconnected via one or more buses 212 which may be of different types, such as … a serial bus.).
By modifying Umezawa’s teachings of two or more buses with Lei’s teachings of buses are serial buses, the modification results in
wherein the two or more buses are serial buses.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified the combination as modified by Umezawa with Lei’s above teachings. The motivation is supporting a proper hardware configuration (Lei [0033]).
Claim 14 recites similar limitations of claim 4, is thus rejected under similar rational.
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pannell in view of Harel and Umezawa and Lei as applied to claims 4 and 14 above, and further in view of US 5887267 A (hereinafter Fugaro).
Regarding claim 5, Pannell in view of Harel and Umezawa and Lei teaches The network device
according to claim 4
Pannell does not explicitly teach wherein the serial buses have a clock rate not exceeding 1 MHz.
Fugaro in the same or similar field of endeavor teaches wherein the serial buses have a clock rate not exceeding 1 MHz (Fugaro Col 8, Lines 35-50, the command clock signal on the serial bus line is typically less than 1 MHz.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Pannell as modified by Harel and Umezawa and Lei with Fugaro’s above teachings. The motivation is reducing data loss (Fugaro Col 8, Lines 35-50).
Claim 15 recites similar limitations of claim 5, is thus rejected under similar rational.
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pannell in view of Harel and Umezawa and Lei as applied to claims 4 and 14 above, and further in view of EP 2615753 A2 (hereinafter Fukasawa).
Regarding claim 6, Pannell in view of Harel and Umezawa and Lei teaches The network device
according to claim 4.
Although Harel teaches sending one or more bits indicative of the synchronization indication to the one or more of the packet processing circuits (See Harel Fig. 1; [0003], [0007], [0032-0033], [0042], [0052] cited above in rejection of claim 1 above.),
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Pannell as modified by Harel and Umezawa and Lei with Harel’s above teachings. The motivation is customizing the LED display of a network switch (Harel [0002-0003]).
Harel does not explicitly teach wherein the synchronization circuitry further comprises at least one intermediary circuit, which (i) is connected to the synchronization source circuit by one of the serial buses, (ii) is connected to one or more of the packet processing circuits, directly or indirectly, by one or more additional serial buses, and (iii) is to relay the synchronization indication from the synchronization source circuit over the one or more additional serial buses.
Fukasawa in the same or similar field of endeavor teaches wherein the synchronization circuitry further comprises at least one intermediary circuit, which (i) is connected to the synchronization source circuit by one of the serial buses, (ii) is connected to one or more of the packet processing circuits, directly or indirectly, by one or more additional serial buses, and (iii) is to relay the synchronization indication from the synchronization source circuit over the one or more additional serial buses (Fukasawa Fig. 1; [0036] Fig. 1 shows a time synchronization system 1 according to the embodiment, which has a master 2 and four slaves (a first slave 3-1 to a fourth slave 3-4 (generically referred to as a slave(s) 3)), a relay 4, and four field devices (a first field device 5-1 to a fourth field device 5-2 (generically referred to as a field device(s) 5).
[0038] the master 2 and the relay 4 are connected to each other by wire and the relay 4 and each slave 3 are connected to each other by wire.
[0004] the master sends time synchronization packets to each slave.
[0005] The time synchronization system 101 includes a master 102, four slaves (a first slave 103-1 to a fourth slave 103-4 (generically referred to as a slave(s) 103), and a relay 104.
[0006] The relay 104 is a network relay for relaying communications between the master 102 and each slave 103.).
By modifying Harel’s teachings of sending one or more bits indicative of the synchronization indication to the one or more of the packet processing circuits with Fukasawa’s teachings of wherein the synchronization circuitry further comprises at least one intermediary circuit, which (i) is connected to the synchronization source circuit by one of the serial buses, (ii) is connected to one or more of the packet processing circuits, directly or indirectly, by one or more additional serial buses, and (iii) is to relay the synchronization indication from the synchronization source circuit over the one or more additional serial buses, the modification results in
wherein the synchronization circuitry further comprises at least one intermediary circuit, which (i) is connected to the synchronization source circuit by one of the serial buses, (ii) is connected to one or more of the packet processing circuits, directly or indirectly, by one or more additional serial buses, and (iii) is to relay the synchronization indication from the synchronization source circuit to the one or more of the packet processing circuits by sending one or more bits indicative of the synchronization indication over the one or more additional serial buses.
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Pannell as modified by Harel and Umezawa and Lei with Fukasawa’s above teachings. The motivation is synchronization for communication between a master and plural slaves (Fukasawa [0001]).
Claim 16 recites similar limitations of claim 6, is thus rejected under similar rational.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pannell in view of Harel and Umezawa and Lei and Fukasawa as applied to claims 6 and 16 above, and further in view of Fugaro.
Regarding claim 7, Pannell in view of Harel and Umezawa and Lei and Fukasawa teaches The
network device according to claim 6.
Pannell does not explicitly teach wherein the one or more additional serial buses have a clock rate not exceeding 1 MHz.
Fugaro in the same or similar field of endeavor teaches wherein the one or more additional serial buses have a clock rate not exceeding 1 MHz (Fugaro Col 8, Lines 35-50, the command clock signal on the serial bus line is typically less than 1 MHz.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have modified Pannell as modified by Harel and Umezawa and Lei and Fukasawa with Fugaro’s above teachings. The motivation is reducing data loss (Fugaro Col 8, Lines 35-50).
Claim 17 recites similar limitations of claim 7, is thus rejected under similar rational.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Z Sun whose telephone number is (571)270-0750. The examiner can normally be reached Monday-Friday 0800am-0500pm.
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/D.Z.S./Examiner, Art Unit 2418 /Moo Jeong/Supervisory Patent Examiner, Art Unit 2418
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