DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/18/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to amended claim 6 have been considered but are not persuasive. Applicant argues Rincon-Mora does not disclose the new claim language amended to claim 6 (to provide current from the first current source to the first source through the first drain) because transistor 34 does not sink current from current mirror 64. While 34 does not sink current from current mirror 64, Examiner believes 32 may be interpreted as the claimed first current source, as 34 does sink the current from 32. The rejections under Rincon-Mora with the new interpretation of the first current source have been presented below. Additionally, new grounds of rejection have been made under Chen (US 2007/0008036).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6-7 and 9-11 are rejected under 35 U.S.C. 102a1 as being anticipated by Chen (US 2007/0008036).
With respect to claim 6, Chen discloses a circuit comprising: a first n-type metal oxide semiconductor (NMOS) transistor (Fig. 3A N7) having a first gate, a first source, and a first drain; a first current source (Fig. 3A P6) coupled (Fig. 3A 303) to the first drain and configurable to provide current from the first current source to the first source through the first drain; a second NMOS transistor (Fig. 3A N2) having a second gate, a second source, and a second drain, wherein the second gate is coupled (Fig. 3A gate N2 coupled through C) to the first drain and has no AC or DC coupling to the first gate external to the first NMOS transistor; a second current source (Fig. 3A I) coupled (Fig. 3A gate of N2 coupled to 321)to the second gate; and a third NMOS transistor (Fig. 3A N1) having a third gate, a third source, and a third drain, wherein the third gate is coupled (Fig. 3A 321) to the second gate, and the third source is coupled (Fig. 3A N1 and N7 sources connected to ground symbol) to the first source.
With respect to claim 7, Chen discloses the circuit of claim 6, further comprising a capacitor (Fig. 3A C) coupled between the first drain and the second gate.
With respect to claim 9, Chen discloses the circuit of claim 6, further comprising: a first p-type metal oxide semiconductor (PMOS) transistor (Fig. 3A P4) having a fourth gate, a fourth source, and a fourth drain, wherein the fourth drain is coupled (Fig. 3A P4 coupled to 323 through 331)to the second drain, the fourth gate is coupled to the fourth drain, and the fourth source is coupled (Fig. 3A sources of P4 and P6 coupled through upper voltage rail) to the first current source; and a second PMOS transistor (Fig. 3A P5) having a fifth gate, a fifth source, and a fifth drain, wherein the fifth gate is coupled (Fig. 3A P4-P5 gates coupled) to the fourth gate, and the fifth source is coupled (Fig. 3A P4 and P5 sources coupled through upper voltage rail) to the fourth source.
With respect to claim 10, Chen discloses the circuit of claim 9, further comprising a third PMOS transistor (Fig. 3A P6) having a sixth gate, a sixth source, and a sixth drain, wherein the sixth gate is coupled (Fig. 3A P6 gate coupled to P5 drain) to the fifth drain, and the sixth source is coupled to the fifth source (Fig. 3A P5-P6 sources coupled through upper voltage rail).
With respect to claim 11, Chen discloses the circuit of claim 10, further comprising a fourth PMOS transistor (Fig. 3A P3) having a seventh gate, a seventh source, and a seventh drain, wherein the seventh gate is coupled (Fig. 3A P3 gate coupled to N1 through P3 drain to P1 to 313) to the third drain, and the seventh source is coupled (Fig. 3A source P3 coupled to P6 through upper voltage rail) to the first current source.
Claim(s) 6-7 and 9-11 are rejected under 35 U.S.C. 102a1 as being anticipated by Rincon-Mora (US 6,084,475).
With respect to claim 6, Rincon-Mora discloses a circuit (Fig. 2 100) comprising: a first n-type metal oxide semiconductor (NMOS) transistor (Fig. 2 34) having a first gate (Fig. 2 62), a first source, and a first drain; a first current source (Fig. 2 32) coupled (Fig. 2 36’) to the first drain and configurable to provide current from the first current source through the first drain; a second NMOS transistor (Fig. 2 106) having a second gate (Fig. 2 102), a second source, and a second drain, wherein the second gate is coupled (Fig. 2 coupled through C2) to the first drain and has no AC or DC coupling (Fig. 2 102 not coupled to 62) to the first gate external to the first NMOS transistor; a second current source (Fig. 2 44) coupled to the second gate; and a third NMOS transistor (Fig. 2 104) having a third gate, a third source, and a third drain, wherein the third gate is coupled (Fig. 2 102) to the second gate, and the third source is coupled (Fig. 2 13) to the first source.
With respect to claim 7, Rincon-Mora discloses the circuit of claim 6, further comprising a capacitor (Fig. 2 C2) coupled between the first drain and the second gate.
With respect to claim 9, Rincon-Mora discloses the circuit of claim 6, further comprising: a first p-type metal oxide semiconductor (PMOS) transistor (Fig. 2 40) having a fourth gate, a fourth source, and a fourth drain, wherein the fourth drain is coupled (Fig. 2 14 coupled to 106 through 46,24) to the second drain, the fourth gate is coupled (Fig. 2 14) to the fourth drain, and the fourth source is coupled (Fig. 2 12) to the first current source; and a second PMOS transistor (Fig. 2 42) having a fifth gate, a fifth source, and a fifth drain, wherein the fifth gate is coupled (Fig. 2 14) to the fourth gate, and the fifth source is coupled (Fig. 2 12) to the fourth source.
With respect to claim 10, Rincon-Mora discloses the circuit of claim 9, further comprising a third PMOS transistor (Fig. 2 transistor in 64 connected to 66) having a sixth gate, a sixth source, and a sixth drain, wherein the sixth gate is coupled (Fig. 2 coupled through 52 to 28) to the fifth drain, and the sixth source is coupled (Fig. 2 12) to the fifth source.
With respect to claim 11, Rincon-Mora discloses the circuit of claim 10, further comprising a fourth PMOS transistor (Fig. 2 transistor in 64 connected to 68) having a seventh gate, a seventh source, and a seventh drain, wherein the seventh gate is coupled (Fig. 2 coupled through 54’,56,28) to the third drain (Fig. 2 102), and the seventh source (Fig. 2 68) is coupled (Fig. 2 12) to the first current source (Fig. 2 64).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. See the action dated 9/5/2025 for the reasons for the indication of allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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