DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6-7 are rejected under 35 U.S.C. 102a1 as being anticipated by Morikawa (US 2012/0098574).
With respect to claim 6, Morikawa discloses a circuit comprising: a first n-type metal oxide semiconductor (NMOS) transistor (Fig. 10 M13) having a first gate, a first source, and a first drain; a first current source (Fig. 10 14) coupled to the first drain and configurable to provide a current (Fig. 14 Icnt14) from the first current source to charge the first drain; a second NMOS transistor (Fig. 10 M3) having a second gate, a second source, and a second drain, wherein the second gate is coupled (Fig. 10 gate of M3 coupled to drain of M13 through C2) to the first drain; a second current source (Fig. 10 11) coupled to the second gate; and a third NMOS transistor (Fig. 10 M1) having a third gate, a third source, and a third drain, wherein the third gate is coupled to the second gate, and the third source is coupled (Fig. 10 coupled to ground) to the first source.
With respect to claim 7, Morikawa discloses the circuit of claim 6, further comprising a capacitor (Fig. 10 C2) coupled between the first drain and the second gate.
Claim(s) 6, 7, 9-10 and 16-17 are rejected under 35 U.S.C. 102a1 as being anticipated by Shiro (CN 101204008 A).
With respect to claim 6, Shiro discloses a circuit comprising: a first n-type metal oxide semiconductor (NMOS) transistor (Fig. 2 NT1) having a first gate, a first source, and a first drain (Fig. 2 N1); a first current source (Fig. 2 Iref,PT4,PT1) coupled to the first drain and configurable to provide a current (Fig. 2 current from PT1) from the first current source to charge the first drain; a second NMOS transistor (Fig. 2 NT2) having a second gate, a second source, and a second drain (Fig. 2 N2), wherein the second gate is coupled (Fig. 2 coupled through C3) to the first drain; a second current source (Fig. 2 Iref,PT4,PT2) coupled (Fig. 2 coupled through SW2) to the second gate; and a third NMOS transistor (Fig. 2 NT4) having a third gate, a third source, and a third drain, wherein the third gate is coupled (Fig. 2 coupled through C3) to the second gate, and the third source is coupled (Fig. 2 VSS) to the first source.
With respect to claim 7, Shiro discloses the circuit of claim 6, further comprising a capacitor (Fig. 2 C3) coupled between the first drain and the second gate.
With respect to claim 9, Shiro discloses the circuit of claim 6, further comprising: a first p-type metal oxide semiconductor (PMOS) transistor (Fig. 2 PT4) having a fourth gate, a fourth source, and a fourth drain, wherein the fourth drain is coupled (Fig. 2 coupled through PT2,SW6,C5) to the second drain, the fourth gate is coupled to the fourth drain, and the fourth source is coupled (Fig. 2 VDD) to the first current source; and a second PMOS transistor (Fig. 2 PT2) having a fifth gate, a fifth source, and a fifth drain, wherein the fifth gate is coupled to the fourth gate, and the fifth source is coupled (Fig. 2 VDD) to the fourth source.
With respect to claim 10, Shiro discloses the circuit of claim 9, further comprising a third PMOS transistor (Fig. 2 PT3) having a sixth gate, a sixth source, and a sixth drain, wherein the sixth gate is coupled (Fig. 2 coupled through C5) to the fifth drain, and the sixth source is coupled (Fig. 2 VDD) to the fifth source.
With respect to claim 16, Shiro discloses he circuit of claim 6, wherein the first current source includes a current mirror (Fig. 2 PT4,PT1).
With respect to claim 17, Shiro discloses the circuit of claim 6, wherein the second current source includes a current mirror (Fig. 2 PT4,PT2).
Shiro additionally discloses an alternative embodiment in Figure 4 with the following:
With respect to claim 6, Shiro discloses a circuit comprising: a first n-type metal oxide semiconductor (NMOS) transistor (Fig. 4 NT101) having a first gate, a first source, and a first drain; a first current source (Fig. 4 PT101) coupled to the first drain and configurable to provide a current (Fig. 4 current from PT101) from the first current source to charge the first drain; a second NMOS transistor (Fig. 4 NT102) having a second gate, a second source, and a second drain, wherein the second gate is coupled (Fig. 4 coupled through C103) to the first drain; a second current source (Fig. 4 PT102) coupled (Fig. 4 coupled through SW102) to the second gate; and a third NMOS transistor (Fig. 4 NT103) having a third gate, a third source, and a third drain, wherein the third gate is coupled (Fig. 4 coupled through SW102,C104) to the second gate, and the third source is coupled (Fig. 4 VSS) to the first source.
With respect to claim 7, Shiro discloses the circuit of claim 6, further comprising a capacitor (Fig. 4 C103) coupled between the first drain and the second gate.
With respect to claim 9, Shiro discloses the circuit of claim 6, further comprising: a first p-type metal oxide semiconductor (PMOS) transistor (Fig. 4 PT104) having a fourth gate, a fourth source, and a fourth drain, wherein the fourth drain is coupled (Fig. 4 coupled through SW104,C105) to the second drain, the fourth gate is coupled to the fourth drain, and the fourth source is coupled (Fig. 4 coupled through VDD and PT105) to the first current source; and a second PMOS transistor (Fig. 4 PT103) having a fifth gate, a fifth source, and a fifth drain, wherein the fifth gate is coupled (Fig. 4 coupled through SW104) to the fourth gate, and the fifth source is coupled (Fig. 4 VDD) to the fourth source.
With respect to claim 16, Shiro discloses he circuit of claim 6, wherein the first current source includes a current mirror (Fig. 4 PT101,PT102).
With respect to claim 17, Shiro discloses the circuit of claim 6, wherein the second current source includes a current mirror (Fig. 4 PT101,PT102).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Morikawa (US 2012/0098574).
With respect to claim 12, Morikawa discloses the circuit of claim 6 as set for above, and remains silent as to wherein the current provided by the first current source is greater than a current provided by the second current source. However, Morkiawa does disclose wherein gm13 can be set equal to gm2 (paragraph 91), and by equations 16 and 20, the first current source Icnt14 is greater than the second current source Icnt11 when the gain of transistor M2 is greater than the gain of transistor 13. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the current provided by the first current source is greater than a current provided by the second current source, in order to increase the feedback from the drain of M1 by increasing the gain of transistor M2.
Allowable Subject Matter
Claims 8, 11 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 8, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily,
a first diode having a first anode and a first cathode, wherein the first anode is coupled to the first drain; and a second diode having a second anode and a second cathode, wherein the second anode is coupled to the first cathode, and the second cathode is coupled to a ground terminal.
With respect to claim 11, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily,
a fourth PMOS transistor having a seventh gate, a seventh source, and a seventh drain, wherein the seventh gate is coupled to the third drain, and the seventh source is coupled to the first current source.
With respect to claim 13, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the first, second, and third NMOS transistors and the first and second current sources are part of a start-up circuit of a voltage regulator.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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