DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-21 are pending. Claims 1-21 have been amended as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on June 11, 2026
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 11, 2026 has been entered.
Claim Objections
Claim 13 is objected to because of the following informalities: in the fifth to last line of the claim it recites “first cache memory has the second cache level …”. Examiner believe this is a typographical error since it has been previously recited in an earlier amended limitation and should instead be “second cache memory has the second cache level …” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 recites “the first cache subsystem having a first level”, “the first cache memory having the first level”, “the second cache memory has the first level”, “the first cache controller having the first level”, “a second cache subsystem having a second level”, “the first memory having a second level”, ”the second memory having a second level”, and “the second cache controller having the second level”.
The specification is mute in regards to what “having a first level” or “having a second level” means. The terms "having a first level" and "having a second level," when applied to a "subsystem," "cache memory," and "controllers," lack any corresponding structural or functional definition within the specification. As these terms are used as modifiers without an identified object, the specification fails to establish the scope of the invention or disclose what characterizes these specific "levels" in the context of the claimed components. Consequently, a person of ordinary skill in the art cannot discern the nature of these levels, whether they refer to a memory hierarchy, logical partitioning, or a different architectural feature, and is therefore left to engage in undue experimentation to interpret the functional or structural boundaries of the claimed invention. Furthermore, the lack of disclosure regarding the relationship between the components and these "levels" indicates that the inventor was not in possession of the claimed invention at the time of filing. Because the specification fails to define the criteria or properties that constitute these levels for the recited elements, the claims do not meet the enablement or written description requirements set forth in 35 U.S.C. 112(a). Also see 112(b) rejection below.
Therefore the specification as originally filed does not provide support for “the first cache subsystem having a first level”, “the second cache memory has the first level”, “the first cache memory having the first level”, “the first cache controller having the first level”, “a second cache subsystem having a second level”, “the first memory having a second level”, ”the second memory having a second level”, or “the second cache controller having the second level”. Claims 2-12 depends on claim 1 and inherits this deficiency.
Claims 13 recites “the first cache subsystem having a first level”, “second cache subsystem has a second level”, “the first memory having the level”, “the first cache memory having the second level”, “the first cache memory having the second level” (see objection above), “second memory has the first level”, and “the first cache controller having the first level”.
The specification is mute in regards to what “having a first level” or “having a second level” means. The terms "having a first level" and "having a second level," when applied to a "subsystem," "cache memory," and "controllers," lack any corresponding structural or functional definition within the specification. As these terms are used as modifiers without an identified object, the specification fails to establish the scope of the invention or disclose what characterizes these specific "levels" in the context of the claimed components. Consequently, a person of ordinary skill in the art cannot discern the nature of these levels, whether they refer to a memory hierarchy, logical partitioning, or a different architectural feature, and is therefore left to engage in undue experimentation to interpret the functional or structural boundaries of the claimed invention. Furthermore, the lack of disclosure regarding the relationship between the components and these "levels" indicates that the inventor was not in possession of the claimed invention at the time of filing. Because the specification fails to define the criteria or properties that constitute these levels for the recited elements, the claims do not meet the enablement or written description requirements set forth in 35 U.S.C. 112(a). Also see 112(b) rejection below.
Therefore the specification as originally filed does not provide support for “the first cache subsystem having a first level”, “second cache subsystem has a second level”, “the first memory having the level”, “the first cache memory having the second level”, “the first cache memory having the second level” (see objection above), “second memory has the first level”, or “the first cache controller having the first level”. Claims 14-21 depends on claim 13 and inherits this deficiency.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 13 recites the limitations “has/having a first level” and “has/having a second level”. The terms "having a first level" and "having a second level," as recited in reference to a "cache subsystem," "cache memory," and "controllers," are insolubly ambiguous because they lack a clear antecedent or structural reference. By using these phrases as modifiers without defining the object being modified or the criteria for these levels, the claim language fails to inform those skilled in the art about the scope of the invention with reasonable certainty. A person of ordinary skill in the art cannot determine whether these levels refer to a known memory hierarchy (e.g., L1/L2 cache levels), logical access levels, or some other architectural parameter, and the specification provides no interpretive guidance to resolve this uncertainty. Because the claim language is fundamentally vague and lacks a definitive framework for interpreting the claimed "levels," it fails to set the necessary boundaries for the public to determine what is or is not covered by the scope of the claims. The absence of a clear structural or functional relationship between the recited components and the claimed levels leaves the claim subject to multiple, conflicting interpretations. Consequently, the claim fails to provide the required clarity to enable a skilled artisan to distinguish between the claimed elements and the prior art or to understand the bounds of the protected technology, rendering the claim indefinite.
For examination purposes examiner will interpret the limitations as “first/second cache subsystem at a first/second cache level hierarchy”, “first/second memory is part of a first/second cache level hierarchy”, “first/second cache memory is part of a first/second cache level hierarchy”, and “first/second controller is part of a first/second cache level hierarchy”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-6, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over RAO et al. (US 2014/0317351) (hereinafter Rao) (published October 23, 2014) in view of Chachad et al. (US 2012/0191916) (hereinafter Chachad) (published July 26, 2012).
Regarding Claim 1, Rao discloses a device comprising: a processor core;
“As is well known, the L1 cache 102, often called the primary cache, is a static memory integrated with processor core 120 that is used to store information recently accessed by the processor 120” (Rao [0007] see fig. 1)
a first cache subsystem having a first level, the first cache subsystem comprising: a first cache memory configured to store a first set of cache entries, the first cache memory having the first level; a second cache memory configured to store a second set of cache entries, wherein the second cache memory has the first level; and (see 112 interpretation above)
“FIG. 1 illustrates a victim cache scheme implemented by a conventional processor. In the victim cache scheme, incoming blocks from memory 158 (or L2 cache 156 if present) are always loaded into the L1 cache 102 with one of the cache blocks in L1 102 being replaced and moved to the victim cache 104. The victim cache 104 in turn discards one of its blocks and moves it back to memory 158 (or L2 cache 156 if present)” (Rao [0006] see fig. 1, L1 cache is the first cache memory and victim cache is the second cache memory, and they are both in level 1)
evict a cache entry from the first cache memory by storing the cache entry in the second cache memory,
“FIG. 1 illustrates a victim cache scheme implemented by a conventional processor. In the victim cache scheme, incoming blocks from memory 158 (or L2 cache 156 if present) are always loaded into the L1 cache 102 with one of the cache blocks in L1 102 being replaced and moved to the victim cache 104. The victim cache 104 in turn discards one of its blocks and moves it back to memory 158 (or L2 cache 156 if present)” (Rao [0006] see fig. 1, evicted block from L1 is loaded stored into the victim cache)
But does not explicitly state a first cache controller coupled to the processor core, the first cache memory and the second cache memory, wherein the first cache controller is configured to; the first cache controller having the first level; and a second cache subsystem having a second level different from the first level of the cache subsystem, the second cache subsystem comprising: a first memory configured to store a first set of tag data associated with the first set of cache entries stored in the first cache memory of the first cache subsystem, the first memory having the second level; a second memory configured to store a second set of tag data associated with the second set of cache entries stored in the second cache memory of the first cache subsystem, the second memory having the second level; and a second cache controller coupled to the first cache controller, the first memory, and the second memory, the second cache controller having the second level.
However Rao does disclose a second level cache
“The victim cache 104 in turn discards one of its blocks and moves it back to memory 158 (or L2 cache 156 if present)” (Rao [0006] see fig. 1 for L2 cache connected to L1)
Chachad and Rao discloses a first cache controller coupled to the processor core, the first cache memory and the second cache memory, wherein the first cache controller is configured to; the first cache controller having the first level; and (see 112 interpretation above)
“FIG. 7 illustrates further details of DMC 710 and UMC 730. DMC 710 includes L1D cache tags 711. These tags are the non-data part of cache lines 510, 520 and 530 illustrated in FIG. 5 for L1D cache 123” (Chachad [0050] see fig. 7, DMC is coupled to the CPU, L1D, and UMC, DMC is part of the first level)
a second cache subsystem having a second level different from the first level of the cache subsystem, the second cache subsystem comprising: a first memory configured to store a first set of tag data associated with the first set of cache entries stored in the first cache memory of the first cache subsystem, the first memory having the second level; (see 112 interpretation above)
“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM” (Chachad [0051] the shadow tag memory is part of the second level)
“FIG. 1 illustrates a victim cache scheme implemented by a conventional processor. In the victim cache scheme, incoming blocks from memory 158 (or L2 cache 156 if present) are always loaded into the L1 cache 102 with one of the cache blocks in L1 102 being replaced and moved to the victim cache 104. The victim cache 104 in turn discards one of its blocks and moves it back to memory 158 (or L2 cache 156 if present)” (Rao [0006])
a second memory configured to store a second set of tag data associated with the second set of cache entries stored in the second cache memory of the first cache subsystem, the second memory having the second level; and (see 112 interpretation above)
“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM” (Chachad [0051] the shadow tag memory is part of the second level)
“FIG. 1 illustrates a victim cache scheme implemented by a conventional processor. In the victim cache scheme, incoming blocks from memory 158 (or L2 cache 156 if present) are always loaded into the L1 cache 102 with one of the cache blocks in L1 102 being replaced and moved to the victim cache 104. The victim cache 104 in turn discards one of its blocks and moves it back to memory 158 (or L2 cache 156 if present)” (Rao [0006])
a second cache controller coupled to the first cache controller, the first memory, and the second memory, the second cache controller having the second level. (see 112 interpretation above)
“FIG. 7 illustrates further details of DMC 710 and UMC 730. DMC 710 includes L1D cache tags 711. These tags are the non-data part of cache lines 510, 520 and 530 illustrated in FIG. 5 for L1D cache 123. UMC 730 includes two sets of cache tags” (Chachad [0050] see fig. 7, UMC is connected to DMC and the shadow tag memory in L2)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the controllers and shadow tags disclosed by Chachad with the system in Rao.
Furthermore, a person of ordinary skill in the art would find it obvious to extend the shadow tag tracking of Chachad to encompass both the primary L1 cache entries and the victim cache entries. Since the victim cache acts as an extension of the primary cache in Rao’s scheme, maintaining coherence requires that the L2-level cache controller (the UMC) be aware of the status of all data residing at the L1 level, including entries that have been evicted to the victim cache. Implementing this shadow tag tracking for both the L1 and victim cache memories ensures the system maintains a unified, coherent view of the entire first-level cache state, thereby preventing coherence violations and improving overall system reliability during snoop operations. The motivation for doing so would be to improve coherency of the memories by providing an efficient mechanism for tracking cache line states and ensuring data coherency between the first-level cache subsystems and the L2 level.
Regarding Claim 4, Chachad further discloses wherein the second cache controller is configured to: receive a request to read data:
“During E1 phase 331, the conditions for the instructions are evaluated and operands are read for all instruction types. For load and store instructions, address generation is performed and address modifications are written to a register file” (Chachad [0027] determining type of instruction)
“During the E2 phase 332, for load instructions, the address is sent to memory” (Chachad [0028] for read instruction only address is sent)
determine whether the request corresponds to a hit or a miss in the first cache memory using the first memory; and
“To determine if a memory access is to data cached within cache 500 (a cache hit), cache 500 compares the address tags for all cache lines to the most significant bits of the memory location accessed. Upon a detecting a match, the position within the cache line along dimension 501 corresponds to the least significant bits of the address permitting identification of the data word accessed” (Chachad [0042])
“Shadow tags 732 include at least the valid and dirty status of the corresponding cache lines in L1D cache 123” (Chachad [0050])
based on the request corresponding to a hit in the first cache memory, provide a snoop request for the data to the first cache controller.
“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache” (Chachad [0051])
Regarding Claim 5, Rao and Chachad further discloses wherein: the second cache subsystem includes a third cache memory; and
“The purpose of the L1 cache 102 is to improve data access speed in cases where the CPU accesses the same data multiple times. The access time of the L1 cache 120 is always faster than the access time of system memory 158 or L2 cache 156” (Rao [0007] the l2 cache is the third cache memory)
“CPU 110 is bidirectionally connected to L1I cache 121 and L1D cache 123. L1I cache 121 and L1D cache 123 are shown together because they are at the same level in the memory hierarchy. These level one caches are bidirectionally connected to L2 130” (Chachad [0049] the l2 cache is the third cache memory)
the second cache controller is further configured to, based on the request corresponding to a miss in the first cache memory: determine whether the request corresponds to a hit or a miss in the third cache memory; and
“In the event of a cache miss to level one instruction cache 121 or to level one data cache 123, the requested instruction or data is sought from level two unified cache 130” (Chachad [0015])
based on the request corresponding to a hit in the third cache memory, provide the data using the third cache memory.
“If the requested instruction or data is stored in level two unified cache 130, then it is supplied to the requesting level one cache for supply to central processing unit core 110” (Chachad [0015])
Regarding Claim 6, Chachad further discloses wherein the second cache controller is configured to: receive a request to write a first set of data;
“During E1 phase 331, the conditions for the instructions are evaluated and operands are read for all instruction types. For load and store instructions, address generation is performed and address modifications are written to a register file” (Chachad [0027] determining type of instruction)
“For store instructions, the address and data are sent to memory” (Chachad [0028] for write instruction address and data is sent)
determine whether the request corresponds to a hit or a miss in the first cache memory using the first memory; and
“To determine if a memory access is to data cached within cache 500 (a cache hit), cache 500 compares the address tags for all cache lines to the most significant bits of the memory location accessed. Upon a detecting a match, the position within the cache line along dimension 501 corresponds to the least significant bits of the address permitting identification of the data word accessed” (Chachad [0042])
“Shadow tags 732 include at least the valid and dirty status of the corresponding cache lines in L1D cache 123” (Chachad [0050])
based on the request corresponding to a hit in the first cache memory, provide a snoop read and invalidate request to the first cache controller.
“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM” (Chachad [0051])
Regarding Claim 9, Chachad further discloses wherein the first set of tag data and the second set of tag data include address data and coherence data.
“Each of cache lines 510, 520 and 530 includes: respective address tags 511, 521 and 522; respective valid bits 512, 522 and 523; respective dirty bits 513, 523 and 533; respective least recently used (LRU) indicators 514, 524 and 534; and respective data words 515, 525 and 535” (Chachad [0040])
Regarding Claim 10, Rao and Chachad further discloses wherein: the first cache subsystem is a level-one (L1) cache subsystem; and the second cache subsystem is a level-two (L2) cache subsystem.
“In the victim cache scheme, incoming blocks from memory 158 (or L2 cache 156 if present) are always loaded into the L1 cache 102 with one of the cache blocks in L1 102 being replaced and moved to the victim cache 104. The victim cache 104 in turn discards one of its blocks and moves it back to memory 158 (or L2 cache 156 if present)” (Rao [0006] L1 cache subsystem has L1 cache and victim cache, L2 cache subsystem has L2 cache)
“The second set of cache tags are shadow tags 732. As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730. Shadow tags 732 include at least the valid and dirty status of the corresponding cache lines in L1D cache 123” (Chachad [0050] see fig. 7, cache 123 is in the L1 level and the shadow tags 732 which corresponds to cache 123 is stored at the L2 level)
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rao (published October 23, 2014) and Chachad (published July 26, 2012) as applied to claim 1 above, and further in view of Habusha et al. (US 2012/0260041) (hereinafter Habusha) (published October 11, 2012).
Regarding Claim 2, the combination of Rao and Chachad disclosed the device of claim 1, but does not explicitly state wherein: the eviction of the cache entry from the first cache memory by the first cache controller includes providing an indication of the eviction to the second cache controller; and wherein the second cache controller is configured to modify the first set of tag data and the second set of tag data based on the indication.
Habusha, Rao, and Chachad discloses wherein: the eviction of the cache entry from the first cache memory by the first cache controller includes providing an indication of the eviction to the second cache controller; and wherein the second cache controller is configured to modify the first set of tag data and the second set of tag data based on the indication.
“if data is to be evicted from a cache line that caches clean or valid data (e.g., caches data that is synchronization with the memory 134), eviction of the data from the cache line involves invalidating data currently cached in the evicted cache line by, for example, updating the tag information and/or valid information in the cache array 112. On the other hand, if data is to be evicted from a cache line that includes dirty data (e.g., includes data that is not synchronized with the memory 134), eviction of the data from the cache line involves (i) writing the evicted data from the cache line to the memory 134 (so that the memory 134 stores the most recent version of the data), and (ii) invalidating the evicted data in the cache line by, for example, updating tag information and/or valid information in the cache array 112” (Habusha [0029] indication of the eviction is provided for the updating of tag information which indicates where the data is)
“In the victim cache scheme, incoming blocks from memory 158 (or L2 cache 156 if present) are always loaded into the L1 cache 102 with one of the cache blocks in L1 102 being replaced and moved to the victim cache 104. The victim cache 104 in turn discards one of its blocks and moves it back to memory 158 (or L2 cache 156 if present)” (Rao [0006] a block is moved to victim cache)
“Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM” (Chachad [0051] to maintain coherence, tags corresponding to both the L1 cache and victim cache are both updated)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the updating of tag information in Habusha with the memory system in the combination of Rao and Chachad. The motivation for doing so would be for better efficiency in locating data when the tags associated with the data are up to date and contain relevant information.
Regarding Claim 3, Habusha further discloses wherein: the cache entry is a first cache entry; the first cache controller is configured to provide, to the second cache controller, a request for data associated with a second cache entry; the eviction of the cache entry from the first cache memory is in response to receiving the data associated with the second cache entry; and the request for the data associated with the second cache entry includes the indication of the eviction of the first cache entry from the first cache memory.
“If the data requested in the read request is not presently stored in the cache array 112, the read request is a miss. In an embodiment, if the read request is a miss, the cache 108 evicts data from a selected cache line, reads the data requested in the read request from the memory 134, and caches the data in the selected cache line (e.g., from which data was evicted earlier)” (Habusha [0028] for a read miss when requesting data, it would include an indication of the cache entry to be evicted for space as the location to store the new data)
“if data is to be evicted from a cache line that caches clean or valid data (e.g., caches data that is synchronization with the memory 134), eviction of the data from the cache line involves invalidating data currently cached in the evicted cache line by, for example, updating the tag information and/or valid information in the cache array 112. On the other hand, if data is to be evicted from a cache line that includes dirty data (e.g., includes data that is not synchronized with the memory 134), eviction of the data from the cache line involves (i) writing the evicted data from the cache line to the memory 134 (so that the memory 134 stores the most recent version of the data), and (ii) invalidating the evicted data in the cache line by, for example, updating tag information and/or valid information in the cache array 112. Once the evicted data is invalidated in the cache line, new data is possibly written in the cache line (i.e., the evicted data is replaced by new data in the cache line)” (Habusha [0029] for the read miss, information about the evicted line and the new line is provided for the updating and inserting of tag information)
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rao (published October 23, 2014) and Chachad (published July 26, 2012) as applied to claim 6 above, and further in view of Chirca et al. (US 2014/0115279) (hereinafter Chirca) (published April 24, 2014).
Regarding Claim 7, the combination of Rao and Chachad disclosed the device of claim 6, but does not explicitly state wherein the second cache controller is further configured to, based on the snoop read and invalidate request returning a second set of data indicated as modified: merge the first set of data and the second set of data to produce a merged set of data; and cause the merged set of data to be written.
Chirca discloses wherein the second cache controller is further configured to, based on the snoop read and invalidate request returning a second set of data indicated as modified: merge the first set of data and the second set of data to produce a merged set of data; and cause the merged set of data to be written.
“If the snoop return is Cached and Dirty with different dirty data in the snoop return than in the coherence write, then comparator 802 triggers a merge write operation. This merge write operation includes only data dirty in the snoop response and clean in the coherence write. As noted above coherence write data queue may store only the corresponding dirty tags or derived write enable strobes. This data and the snoop return data and the dirty tags corresponding to the snoop data from the other processing core are sufficient to determine the data for the merge write” (Chirca [0069])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of merge write operation in Chirca with the memory system in the combination of Rao and Chachad. The motivation for doing so would be to requires less writes as described by Chirca. “This is advantageous because the dirty tags or write enable strobes comprise less data to be stored in coherence write data queue than the data itself” (Chirca [0069])
Regarding Claim 8, Chirca further discloses wherein the second cache controller is further configured to, based on the snoop read and invalidate request returning the second set of data indicated as unmodified, cause the first set of data to be written.
“No merge operation is needed if the snoop response is Not Cached, Cached and Clean or Cached and Dirty where the same coherence write data and snoop data are dirty” (Chirca [0069] the write will just be the first set of data not merged with the second set)
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rao (published October 23, 2014) and Chachad (published July 26, 2012) as applied to claim 1 above, and further in view of Palacharla et al. (US 2016/0019157) (hereinafter Pala) (published January 21, 2016).
Regarding Claim 11, the combination of Rao and Chachad disclosed the device of claim 1, but does not explicitly state wherein the first cache memory and the second cache memory have different associativity.
Pala discloses wherein the first cache memory and the second cache memory have different associativity.
“FIG. 5 illustrates a component cache configuration table 500 that may be used by the system cache controller to manage the traits of the various component caches” (Pala [0072])
“The way group partition of a component cache may allow for customization of the associativity of the component cache, both statically and dynamically, at run time” (Pala [0078] the cache memories may be customized to have different associativity)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the memories having different associativity in Pala with the memory system in combination of Rao and Chachad. The motivation for doing so would be to for better efficiency of the cache by customizing to the type of workload.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rao (published October 23, 2014) and Chachad (published July 26, 2012) as applied to claim 1 above, and further in view of HAGERSTEN et al. (US 2019/0155732) (hereinafter Hagersten) (published May 23, 2019).
Regarding Claim 12, the combination of Rao and Chachad disclosed the device of claim 1, and Chachad further discloses second tag memory is configured to store a third set of tag data associated with the third set of cache entries.
“UMC 730 includes two sets of cache tags. The first set of cache tags are L2 tags 731. These are non-data part of cache lines 510, 520 and 530 illustrated in FIG. 5 for L2 cache 130. The second set of cache tags are shadow tags 732. As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730. Shadow tags 732 include at least the valid and dirty status of the corresponding cache lines in L1D cache 123” (Chachad [0050])
But does not explicitly state wherein: the first cache subsystem includes a set of buffers configured to store a third set of cache entries for transfer to the second cache subsystem.
Hagersten and Chachad discloses wherein: the first cache subsystem includes a set of buffers configured to store a third set of cache entries for transfer to the second cache subsystem (the claim does not positively recite the transferring step and the limitation “for transfer to the second cache subsystem” is a statement of intended use, therefore does not limit the scope of the claim under BRI, and would not be considered)
“A computer system may utilize a victim buffer (VB) to quickly dispose of a victim from an L1 cache. The VB is a small and associative buffer for storing cache lines (with their address tags) on their way to be evicted” (Hagersten [0068])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of victim buffers in Hagersten with the system in the combination of Rao and Chachad. The motivation for doing so would be to allow for faster referencing of the cache line after it has been victimized and before removal from the cache as disclosed by Hagersten. “On certain read requests and external requests from the rest of the system, the address tags of the cache lines in the VB need to be searched for a match. In the case of a match, a read request may be satisfied by reading the corresponding cache line. The advantage of the VB is that the evicted cache line can be quickly removed from the L1 cache and the evicted cache line's former location in the L1 cache can be reused by the new cache line within a few cycles” (Hagersten [0068])
Claim(s) 13-17, 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chachad (published July 26, 2012) in view of Rao (published October 23, 2014) and Habusha (published October 11, 2012).
Regarding Claim 13, Chachad discloses a device comprising: a first cache subsystem having a first level, the first cache system comprising: a first memory associated with a first cache memory of a second cache subsystem, the first memory configured to store a first set of tag data associated with a first set of entries stored in a first cache memory of the second cache subsystem,
“The second set of cache tags are shadow tags 732. As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730. Shadow tags 732 include at least the valid and dirty status of the corresponding cache lines in L1D cache 123” (Chachad [0050] the first cache subsystem is the L2 level, the first memory is the shadow cache tag corresponding to the L1D tags for the first cache memory which would be L1D in the second cache subsystem of L1)
wherein the second cache subsystem has a second level different than the first level of the first cache subsystem, the first memory have the first level, and the first cache memory having the second level; (see 112 interpretation above)
“FIG. 7 is a further view of the digital signal processor system 100 of this invention. CPU 110 is bidirectionally connected to L1I cache 121 and L1D cache 123. L1I cache 121 and L1D cache 123 are shown together because they are at the same level in the memory hierarchy. These level one caches are bidirectionally connected to L2 130” (Chachad [0049] see fig. 7, the first cache subsystem is second level/L1, the second cache subsystem is first level/L2, the L1D cache is the first cache memory at the second level/L1)
“The second set of cache tags are shadow tags 732. As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730” (Chachad [0050] the shadow tags are in the first level/L2)
a cache controller coupled to the first memory and the second cache subsystem, the cache controller having the first level. (see 112 interpretation above)
“FIG. 7 illustrates further details of DMC 710 and UMC 730. DMC 710 includes L1D cache tags 711. These tags are the non-data part of cache lines 510, 520 and 530 illustrated in FIG. 5 for L1D cache 123. UMC 730 includes two sets of cache tags” (Chachad [0050] see fig. 7, UMC is connected to DMC and part of the first level/L1, the shadow tag memory in first level/L2, and L1 cache)
But does not explicitly state a second memory associated with a second cache memory of the second cache subsystem, the second memory configured to store a second set of tag data associated with a second set of entries stored in the second cache memory of the second cache subsystem, wherein the first cache memory has the second level and the second memory has the first level; and wherein the cache controller is configured to modify the first set of tag data and the second set of tag data based on a cache entry being evicted from the first cache memory and stored in the second cache memory.
Rao and Chachad discloses a second memory associated with a second cache memory of the second cache subsystem, the second memory configured to store a second set of tag data associated with a second set of entries stored in the second cache memory of the second cache subsystem, wherein the first cache memory has the second level and the second memory has the first level; and (see objection and 112 interpretation above)
“FIG. 1 illustrates a victim cache scheme implemented by a conventional processor. In the victim cache scheme, incoming blocks from memory 158 (or L2 cache 156 if present) are always loaded into the L1 cache 102 with one of the cache blocks in L1 102 being replaced and moved to the victim cache 104. The victim cache 104 in turn discards one of its blocks and moves it back to memory 158 (or L2 cache 156 if present)” (Rao [0006] the victim cache is the second cache memory and is part of the second level/L1)
“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM” (Chachad [0051] the shadow tags corresponding to victim cache would be the second memory that is part of first level/L2)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to integrate the victim cache architecture disclosed in Rao into the system described in Chachad. Furthermore, a person of ordinary skill in the art would find it obvious to incorporate this victim cache mechanism to augment the primary cache structure within the Chachad framework, effectively acting as a spill-over buffer for evicted cache lines. By utilizing the victim cache to hold lines displaced from the primary cache, the system can reduce conflict misses and improve the hit rate of the first-level memory subsystem. The integration of Rao’s victim cache into the Chachad system ensures that the shadow tag controller maintains visibility over these displaced lines, thereby preventing the unnecessary write-back or invalidation traffic that would otherwise occur if displaced lines were immediately evicted to the L2 level. The motivation for doing so would be to enhance overall system performance by mitigating the penalty of frequent cache evictions while simultaneously maintaining strict data integrity and coherence across the multi-level cache hierarchy.
Habusha, Rao, and Chachad discloses wherein the cache controller is configured to modify the first set of tag data and the second set of tag data based on a cache entry being evicted from the first cache memory and stored in the second cache memory.
“if data is to be evicted from a cache line that caches clean or valid data (e.g., caches data that is synchronization with the memory 134), eviction of the data from the cache line involves invalidating data currently cached in the evicted cache line by, for example, updating the tag information and/or valid information in the cache array 112. On the other hand, if data is to be evicted from a cache line that includes dirty data (e.g., includes data that is not synchronized with the memory 134), eviction of the data from the cache line involves (i) writing the evicted data from the cache line to the memory 134 (so that the memory 134 stores the most recent version of the data), and (ii) invalidating the evicted data in the cache line by, for example, updating tag information and/or valid information in the cache array 112” (Habusha [0029] indication of the eviction is provided for the updating of tag information which indicates where the data is)
“In the victim cache scheme, incoming blocks from memory 158 (or L2 cache 156 if present) are always loaded into the L1 cache 102 with one of the cache blocks in L1 102 being replaced and moved to the victim cache 104. The victim cache 104 in turn discards one of its blocks and moves it back to memory 158 (or L2 cache 156 if present)” (Rao [0006] a block is moved to victim cache)
“Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM” (Chachad [0051] to maintain coherence, tags corresponding to both the L1 cache and victim cache are both updated)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the updating of tag information in Habusha with the memory system in the combination of Rao and Chachad. The motivation for doing so would be for better efficiency in locating data when the tags associated with the data are up to date and contain relevant information.
Regarding Claim 14, Habusha further discloses wherein: the cache entry is a first cache entry; the cache controller is configured to receive, from the second cache subsystem, a request for data associated with a second cache entry to replace the first cache entry in the first cache memory; and the request for the data associated with the second cache entry includes an indication of the eviction of the first cache entry from the first cache memory.
“If the data requested in the read request is not presently stored in the cache array 112, the read request is a miss. In an embodiment, if the read request is a miss, the cache 108 evicts data from a selected cache line, reads the data requested in the read request from the memory 134, and caches the data in the selected cache line (e.g., from which data was evicted earlier)” (Habusha [0028] for a read miss when requesting data, it would include an indication of the cache entry to be evicted for space as the location to store the new data)
“if data is to be evicted from a cache line that caches clean or valid data (e.g., caches data that is synchronization with the memory 134), eviction of the data from the cache line involves invalidating data currently cached in the evicted cache line by, for example, updating the tag information and/or valid information in the cache array 112. On the other hand, if data is to be evicted from a cache line that includes dirty data (e.g., includes data that is not synchronized with the memory 134), eviction of the data from the cache line involves (i) writing the evicted data from the cache line to the memory 134 (so that the memory 134 stores the most recent version of the data), and (ii) invalidating the evicted data in the cache line by, for example, updating tag information and/or valid information in the cache array 112. Once the evicted data is invalidated in the cache line, new data is possibly written in the cache line (i.e., the evicted data is replaced by new data in the cache line)” (Habusha [0029] for the read miss, information about the evicted line and the new line is provided for the updating and inserting of tag information)
Regarding Claim 15, Chachad further discloses wherein the cache controller is configured to: receive a request to read data:
“During E1 phase 331, the conditions for the instructions are evaluated and operands are read for all instruction types. For load and store instructions, address generation is performed and address modifications are written to a register file” (Chachad [0027] determining type of instruction)
“During the E2 phase 332, for load instructions, the address is sent to memory” (Chachad [0028] for read instruction only address is sent)
determine whether the request corresponds to a hit or a miss in the first cache memory using the first memory; and
“To determine if a memory access is to data cached within cache 500 (a cache hit), cache 500 compares the address tags for all cache lines to the most significant bits of the memory location accessed. Upon a detecting a match, the position within the cache line along dimension 501 corresponds to the least significant bits of the address permitting identification of the data word accessed” (Chachad [0042])
“Shadow tags 732 include at least the valid and dirty status of the corresponding cache lines in L1D cache 123” (Chachad [0050])
based on the request corresponding to a hit in the first cache memory, provide a snoop request for the data to the first cache controller.
“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache” (Chachad [0051])
Regarding Claim 16, Rao and Chachad further discloses wherein: the first cache subsystem includes a third cache memory; and
“The purpose of the L1 cache 102 is to improve data access speed in cases where the CPU accesses the same data multiple times. The access time of the L1 cache 120 is always faster than the access time of system memory 158 or L2 cache 156” (Rao [0007] the l2 cache is the third cache memory)
“CPU 110 is bidirectionally connected to L1I cache 121 and L1D cache 123. L1I cache 121 and L1D cache 123 are shown together because they are at the same level in the memory hierarchy. These level one caches are bidirectionally connected to L2 130” (Chachad [0049] the l2 cache is the third cache memory)
the cache controller is further configured to, based on the request corresponding to a miss in the first cache memory: determine whether the request corresponds to a hit or a miss in the third cache memory; and
“In the event of a cache miss to level one instruction cache 121 or to level one data cache 123, the requested instruction or data is sought from level two unified cache 130” (Chachad [0015])
based on the request corresponding to a hit in the third cache memory, provide the data using the third cache memory.
“If the requested instruction or data is stored in level two unified cache 130, then it is supplied to the requesting level one cache for supply to central processing unit core 110” (Chachad [0015])
Regarding Claim 17, Chachad further discloses wherein the cache controller is configured to: receive a request to write a first set of data;
“During E1 phase 331, the conditions for the instructions are evaluated and operands are read for all instruction types. For load and store instructions, address generation is performed and address modifications are written to a register file” (Chachad [0027] determining type of instruction)
“For store instructions, the address and data are sent to memory” (Chachad [0028] for write instruction address and data is sent)
determine whether the request corresponds to a hit or a miss in the first cache memory using the first memory; and
“To determine if a memory access is to data cached within cache 500 (a cache hit), cache 500 compares the address tags for all cache lines to the most significant bits of the memory location accessed. Upon a detecting a match, the position within the cache line along dimension 501 corresponds to the least significant bits of the address permitting identification of the data word accessed” (Chachad [0042])
“Shadow tags 732 include at least the valid and dirty status of the corresponding cache lines in L1D cache 123” (Chachad [0050])
based on the request corresponding to a hit in the first cache memory, provide a snoop read and invalidate request to the first cache controller.
“DMC 710 uses shadow tags 732 to implement snoop read and write coherence. DMC 710 tracks the status of L1D cache lines. Shadow tags 732 are used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. Shadow tags 732 are updated on all L1D cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM” (Chachad [0051])
Regarding Claim 20, Chachad further discloses wherein the first set of tag data and the second set of tag data include address data and coherence data.
“Each of cache lines 510, 520 and 530 includes: respective address tags 511, 521 and 522; respective valid bits 512, 522 and 523; respective dirty bits 513, 523 and 533; respective least recently used (LRU) indicators 514, 524 and 534; and respective data words 515, 525 and 535” (Chachad [0040])
Regarding Claim 21, Rao and Chachad further discloses wherein: the first cache subsystem is a level-two (L2) cache subsystem; and the second cache subsystem is a level-one (L1) cache subsystem.
“In the victim cache scheme, incoming blocks from memory 158 (or L2 cache 156 if present) are always loaded into the L1 cache 102 with one of the cache blocks in L1 102 being replaced and moved to the victim cache 104. The victim cache 104 in turn discards one of its blocks and moves it back to memory 158 (or L2 cache 156 if present)” (Rao [0006] L1 cache subsystem has L1 cache and victim cache, L2 cache subsystem has L2 cache)
“The second set of cache tags are shadow tags 732. As shown by bus 715 shadow tags 732 generally correspond to L1D cache tags 711 except these are located in UMC 730. Shadow tags 732 include at least the valid and dirty status of the corresponding cache lines in L1D cache 123” (Chachad [0050] see fig. 7, cache 123 is in the L1 level and the shadow tags 732 which corresponds to cache 123 is stored at the L2 level)
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chachad (published July 26, 2012), Rao (published October 23, 2014), and Habusha (published October 11, 2012) as applied to claim 17 above, and further in view of Chirca (published April 24, 2014).
Regarding Claim 18, the combination of Chachad, Rao, and Habusha disclosed the device of claim 17, but does not explicitly state wherein the cache controller is further configured to, based on the snoop read and invalidate request returning a second set of data indicated as modified: merge the first set of data and the second set of data to produce a merged set of data; and cause the merged set of data to be written.
Chirca discloses wherein the cache controller is further configured to, based on the snoop read and invalidate request returning a second set of data indicated as modified: merge the first set of data and the second set of data to produce a merged set of data; and cause the merged set of data to be written.
“If the snoop return is Cached and Dirty with different dirty data in the snoop return than in the coherence write, then comparator 802 triggers a merge write operation. This merge write operation includes only data dirty in the snoop response and clean in the coherence write. As noted above coherence write data queue may store only the corresponding dirty tags or derived write enable strobes. This data and the snoop return data and the dirty tags corresponding to the snoop data from the other processing core are sufficient to determine the data for the merge write” (Chirca [0069])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of merge write operation in Chirca with the memory system in the combination of Chachad, Rao, and Habusha. The motivation for doing so would be to requires less writes as described by Chirca. “This is advantageous because the dirty tags or write enable strobes comprise less data to be stored in coherence write data queue than the data itself” (Chirca [0069])
Regarding Claim 19, Chirca further discloses wherein the cache controller is further configured to, based on the snoop read and invalidate request returning the second set of data indicated as unmodified, cause the first set of data to be written.
“No merge operation is needed if the snoop response is Not Cached, Cached and Clean or Cached and Dirty where the same coherence write data and snoop data are dirty” (Chirca [0069] the write will just be the first set of data not merged with the second set)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Although examiner believes that the combination of Bali and Chachad discloses all the limitations of the claim 1, applicant points to Bali as only having one level, but the combination of Bali and Chachad would have two levels. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
However to further prosecution, Examiner now uses the prior art Rao in place of Bali, and Rao explicitly shows two levels of cache and the first level cache is on the same level as the victim cache to render any arguments with regards to only having one level moot. Chachad is combined with Rao for the disclosure of controllers and shadow cache tags being in the L2 cache.
Conclusion
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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