DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
First current source, second current source, first through sixth transistors required to be identified in detailed description of Fig. 3. Unless proper reference designation of the first through sixth transistors and the first and second current sources as referenced in the claim 1, 9 and 16 it is difficult to verify the connections properly represented in Fig 3 as claimed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 9 are rejected under 35 U.S.C. 102 as being anticipated by Sun et. al., (CN 113328710 A, published on 31 August 2021, a marked machine translation is relied upon).
Regarding claims 1 and 9, Sun teaches (Fig. 2, pages 4 & 5 of the machine translation) an amplifier circuit comprising:
a first transistor (M1) having a first terminal (drain) and a control terminal (gate);
a second transistor (M2) having a first terminal (drain) coupled to the first terminal (drain) of the first transistor (M1), and having a control terminal (gate);
a first current source (Ib) coupled to the first terminal (drain1) of the first transistor (M1), the first current source (Ib) including:
[AltContent: textbox (I2)][AltContent: arrow]
PNG
media_image1.png
278
656
media_image1.png
Greyscale
Fig. 2 of Li annotated by the examiner for ease of reference.
a second current source (I2);
a third transistor (M4) having a first terminal (drain) coupled to the first terminal (drain) of the first transistor (M1)2, having a second terminal (source) coupled to the second current source (I2), and having a control terminal (gate) coupled to the control terminal (gate) of the first transistor (M1, both gates are connected to RFP);
a fourth transistor (M5) having a first terminal (drain) coupled to the first terminal (drain) of the third transistor(M4), having a second terminal (source) coupled to the second current source (I2), and having a control terminal (gate) coupled to the control terminal (gate) of the second transistor (M2);
a fifth transistor (M7) having a first terminal (drain), having a second terminal (source) coupled to the second current source (I2), and having a control terminal (gate); and
a sixth transistor (M8) having a first terminal (drain) coupled to the first terminal (drain) of the fifth transistor (M7), having a second terminal (source) coupled to the second current source (I2), and having a control terminal (gate) coupled to the control terminal (gate) of the fifth transistor (M7).
wherein per claim 3, the second current source (I2) has a first terminal coupled to the third (M4), fourth(M5), fifth(M7), and sixth(M8) transistors and has a second terminal coupled to a reference voltage terminal (ground through R3); and
wherein per claim 4, the amplifier of Sun (Fig. 2) further comprising:
a first resistor (R3) having a first terminal (bottom terminal in Fig. 2) coupled to the control terminal (gate) of the first transistor (M1), and having a second terminal (top of the resistor R3, Fig. 2); and
a second resistor (R4) having a first terminal (bottom terminal in Fig. 2) coupled to the control terminal (gate) of the second transistor (M2), and a second terminal (top of the resistor R4, Fig. 2) coupled to the second terminal (top of resistor R3) of the first resistor (R3) and the control terminal of the fifth transistor (M7 through M6).
wherein further per claim 9, a voltage summing circuit (Vg2+VIM2, see equation 1 on page 6 of the machine translation of Sun) including:
a first resistor (R3) having a first terminal coupled to the control terminal (gate) of the first transistor (M1), and having a second terminal coupled to the control terminal of the fifth transistor (M7 through M6); and
a second resistor (R4) having a first terminal (bottom) coupled to the control terminal (gate) of the second transistor (M2), and having a second terminal coupled to the second terminal of the first resistor (R3, see Fig. 2 of Sun).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of commonly used current mirror circuits used for stable current sources in electronic circuits.
According to claim 12, Sun teaches all limitations of claim 9, a first current source (Ib) and second current source (I2) as claimed. However, Sun is not explicit about current mirrors used as current sources.
However, a person of ordinary skill in the art knows that the easiest way to implement a stable current source use to resort to current mirror circuits and therefore it would have been obvious to use a first and a second current mirror circuits of proper ratio to form the first and the second current sources of Sun.
Therefore, replacing current sources with current mirrors the resultant combination would teach a first current mirror circuit (to replace the first current source Ib) and a second current mirror circuit (to replace the second current source I2), in which:
The first current mirror circuit is coupled between the first transistor pair (M1 & M2) and the second current mirror circuit (I2 see Fig. 2 of Sun); and
the second current mirror circuit is coupled between the first current mirror () circuit and the differential pair (the amplifier circuit as shown in Fig. 2, where VDD is the head of the differential pair and the second current source, i.e., the second current mirror has be connected to VDD on the top and between the Ib and ground at the bottom).
Wherein per claim 13, the first current mirror circuit (Ib) configured to receive a first second-order intermodulation current (IM2) from the first transistor pair (M1 & M2), and source a second second-order intermodulation current (IM2) to the second current mirror circuit (I2); and
the second current mirror circuit (I2) is configured to sink (to ground through the resistor R3) a third second-order intermodulation current (part of the IM2) from the differential pair (the amplifier of Fig. 2).
Claim 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lamesch (US 2016/0198979 A1) in view of Sun.
PNG
media_image2.png
552
850
media_image2.png
Greyscale
Fig. 2 of Lamesch annotated by the examiner for ease of reference.
According to claim 16, Lamesch teaches
A receiver circuit (inductive respiration sensor, 10 of Fig. 1) comprising:
a band pass filter (BPF, 44);
an analog-to-digital converter (ADC, the digital signal processor 24 has an ADC to convert the analog output of the amplifier into digital signal format, The mixed signal is fed to low-pass filter 44, which removes high-frequency components and passes the resulting DC voltage through amplifier 46 to the ADC input 23 of microcontroller 24, 0026); and
an amplifier (46) coupled between the BPF (44) and the ADC (24).
The amplifier (46) is not well defined Lamesch other than it is a differential amplifier). Sun teaches all limitations of the amplifier in Fig. 2 (please see above in regards to the rejection of claims 1 and 9).
A person of ordinary skill in the art would find it obvious before the effective filing of the current invention to replace the differential pair of Lamesch by the linear and efficient amplifier of Sun to improve the signal clarity and efficiency of the Lamesch sensor using Sun’s differential pair and thereby the combination teaches all limitations of claim 16.
Wherein per claim 17, Sun also teaches a voltage summing circuit (Vg2+VIM2, see equation 1 on page 6 of the machine translation of Sun) including:
a first resistor (R3) having a first terminal coupled to the control terminal (gate) of the first transistor (M1), and having a second terminal coupled to the control terminal of the fifth transistor (M7 through M6); and
a second resistor (R4) having a first terminal (bottom) coupled to the control terminal (gate) of the second transistor (M2), and having a second terminal coupled to the second terminal of the first resistor (R3, see Fig. 2 of Sun).
the first current mirror circuit (Ib) configured to receive a first second-order intermodulation current (IM2) from the first transistor pair (M1 & M2), and source a second second-order intermodulation current (IM2) to the second current mirror circuit (I2); and
the second current mirror circuit (I2) is configured to sink (to ground through the resistor R3) a third second-order intermodulation current (part of the IM2) from the differential pair (the amplifier of Fig. 2).
Allowable Subject Matter
Claims 2, 5-8, 10-11, 14-15, 18-20 are objected to as being dependent upon a rejected base claim 1 but would be allowable if rewritten in independent form including all of the limitations of the base claim 1 and any intervening claims.
Claims 2 and 10 are allowable because Sun doesn’t teach all first through sixth transistors as n-channel FETs as claimed. Claim 11 is allowable because Sun is not explicit about the third through sixth transistors being scaled replicas of the first and second FETs.
Claims 5 and 18 are allowable because the closest prior art of record, Sun doesn’t teach explicitly the seventh and eighth transistors forming the current mirror as claimed.
No bleed current source as claimed in 14 or a circuit capacitor as claimed in 15 are explicit in the differential amplifier circuit of the closest prior art of record Sun.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
1 Transistor M3 receives supply VDD through M1/M2 to act as a tail current source, hence the current source Ib effectively is connected to VDD which is the first terminal (i.e., the drain) of the first (M1) and second (M2) transistors.
2 VDD are connected to the drains of M1 and M4.