Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 31st, 2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-6 are objected to because of the following informalities:
Replace “…performing till one of…” to “…performing until one of…” in claims 1, 3, and 5.
Replace “…is exceeding….” to “exceeds” in claims 1, 3, and 5.
Replace “…switching the data model training to next…” to “…switching the data model to a next” in claims 1, 3, and 5.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Ma (“Heterogeneous CPU+GPU Stochastic Gradient Descent Algorithms”, 2020) in view of Wheatley (US 20240352839 A1).
Regarding claim 1,
Ma teaches [a] processor implemented method, comprising: initiating a data model training using a first hardware accelerator from among a plurality of heterogeneous hardware accelerators (Page 7 Section 5, “CPUs and GPUs perform concurrent asynchronous SGD algorithms– specialized for their specific architecture– on data assigned dynamically and adaptively at runtime based on the current execution state.”, Page 7 Section 5.1 of Ma, “The architecture of the heterogeneous CPU+GPU framework for deep learning is depicted in Figure 3. It consists of a series of asynchronous worker threads corresponding to each of the CPUs and GPUs in Figure 2, and a central coordinator. The worker assigned to a hardware component is in charge of managing the resources, e.g., cores, memory, threads, and operation of that component.”
Ma teaches training a deep learning model using a first hardware accelerator (CPU or GPU worker) from a set of heterogeneous accelerators.)
wherein the data model training is spread across a plurality of epochs (Page 5 Section 3, “SGD can be stopped either after a fixed number of iterations, i.e., epochs, or when there is no significant drop in the loss across iterations. In practice, due to the large data set size and number of iterations it takes to converge, each SGD iteration is performed only over a randomly selected batch of B training examples…”, Page 10 Section 5.2, “As such, the framework performs loss computation after each complete pass– or a given number of batches– over the training data.”
Ma teaches training and performing loss computation after each complete pass across multiple epochs.);
and iteratively performing till one of a) a maximum accuracy is achieved for the data model, and b) a final hardware accelerator in a sequence of the plurality of heterogeneous hardware accelerators has reached (Page 5 Section 3, “SGD can be stopped either after a fixed number of iterations, i.e., epochs, or when there is no significant drop in the loss across iterations."
Ma teaches that the model is iteratively performed until the loss is minimized, meaning that the accuracy is at its maximum level.):
measuring accuracy of the data model after each of the plurality of epochs (Page 5 Section 3, “SGD can be stopped either after a fixed number of iterations, i.e., epochs, or when there is no significant drop in the loss across iterations.", Page 10 Section 5.2, “As such, the framework performs loss computation after each complete pass– or a given number of batches– over the training data. The loss is computed with a DNN forward pass over the training– or test– data… The size of the batch is proportional to the worker speed… Each worker computes a partial loss on its data batch and then sends it back to the coordinator, which aggregates it into the overall loss. This strategy is optimized for execution time by prioritizing the fast workers and minimizing the coordinator overhead.”
The loss is measured after each epoch and the SGD is stopped once there is minimal change in the loss across epochs, meaning that the accuracy has reached its highest point.);
determining if difference between the accuracy of the data model measured in two consecutive epochs of the plurality of epochs is exceeding a threshold of accuracy (Page 5 Section 3, “SGD can be stopped either after a fixed number of iterations, i.e., epochs, or when there is no significant drop in the loss across iterations.");
if the difference between the accuracy of the data model measured in two consecutive epochs of the plurality of epochs is exceeding the threshold of accuracy (Page 5 Section 3, “SGD can be stopped either after a fixed number of iterations, i.e., epochs, or when there is no significant drop in the loss across iterations.")
Ma does not teach and switching the data model training to next hardware accelerator in the sequence of the plurality of heterogeneous hardware accelerators, if the difference between the accuracy of the data model measured in two consecutive epochs of the plurality of epochs is exceeding the threshold of accuracy.
Wheatley, in the same field of endeavor, teaches and switching the data model training to next hardware accelerator in the sequence of the plurality of… hardware accelerators (Paragraph 184, “As an example, a convolution neural network system (CNNS) can be implemented using one or more platforms… The GAFFE framework includes models and optimization defined by configuration where switching between CPU and GPU setting can be achieved via a single flag to train on a GPU machine then deploy to clusters.”)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Ma’s teaching of learning data model training across heterogeneous CPU and GPU accelerators with Wheatley’s teaching of switching processors during training in a neural network in order to enhance training efficiency and resource utilization (Paragraph 156 of Wheatley).
Regarding claim 3,
Ma teaches [a] system, comprising: one or more hardware processors; a communication interface; and a memory storing a plurality of instructions, wherein the plurality of instructions when executed, cause the one or more hardware processors to (Page 7 Section 5.1 of Ma, “The architecture of the heterogeneous CPU+GPU framework for deep learning is depicted in Figure 3. It consists of a series of asynchronous worker threads corresponding to each of the CPUs and GPUs in Figure2, and a central coordinator… The coordinator and workers are implemented as stand-alone system threads that exist over the entire duration of the program. The worker assigned to a hardware component is in charge of managing the resources, e.g., cores, memory, threads, and operation of that component. The coordinator assigns data and tasks to workers, and schedules their interaction. The communication between the coordinator and workers– workers do not communicate directly– is realized through control messages, while data are passed through references in the shared memory space.”):
The remainder of claim 3 recites identical limitations to claim 1. Therefore, the claim is rejected using the same rationale as claim 1.
Regarding claim 5,
Ma teaches [o]ne or more non-transitory machine-readable information storage mediums comprising one or more instructions which when executed by one or more hardware processors cause (Page 13 Section 7.1, “We implement the heterogeneous CPU+GPU framework for deep learning in C/C++ using the pthreads library. The coordinator and each worker is managed by a stand-alone thread. The threads communicate using our custom asynchronous message queue.”):
The remainder of claim 5 recites identical limitations to claim 1. Therefore, the claim is rejected using the same rationale as claim 1.
Claims 2, 4, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Ma (“Heterogeneous CPU+GPU Stochastic Gradient Descent Algorithms”, 2020) in view of Wheatley (US 20240352839 A1) and Kang (“Scheduling of Deep Learning Applications Onto Heterogeneous Processors in an Embedded Device”, 2020).
Regarding claim 2,
Ma does not teach the plurality of hardware accelerators in the sequence of the plurality of heterogeneous hardware accelerators are arranged in increasing order of specification.
Kang, in the same field of endeavor, teaches the plurality of hardware accelerators in the sequence of the plurality of heterogeneous hardware accelerators are arranged in increasing order of specification (Page 4 Section 3, “Galaxy S9 is a heterogeneous system that consists of a Mali-G72 MP18 GPU and big.LITTLE CPUs with a quad-core M3 CPU running at 2.7GHz and a quad-core Cortex-A55 CPU at 1.79GHz.”, Page 7 Section 5, “Let L={L1,L2, ...,Ln} be a set of layers, or tasks, in a DL application sorted in the topology order, and PE={PE1, PE2,..., PEm} be a set of logical PEs in the device…” See Figure 1,
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Kang teaches heterogeneous processors (CPU, GPU, NPU) with their specifications and the CPUS are arranged by increasing specification. P1, P2, P3, P4 represents a sequence of hardware accelerators. The scheduler determines which PE to proceed first which can start off with the worst accelerator to the best performing one according to the specification.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Ma’s teaching of learning data model training across heterogeneous CPU and GPU accelerators with Kang’s teaching of switching neural network computation across heterogeneous processors in order to enhance training efficiency and resource utilization (Introduction of Kang).
Claim 4 recites identical limitations to claim 2. Therefore, claim 4 is rejected using the same rationale as claim 2.
Claim 6 recites identical limitations to claim 2. Therefore, claim 6 is rejected using the same rationale as claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAJD MAHER HADDAD whose telephone number is (571)272-2265. The examiner can normally be reached Mon-Friday 8-5 pm.
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/M.M.H./Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125