DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
The Amendment filed January 30, 2026 has been entered. Claim 13 has been cancelled. Claims 9, 14-15, 18, and 25-26 have been amended. Claim 28 has been added. Claims 1-12, and 14-28 remain pending in the application. Applicant’s amendments have overcome the 112(b) rejection previously set forth in the Non-Final Office Action mailed 07/03/2025.
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
5. Claims 1-8, 19, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Guilbert U.S. Patent Application Publication 20060159292 in view of Magrath U.S. Patent Application Publication 20080024213; previously cited.
Regarding claim 1, Guilbert teaches an apparatus (H-Bridge circuit configurations 200, Fig. 3, par [0025], see Fig. 3, and respective portions of the specification, see Guilbert) comprising:
a first power stage circuit (including see transistors 241-242, left side Fig. 3, par [0025], see Guilbert) having a first output (output between transistors 241-242) and a first power terminal (left side Vdd--, see Fig. 3, par [0025], see Guilbert);
a second power stage circuit including see transistors 243-244, right side Fig. 3, par [0025], see Guilbert) having a second output (output between transistors 243-244) and a second power terminal (right side Vdd--, see Fig. 3, par [0025], see Guilbert); and
a control circuit having a control input (including input of common mode voltage VCM+, VCM-, at input of selection devices 230, 231, 230, 231, 232, 233, Fig. 3 (corresponds to control circuit), par [0027], see Guilbert), a first control output (see output of V--CM+ and selection device 230, Fig. 3), and a second control output (output of V--CM- and selection device 231, Fig. 3), the control input coupled to the first and second power terminals (left side Vdd--, right side Vdd--, Fig. 3), the first control output (see output of V--CM+ and selection device 230, Fig. 3) coupled to the first output (output between transistors 241-242), and the second control output (output of V--CM- and selection device 231, Fig. 3) coupled to the second output (output between transistors 243-244, see Fig. 3, par [0025], see Guilbert).
Guilbert further teaches when a solid state switching device is used, the switching method may operate as quickly as the solid state device allows, or may operate or couple the amplifier stages at a slower rate (ramp) to control the coupling speed (par [0022], see Guilbert). For example, a CMOS pass gate device may be used to implement each switch, or a transistor device operating in a linear or ramp mode may be used (par [0028], see Guilbert).
However, Guilbert does not explicitly disclose the control circuit configured to, responsive to a first voltage at the first and second power terminals being below a threshold voltage, set the first output to a second voltage and the second output to a third voltage.
Magrath teaches amplifier circuits, methods of starting and stopping amplifier circuits (see Title) in which the switches SW1 and SW2 are closed by a control circuit (not shown) (Fig. 3, par [0064], see Magrath). Referring Figs. 6, 7, the control circuit 604 also generates control signals EN and FAST to control the operation of the PWM amplifier 100 and driver 110 in particular, although these outputs are not shown on FIG. 6 to avoid clutter (Fig. 6, par [0082], see Magrath). Phase 1, initially the output stage of the amplifier is disabled (signal `EN` is low), including for example the op-amp OP1 and the output devices Q1, Q2 (par [0084], Figs. 6, 7, see Magrath). When start-up is desired, switch SW1 is closed and the output V1 (corresponds to second voltage)ramps up at a rate determined by the dominant RC time constant formed by R1 and Cdc. At time t1, comparator 606 detects that the output voltage V1 exceeds the reference voltage Vmid, so control circuit 604 opens switch SW1. Op-amp OP1 is then enabled. It should be recalled that Vmid is the ground reference level for the input stage and so, assuming the audio input signal is muted on start-up, Vin=V1=Vmid. Therefore, so long as the output devices Q1, Q2 remain disabled (high-impedance) and bypass switch SW5 remains closed, op-amp OP1 acts simply as a buffer, keeping its virtual earth at Vmid, so the output of the overall amplifier will remain substantially at a voltage of Vmid (par [0085]). Next, after a short delay to allow the op-amp and other elements of circuit 100 to settle, signal `EN` goes high and the output devices Q1, Q2 are enabled. The switch SW5 is opened also at this time, enabling the integrator portion of OP1. In accordance with the signal voltage Vin=Vmid at this point in the start-up sequence, the PWM duty cycle will not be 50%, representing an output voltage of PVdd/2, but rather some other percentage appropriate to represent Vmid on a scale of 0 to PVdd (corresponds to threshold voltage). For example, if PVdd=12 volts and AVdd=3.3 volts, a duty cycle of 13.75% will apply (3.3/2=1.65V and 1.65/12.0=0.1375) (par [0087]). After this has happened, the first phase of the novel start-up sequence is complete, as seen where the output voltage V1 (corresponds to second voltage) reaches an intermediate plateau in the trace of FIG. 7 (par [0088]). In phase 2, To begin the second phase of start-up, switches SW3 and SW4 are closed and the voltage Vy (corresponds to third voltage) in the offset circuit 602 increases to PVdd/2 due to the RC time constant. Note that the current mirror output is actually only capable of sinking current. Initially Vy starts at 0V, while the current mirror input has a reference voltage of Vmid, so Ioff will be zero until Vy > Vmid. This is shown in FIG. 7 as the period between t1 and t2, with Vy represented (schematically and not to scale) in broken line. Once Vy surpasses Vmid, the offset current then increases, resulting in an increase in the DC voltage of the PWM output signal V1 too. The signal will continue increasing until it reaches PVdd/2 (par [0089]). There is no sudden transition in output voltage between some pre-charge voltage and the quiescent output voltage, which even if nominally the same would in practice differ because of mismatches of components in manufacture. The ramping of the offset current, which is enabled with SW3, masks any mismatch in current sources or resistors (par [0091], Figs. 6, 7, see Magrath).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the amplifier circuits, methods of starting and stopping amplifier circuits taught by Magrath with the apparatus of Guilbert such that to have obtained the control circuit configured to, responsive to a first voltage at the first and second power terminals being below a threshold voltage, set the first output to a second voltage and the second output to a third voltage as claimed for purpose of controlling the start-up of such amplifiers while minimizing transients as suggested by Magrath in paragraph [0001].
Regarding claim 2, Guilbert in view of Magrath teaches the apparatus of claim 1. Guilbert in view of Magrath, as modified, teaches wherein the control circuit includes:
a first transistor (transistor 242, see Fig. 3, par [0028], see Guilbert) coupled between the first control output (election device 232) and a first voltage terminal (ground terminal at transistor 242, see Fig. 3, par [0028], see Guilbert); and
a second transistor (transistor 244, see Fig. 3, par [0028], see Guilbert) coupled between the second control output (election device 233) and a second voltage terminal (ground terminal at transistor 244, see Fig. 3, par [0028], see Guilbert),
wherein the control circuit (including common mode voltage VCM+, VCM-, selection devices 230, 231, 232, 233, Fig. 3, par [0027], see Guilbert) is configured to enable the first and second transistors responsive to the first voltage being below the threshold voltage (When a solid state switching device is used, the switching method may operate as quickly as the solid state device allows, or may operate or couple the amplifier stages at a slower rate (ramp) to control the coupling speed, par [0022], see Guilbert); (see also switches SW1 and SW2 are closed by a control circuit (not shown) (Fig. 3, par [0064], see Magrath), the control circuit 604, (Fig. 6, par [0082], see Magrath), PVdd, V1, Vy, Figs. 6, 7, pars [0087-0089], see Magrath as presented in independent claim 1).
Regarding claim 3, Guilbert in view of Magrath teaches the apparatus of claim 2. Guilbert in view of Magrath, as modified, teaches wherein each of the first and second voltage terminals is a ground terminal (see ground terminal at transistors 242, 244, Fig. 3, par [0025], see Guilbert).
Regarding claim 4, Guilbert in view of Magrath teaches the apparatus of claim 2. Guilbert in view of Magrath, as modified, teaches wherein the first voltage terminal is coupled to first voltage source configured to a first direct current (DC) voltage, and the second voltage terminal is coupled to a second voltage source configured to provide a second DC voltage (see Vdd on left side and right side in Fig. 3 of Guilbert).
Regarding claim 5, Guilbert in view of Magrath teaches the apparatus of claim 4. Guilbert in view of Magrath, as modified, teaches wherein the first and second DC voltages are substantially same (the selection devices 210-213, 220-223 may also be used to place the MOS transistors 241-244, 245-248 in a high impedance state, for example to reduce power consumption, by coupling the MOS transistor 241-244, 245-248 gates to a pre-selected voltage or bias source (such as connecting to V.sub.dd or to ground), Fig. 3, par [0025], see Guilbert).
Regarding claim 6, Guilbert in view of Magrath teaches the apparatus of claim 4. Guilbert in view of Magrath, as modified, teaches the selection devices 210-213, 220-223 may also be used to place the MOS transistors 241-244, 245-248 in a high impedance state, for example to reduce power consumption, by coupling the MOS transistor 241-244, 245-248 gates to a pre-selected voltage or bias source (such as connecting to V.sub.dd or to ground), Fig. 3, par [0025], see Guilbert.
However, Guilbert in view of Magrath does not explicitly disclose wherein the first and second DC voltages are different DC voltages.
It would have been obvious to one of ordinary skill in the art at the time the invention was made, in the absence of new or unexpected results, those of ordinary skill in the art when facing a design need of providing wherein the first and second DC voltages are different DC voltages would have recognized and would have been obvious to try to modify the apparatus of Guilbert in view of Magrath such that to have obtained wherein the first and second DC voltages are different DC voltages since there are a finite number of identified, predictable potential solutions (i.e., wherein the first and second DC voltages are the same, wherein the first and second DC voltages are different DC voltages) to the recognized need (i.e., modifying), and one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success. The motivation is for purpose of controlling the start-up of such amplifiers while minimizing transients as suggested by Magrath in paragraph [0001].
Regarding claim 7, Guilbert in view of Magrath teaches the apparatus of claim 2. Guilbert in view of Magrath, as modified, teaches wherein the first voltage terminal and the second voltage terminal are coupled to a voltage source, and the first and second voltages are a same voltage (the selection devices 210-213, 220-223 may also be used to place the MOS transistors 241-244, 245-248 in a high impedance state, for example to reduce power consumption, by coupling the MOS transistor 241-244, 245-248 gates to a pre-selected voltage or bias source (such as connecting to V.sub.dd or to ground), Fig. 3, par [0025], see Guilbert); (For example, if PVdd=12 volts, see Fig. 6, par [0087], see Magrath).
Regarding claim 8, Guilbert in view of Magrath teaches the apparatus of claim 1. Guilbert in view of Magrath, as modified, teaches wherein the control circuit includes a transistor coupled between the first and second control outputs, and the control circuit is configured to enable the transistor responsive to the first voltage being below the threshold voltage (The speaker and earphone select switches 140, 141 which may be implemented as a standard electromechanical switches or as a solid state switching devices such as CMOS transistors. When a solid state switching device is used, the switching method may operate as quickly as the solid state device allows, or may operate or couple the amplifier stages at a slower rate (ramp) to control the coupling speed, Fig. 2, par [0022], see Guilbert).
Regarding claim 19, Guilbert in view of Magrath teaches the apparatus of claim 1. Guilbert in view of Magrath, as modified, teaches wherein the first and second power stages and the control circuit are part of an integrated circuit (In one embodiment, a dedicated integrated circuit, an approximate reduction in the silicon die size of approximately 30 percent may be realized. The invention-may be used in many types of communication devices and audio devices, par [0007], see Guilbert).
Regarding claim 23, this claim merely reflects the method to the apparatus claim of Claim 1 and is therefore rejected for the same reasons.
Regarding claim 24, this claim has similar limitations as of Claim 3 and is therefore rejected for the same reasons.
6. Claims 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kaiho et al. U.S. Patent Application Publication 20070290726 (hereinafter, “Kaiho”) in view of Magrath U.S. Patent Application Publication 20080024213; previously cited.
Regarding claim 20, Kaiho teaches an apparatus (driving device 1, Fig. 1; FIG. 1 shows a driving device 1 configured as a switching amplifier, par [0074], see Fig. 1, and respective portions of the specification, see Kaiho) comprising:
a first power stage circuit (see left side of switching circuit 100, Fig. 1, par [0077], see Kaiho) having a first output (at OUTP, see Fig. 1) and a first power terminal (see ground terminal switching elements 102, Fig. 1, par [0077], see Kaiho);
a second power stage circuit (see right side of switching circuit 100, Fig. 1, par [0077], see Kaiho) having a second output (at OUTN, see Fig. 1) and a second power terminal (see ground terminal via switching elements 104, Fig. 1, par [0077], see Kaiho);
a capacitor (C1, Fig. 1, par [0077], see Kaiho) coupled between the first output (at OUTP of switching elements 101, 102, see Fig. 1) and a ground terminal (terminal 41 with grounding symbol of switching elements 104) via OUTN of switching elements 103, 104, see Fig. 1, pars [0077-0078], see Kaiho;
a speaker (201, Fig. 18; the mobile information terminal 200 has a speaker 201 such as a piezoelectric speaker as a capacitive load, the driving device 1 of FIG. 1 or the driving device 2 of FIG. 14 for driving the speaker, par [0172], see Kaiho) having a first speaker terminal (at Vcap1, Fig. 18, The driving device 1 or the driving device 2 outputs the output signal Vcap1 to the speaker 201 based on the input signal Vin, thereby supplying the speaker 201 with electric power, par [0172], see Kaiho) and a second speaker terminal (not shown, see speaker 201, Fig. 18), the first speaker terminal coupled to the first output (OUTP, see Fig. 1, par [0077], see Kaiho);
an inductor (L1, Fig. 22, see par [0016], see Kaiho) coupled between the second output (OUTN, see Fig. 1, par [0077], see Kaiho) and the second speaker terminal (not shown, see speaker 201, Fig. 18). The switching circuit 100 controls ON/OFF behavior of the switching elements 101, 102, 103, and 104 based on the switching control signals Vp1p, Vp1n, Vp2p, and Vp2n to control the power supply to the inductive load C1. An output signal Vcap1, which is a voltage across the terminals of the inductive load C1, is produced between the output terminals 50 and 51 that are provided at the connection points (OUTP, OUTN) between the terminal of the inductive load C1 and the first terminals 40 of the switching elements 101, 102, 103, and 104 (see Fig. 1, par [0079], see Kaiho) and
a control circuit (switching circuit 100, Fig. 1; the driving circuit 10 has a switching circuit 100, see Fig. 1, par [0077], see Kaiho) having a control input (at gate of switching elements 102, see Fig. 1, par [0077], see Kaiho), a first control output (at output Vp1n, see Fig. 1), and a second control output (at output Vp2n, see Fig. 1), the control input (at gate of switching elements 102, see Fig. 1) coupled to the first and second power terminals (ground terminal via switching elements 102, and 104, see Fig. 1), the first control output (Vp1n, see Fig. 1) coupled to the first output (OUTP, see Fig. 1), and the second control output put (Vp2n, see Fig. 1) coupled to the second output or the second speaker terminal (OUTN, see Fig. 1, par [0077], see Kaiho).
Kaiho further teaches the duration T2a of FIG. 8 is duration that Vcap10 transits from negative maximum level of amplitude to positive maximum level of amplitude (see par [0122], see Kaiho). In the transition duration T2a, when the absolute value of the amplitude of the first error suppression signal Vout1 outputted from the error suppression circuit 11 is large, as waveforms shown in the timing 2-a of FIG. 9 (see Figs. 8, 9, par [0123], see Kaiho).
However, Kaiho does not explicitly disclose the control circuit configured to, responsive to a first voltage at the first and second power terminals being below a threshold voltage, set the first output to a second voltage and the second output to a third voltage.
Magrath teaches amplifier circuits, methods of starting and stopping amplifier circuits (see Title) in which the switches SW1 and SW2 are closed by a control circuit (not shown) (Fig. 3, par [0064], see Magrath). Referring Figs. 6, 7, the control circuit 604 also generates control signals EN and FAST to control the operation of the PWM amplifier 100 and driver 110 in particular, although these outputs are not shown on FIG. 6 to avoid clutter (Fig. 6, par [0082], see Magrath). Phase 1, initially the output stage of the amplifier is disabled (signal `EN` is low), including for example the op-amp OP1 and the output devices Q1, Q2 (par [0084], Figs. 6, 7, see Magrath). When start-up is desired, switch SW1 is closed and the output V1 (corresponds to second voltage)ramps up at a rate determined by the dominant RC time constant formed by R1 and Cdc. At time t1, comparator 606 detects that the output voltage V1 exceeds the reference voltage Vmid, so control circuit 604 opens switch SW1. Op-amp OP1 is then enabled. It should be recalled that Vmid is the ground reference level for the input stage and so, assuming the audio input signal is muted on start-up, Vin=V1=Vmid. Therefore, so long as the output devices Q1, Q2 remain disabled (high-impedance) and bypass switch SW5 remains closed, op-amp OP1 acts simply as a buffer, keeping its virtual earth at Vmid, so the output of the overall amplifier will remain substantially at a voltage of Vmid (par [0085]). Next, after a short delay to allow the op-amp and other elements of circuit 100 to settle, signal `EN` goes high and the output devices Q1, Q2 are enabled. The switch SW5 is opened also at this time, enabling the integrator portion of OP1. In accordance with the signal voltage Vin=Vmid at this point in the start-up sequence, the PWM duty cycle will not be 50%, representing an output voltage of PVdd/2, but rather some other percentage appropriate to represent Vmid on a scale of 0 to PVdd (corresponds to threshold voltage). For example, if PVdd=12 volts and AVdd=3.3 volts, a duty cycle of 13.75% will apply (3.3/2=1.65V and 1.65/12.0=0.1375) (par [0087]). After this has happened, the first phase of the novel start-up sequence is complete, as seen where the output voltage V1 (corresponds to second voltage) reaches an intermediate plateau in the trace of FIG. 7 (par [0088]). In phase 2, To begin the second phase of start-up, switches SW3 and SW4 are closed and the voltage Vy (corresponds to third voltage) in the offset circuit 602 increases to PVdd/2 due to the RC time constant. Note that the current mirror output is actually only capable of sinking current. Initially Vy starts at 0V, while the current mirror input has a reference voltage of Vmid, so Ioff will be zero until Vy > Vmid. This is shown in FIG. 7 as the period between t1 and t2, with Vy represented (schematically and not to scale) in broken line. Once Vy surpasses Vmid, the offset current then increases, resulting in an increase in the DC voltage of the PWM output signal V1 too. The signal will continue increasing until it reaches PVdd/2 (par [0089]). There is no sudden transition in output voltage between some pre-charge voltage and the quiescent output voltage, which even if nominally the same would in practice differ because of mismatches of components in manufacture. The ramping of the offset current, which is enabled with SW3, masks any mismatch in current sources or resistors (par [0091], Figs. 6, 7, see Magrath).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the amplifier circuits, methods of starting and stopping amplifier circuits taught by Magrath with the apparatus of Kaiho such that to have obtained the control circuit configured to, responsive to a first voltage at the first and second power terminals being below a threshold voltage, set the first output to a second voltage and the second output to a third voltage for purpose of controlling the start-up of such amplifiers while minimizing transients as suggested by Magrath in paragraph [0001].
Regarding claim 21, Kaiho in view of Magrath teaches the apparatus of claim 20. Kaiho in view of Magrath, as modified, teaches wherein the control circuit (switching circuit 100, Fig. 1; the driving circuit 10 has a switching circuit 100, see Fig. 1, par [0077], see Kaiho) includes:
a first transistor (102, see Fig. 1, par [0078], see Kaiho) coupled between the first control output (Vp1n) and a first voltage terminal (ground terminal, see Fig. 1; Each of the switching elements 101, 102, 103, and 104 (each one is a transistor such as a MOSFET) has a first terminal 40 (the connection point OUTP or OUTN) connected to one output terminal 50 of the capacitive load C1, a second terminal 41 connected to the power source (Vcc) or the ground terminal, and a third terminal 42 that one of the switching control signals Vp1p, Vp1n, Vp2p, and Vp2n is inputted, Fig. 1, par [0078], see Kaiho); and
a second transistor (104, see Fig. 1, par [0078], see Kaiho) coupled between the second control output (Vp2n) and a second voltage terminal (ground terminal, see Fig. 1; Each of the switching elements 101, 102, 103, and 104 (each one is a transistor such as a MOSFET) has a first terminal 40 (the connection point OUTP or OUTN) connected to one output terminal 50 of the capacitive load C1, a second terminal 41 connected to the power source (Vcc) or the ground terminal, and a third terminal 42 that one of the switching control signals Vp1p, Vp1n, Vp2p, and Vp2n is inputted, Fig. 1, par [0078], see Kaiho),
wherein the control circuit (switching circuit 100, Fig. 1; the driving circuit 10 has a switching circuit 100, see Fig. 1, par [0077], see Kaiho) is configured to enable the first and second transistors (The switching circuit 100 controls ON/OFF behavior of the switching elements 101, 102, 103, and 104 based on the switching control signals Vp1p, Vp1n, Vp2p, and Vp2n to control the power supply to the inductive load C1. An output signal Vcap1, which is a voltage across the terminals of the inductive load C1, is produced between the output terminals 50 and 51 that are provided at the connection points (OUTP, OUTN) between the terminal of the inductive load C1 and the first terminals 40 of the switching elements 101, 102, 103, and 104, Fig. 1, par [0079], see Kaiho) responsive to the first voltage being below the threshold voltage (The duration T2a of FIG. 8 is duration that Vcap10 transits from negative maximum level of amplitude to positive maximum level of amplitude, (see par [0122], see Kaiho), see also the control circuit 604, (Fig. 6, par [0082], see Magrath; PVdd, V1, Vy, Figs. 6, 7, pars [0087-0089], see Magrath as presented in independent claim 20).
Regarding claim 22, Kaiho in view of Magrath teaches the apparatus of claim 21. Kaiho in view of Magrath, as modified, teaches wherein each of the first and second voltage terminals is a ground terminal (see ground terminal in Fig. 1; a second terminal 41 connected to the power source (Vcc) or the ground terminal par [0078], see Kaiho).
7. Claims 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Magrath U.S. Patent Application Publication 20080024213 in view of Kanji et al. U.S. Patent Application Publication 20100013561 (hereinafter, “Kanji”); previously cited.
Regarding claim 25, Magrath teaches a method (amplifier circuits, methods of starting and stopping amplifier circuits (see Title); A method of starting an amplifier circuit having an input stage and an output stage, see claim 1; referring Figs. 6, 7 and respective portions of the specification, see Magrath) comprising:
receiving a first voltage (at V1, Initially the output stage of the amplifier is disabled (signal `EN` is low), including for example the op-amp OP1 and the output devices Q1, Q2. Switch SW2 is open but has been closed previously, so that the switching output V1 is at zero, Figs. 6, 7, par [0084], see Magrath) that ramps up at a first power terminal (see terminal at PVdd and SW1) of a power stage circuit (100, When start-up is desired, switch SW1 is closed and the output VI ramps up at a rate determined by the dominant RC time constant formed by R1 and Cdc, Figs. 6, 7, par [0085], see Magrath) coupled to a speaker (RL, see Fig. 6; the load RL tied between the two outputs, as shown in FIG. 8, par [0097]; applications of the amplifier include audio applications, as mentioned already. In such cases the load RL will be a loudspeaker or headphones, par [0104], see Magrath) and at a second power terminal (at output of offset compensation circuit 602; Initially switches SW3 and SW4 are open, effectively disabling the offset compensation circuit 602 meaning that the bias signal to compensate the offset current will be zero, par [0084], see Magrath) of a power supply circuit (PVdd, see PVdd at offset compensation circuit 602, Fig. 6, see Magrath);
responsive to the first voltage (V1) reaching a first threshold voltage (see plateau, Fig. 7; After this has happened, the first phase of the novel start-up sequence is complete, as seen where the output voltage V1 reaches an intermediate plateau in the trace of FIG. 7, par [0088], see Magrath), enabling a first voltage regulator (including switches SW1), of the power supply circuit (PVdd, see PVdd at SW1 in Fig. 6, par [0085], see Magrath) to provide a second voltage (VY, To begin the second phase of start-up, switches SW3 and SW4 are closed and the voltage Vy in the offset circuit 602 increases to PVdd/2 due to the RC time constant, par [0088], see Magrath) at a driver power terminal (at inverting input of op-amp OP1, [0084]) of a driver circuit (110) of the power stage circuit (100, The control circuit 604 also generates control signals EN and FAST to control the operation of the PWM amplifier 100 and driver 110 in particular, although these outputs are not shown on FIG. 6 to avoid clutter. Numerous other control signals and components associated with initialization of the circuit may ordinarily be provided around the main functional components illustrated here and may be generated by this control circuit, Fig. 6, par [0082], see Magrath); and
after enabling of the first voltage regulator (SW1), enabling a second voltage regulator (including offset compensation circuit 602 switch SW3 and SW4) of the power supply circuit (PVdd) to increase the second voltage by no more than a particular percentage of the second voltage (VY, In accordance with the signal voltage Vin=Vmid at this point in the start-up sequence, the PWM duty cycle will not be 50%, representing an output voltage of PVdd/2, but rather some other percentage appropriate to represent Vmid on a scale of 0 to PVdd. For example, if PVdd=12 volts and AVdd=3.3 volts, a duty cycle of 13.75% will apply (3.3/2=1.65V and 1.65/12.0=0.1375). par [0087], see Magrath) or at no more than a particular slew rate.
However, Magrath does not explicitly disclose in which the percentage or the slew rate is based on a pop noise level limit at the speaker.
Kanji et al. anti-pop circuits and methods for audio amplifiers using variable resistors (see Title) in which Since impulses from the ports cause the speakers to pop, which could damage the speaker or a human ear, it is desirable to reduce the pops, caused by the CODEC ports. Since power can be applied at different slew rates (i.e., dv/dt), and the internal ground is referenced to VDDA, which should be ramped up slowly to reduce pops due to DC shifts at the port, it may be difficult to determine when to turn on the amplifier. To add to the problem, the amplifiers driving the ports generally will not operate correctly until the VDDA power supply is large enough to allow the amplifier to close the loop. Turning the amplifier on too early or too late will generally cause an impulse to be applied to the port and transferred to the speaker, causing an unwanted pop (par [0064], see Kanji).
It would have been obvious to one of ordinary skill in the art at the time the invention was made, in the absence of new or unexpected results, those of ordinary skill in the art when facing a design need of providing in which the percentage or slew rate is based on a pop noise level limit at the speaker would have recognized and would have been obvious to try to modify the method of Kanji such that to have obtained in which the percentage or slew rate is based on a pop noise level limit at the speaker as claimed since there are a finite number of identified, predictable potential solutions (i.e., in which the percentage or slew rate is not based on a pop noise level limit at the speaker, in which the percentage or slew rate is based on a pop noise level limit at the speaker) to the recognized need (i.e., modifying), and one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success. The motivation is in order to prevent to damage the speaker or a human ear, as suggested by Kanji in paragraph [0064].
Regarding claim 26, Magrath in view of Kanji teaches the method of claim 25. Magrath in view of Kanji, as modified teaches wherein enabling the second voltage regulator includes enabling the second voltage regulator responsive to the second voltage exceeding a threshold voltage (surpass Vmid; To begin the second phase of start-up, switches SW3 and SW4 are closed and the voltage Vy in the offset circuit 602 increases to PVdd/2 due to the RC time constant. Note that the current mirror output is actually only capable of sinking current. Initially Vy starts at 0V, while the current mirror input has a reference voltage of Vmid, so Ioff will be zero until Vy > Vmid. This is shown in FIG. 7 as the period between t1 and t2, with Vy represented (schematically and not to scale) in broken line. Once Vy surpasses Vmid, the offset current then increases, resulting in an increase in the DC voltage of the PWM output signal V1 too. The signal will continue increasing until it reaches PVdd/2. see Fig. 7, par [0089], see Magrath).
Regarding claim 27, Magrath in view of Kanji teaches the method of claim 26. Magrath in view of Kanji, as modified teaches wherein enabling the second voltage regulator includes enabling the second voltage regulator after a delay time (i.e., the signal will continue increasing until it reaches PVdd/2) has elapsed from when the second voltage exceeds the second threshold voltage (To begin the second phase of start-up, switches SW3 and SW4 are closed and the voltage Vy in the offset circuit 602 increases to PVdd/2 due to the RC time constant. Note that the current mirror output is actually only capable of sinking current. Initially Vy starts at 0V, while the current mirror input has a reference voltage of Vmid, so Ioff will be zero until Vy > Vmid. This is shown in FIG. 7 as the period between t1 and t2, with Vy represented (schematically and not to scale) in broken line. Once Vy surpasses Vmid, the offset current then increases, resulting in an increase in the DC voltage of the PWM output signal V1 too. The signal will continue increasing until it reaches PVdd/2. see Fig. 7, par [0089], see Magrath).
Allowable Subject Matter
8. Claim 9 would be allowable.
Regarding Claims 10-12, these claims depends from Claim 9 therefore would be allowable.
9. Claim 28 would be allowable.
Regarding Claims 14-18, these claims depends from Claim 13 therefore would be allowable.
Response to Arguments
10. Applicant's arguments filed January 30, 2026 have been fully considered but they are not persuasive.
11. Applicant asserts on page 11, two-next-to last paragraph, regarding claim 1:
Claim 1 Claim 1 requires "a control circuit having a control input ... the control input coupled to the first and second power terminals" Guilbert, in combination with Magrath, does not show, teach, or suggest this limitation. The Examiner identifies VCM+, VCM-, and selection devices 230, 231, 232, and 233 from Fig. 3 of Guilbert as constituting a control circuit having a control input. VCM+, VCM-, and selection devices 230, 231, 232, and 233 do not have an identified control input coupled to the first and second power terminals as recited by Claim 1.
Additionally, in the fourth paragraph of page 5 of the office action dated 07/30/2025, the Examiner states that "the control input coupled to the first and second power terminals" is taught by Guilbert by "left side Vaa, right side Vaa, Fig. 3". No control input as recited by claim 1 is identified by the Examiner.
Examiner respectfully disagrees. As presented above in the Office Action Guilbert in view of Magrath teaches claim 1 in which from page 4 of the Office Action, Guilbert teaches “a control circuit having a control input (including input of common mode voltage VCM+, VCM-, at input of selection devices 230, 231, 230, 231, 232, 233, Fig. 3 (corresponds to control circuit), par [0027], see Guilbert), a first control output (see output of V--CM+ and selection device 230, Fig. 3), and a second control output (output of V--CM- and selection device 231, Fig. 3), the control input coupled to the first and second power terminals (left side Vdd--, right side Vdd--, Fig. 3. In other words VCM+, VCM-, coupled to power terminals via the circuit itself”.
12. Applicant asserts on page 11, last paragraph, regarding claim 1:
Furthermore, Guilbert in view of Magrath does not show, teach, or suggest "the control circuit configured to, responsive to a first voltage at the first and second power terminals being below a threshold voltage, set the first output to a second voltage and the second output to a third voltage" as recited by claim 1. Guilbert in view of Magrath does not teach the specific threshold-responsive control based on power terminal voltage monitoring as claimed in Claim 1.
Examiner respectfully disagrees. As presented above in the Office Action Guilbert in view of Magrath teaches claim 1 in which from page 6 of the Office Action, Guilbert in view of Magrath teaches the control response when PVdd/2 where PVdd corresponds to threshold voltage, see Fig. 7, thus PVdd/2 considered below threshold voltage (i.e., specific threshold-responsive): “In accordance with the signal voltage Vin=Vmid at this point in the start-up sequence, the PWM duty cycle will not be 50%, representing an output voltage of PVdd/2, but rather some other percentage appropriate to represent Vmid on a scale of 0 to PVdd (corresponds to threshold voltage). For example, if PVdd=12 volts and AVdd=3.3 volts, a duty cycle of 13.75% will apply (3.3/2=1.65V and 1.65/12.0=0.1375) (par [0087]). After this has happened, the first phase of the novel start-up sequence is complete, as seen where the output voltage V1 (corresponds to second voltage) reaches an intermediate plateau in the trace of FIG. 7 (par [0088]). In phase 2, To begin the second phase of start-up, switches SW3 and SW4 are closed and the voltage Vy (corresponds to third voltage) in the offset circuit 602 increases to PVdd/2 due to the RC time constant. Note that the current mirror output is actually only capable of sinking current. Initially Vy starts at 0V, while the current mirror input has a reference voltage of Vmid, so Ioff will be zero until Vy > Vmid. This is shown in FIG. 7 as the period between t1 and t2, with Vy represented (schematically and not to scale) in broken line. Once Vy surpasses Vmid, the offset current then increases, resulting in an increase in the DC voltage of the PWM output signal V1 too. The signal will continue increasing until it reaches PVdd/2 (par [0089])”, see Fig. 7 of Magrath.
13. Applicant asserts on page 13, second paragraph, regarding claim 20:
Thus, Kaiho teaches the capacitive load C1 coupled between output terminals 50 and 51 receiving the output signal Vcap1, and does not show, teach, or suggest "a capacitor coupled between the first output and a ground terminal" as recited by Claim 1
Examiner respectfully disagrees. As presented above in the Office Action, Kaiho in view of Magrath teaches claim 20 in which from page 12 of the Office Action, Kaiho teaches “a capacitor (C1, Fig. 1, par [0077], see Kaiho) coupled between the first output (at OUTP of switching elements 101, 102, see Fig. 1) and a ground terminal (see terminal 41 with grounding symbol of switching elements 104, Fig. 1) via OUTN of switching elements 103, 104, and see Fig. 1, pars [0077-0078], see Kaiho”.
14. Applicant asserts on page 14, last paragraph, regarding claim 20:
The inductor as presented in Kaiho is not configured as stated in claim 20. Fig. 22 of Kaiho shows an inductor with a first terminal connected to OUTP and a second terminal connected to OUTN. This inductor is configured as representing an inductive load, see Kaiho par [0006] and Kaiho par [0172]. Kaiho does not show that inductor as coupled between the second output (Kaiho's OUTN terminal) and the second speaker terminal.
Examiner respectfully disagrees. As presented above in the Office Action, Kaiho in view of Magrath teaches claim 20 in which from page 12, to page 13 of the Office Action Kaiho in view of Magrath teaches: “an inductor (L1, Fig. 22, see par [0016], see Kaiho) coupled between the second output (OUTN, see Fig. 1, par [0077], see Kaiho) and the second speaker terminal (not shown, see speaker 201, Fig. 18). The switching circuit 100 controls ON/OFF behavior of the switching elements 101, 102, 103, and 104 based on the switching control signals Vp1p, Vp1n, Vp2p, and Vp2n to control the power supply to the inductive load C1. An output signal Vcap1, which is a voltage across the terminals of the inductive load C1 (corresponds to an inductor), is produced between the output terminals 50 and 51 that are provided at the connection points (OUTP, OUTN) between the terminal of the inductive load C1 (corresponds to an inductor) and the first terminals 40 of the switching elements 101, 102, 103, and 104 (see Fig. 1, par [0079], see Kaiho); and
15. Applicant asserts on page 15, first paragraph, regarding claim 20:
Additionally, claim 20 requires "a first stage power circuit having a first output and a first power terminal." The Examiner identifies the ground terminal via switching elements 102, Fig. 1, par [0077] from Kaiho as a first power terminal. This is a ground terminal; not a power terminal as required by claim 20. Similarly, claim 20 requires "a second stage power circuit having a second output and a second power terminal." The Examiner similarly identifies the ground terminal via switching elements 104, Fig. 1, par [0077] from Kaiho as a second power terminal. This is also a ground terminal; not a power terminal as required by claim 20.
Examiner respectfully disagrees. As presented above in the Office Action, Kaiho in view of Magrath teaches claim 20 in which from page 11 to page 12 of the Office Action with a correction of typo regarding power terminal Kaiho in view of Magrath teaches: “a first power stage circuit (see left side of switching circuit 100, Fig. 1, par [0077], see Kaiho) having a first output (at OUTP, see Fig. 1) and a first power terminal (see power supply terminal Vcc, via switching element 101, Fig. 1, par [0077], see Kaiho);
a second power stage circuit (see right side of switching circuit 100, Fig. 1, par [0077], see Kaiho) having a second output (at OUTN, see Fig. 1) and a second power terminal (see power supply terminal Vcc, via switching element 104, Fig. 1, par [0077], see Kaiho)”.
16. Applicant asserts on 15, second paragraph, regarding claim 20:
However, neither Kaiho nor Magrath teach a control circuit claimed in claim 20. Specifically, there is no monitoring of the input voltage at the first and the second power terminals wherein the control circuit responds to the input voltage below a threshold voltage by setting different output voltages at the first and second output.
Examiner respectfully disagrees. As presented above in the Office Action, Kaiho in view of Magrath teaches claim 20 in which from page 14 to page 15 of the Office Action, Kaiho in view of Magrath teaches the control response when PVdd/2 where PVdd corresponds to threshold voltage, see Fig. 7, thus PVdd/2 considered below threshold voltage (i.e., specific threshold-responsive): “In accordance with the signal voltage Vin=Vmid at this point in the start-up sequence, the PWM duty cycle will not be 50%, representing an output voltage of PVdd/2, but rather some other percentage appropriate to represent Vmid on a scale of 0 to PVdd (corresponds to threshold voltage). For example, if PVdd=12 volts and AVdd=3.3 volts, a duty cycle of 13.75% will apply (3.3/2=1.65V and 1.65/12.0=0.1375) (par [0087]). After this has happened, the first phase of the novel start-up sequence is complete, as seen where the output voltage V1 (corresponds to second voltage) reaches an intermediate plateau in the trace of FIG. 7 (par [0088]). In phase 2, To begin the second phase of start-up, switches SW3 and SW4 are closed and the voltage Vy (corresponds to third voltage) in the offset circuit 602 increases to PVdd/2 due to the RC time constant. Note that the current mirror output is actually only capable of sinking current. Initially Vy starts at 0V, while the current mirror input has a reference voltage of Vmid, so Ioff will be zero until Vy > Vmid. This is shown in FIG. 7 as the period between t1 and t2, with Vy represented (schematically and not to scale) in broken line. Once Vy surpasses Vmid, the offset current then increases, resulting in an increase in the DC voltage of the PWM output signal V1 too. The signal will continue increasing until it reaches PVdd/2 (par [0089])”, see Fig. 7 of Magrath. The motivation is for purpose of controlling the start-up of such amplifiers while minimizing transients as suggested by Magrath in paragraph [0001].
17. Applicant asserts on 16, next-to-last paragraph, regarding claim 25:
As such, the combination of Magrath and Kanji fails to show, teach, or suggest the limitation of Claim 25 "enabling a second voltage regulator of the power supply circuit to increase the second voltage by no more than a particular percentage of the second voltage or at no more than a particular slew rate, in which the percentage or slew rate is based on a pop noise level limit at the speaker." As the references do not support the rejection of claim 25, the rejection should be withdrawn.
Examiner respectfully disagrees. As presented above of the Office Action, Magrath in view of Kanji teaches claim 25 in which from page 19 to page 21, Magrath teaches: “after enabling of the first voltage regulator (SW1), enabling a second voltage regulator (including offset compensation circuit 602 switch SW3 and SW4) of the power supply circuit (PVdd) to increase the second voltage by no more than a particular percentage of the second voltage (VY, In accordance with the signal voltage Vin=Vmid at this point in the start-up sequence, the PWM duty cycle will not be 50%, representing an output voltage of PVdd/2, but rather some other percentage appropriate to represent Vmid on a scale of 0 to PVdd. For example, if PVdd=12 volts and AVdd=3.3 volts, a duty cycle of 13.75% will apply (3.3/2=1.65V and 1.65/12.0=0.1375). par [0087], see Magrath) or at no more than a particular slew rate.
However, Magrath does not explicitly disclose in which the percentage or the slew rate is based on a pop noise level limit at the speaker.
Kanji et al. anti-pop circuits and methods for audio amplifiers using variable resistors (see Title) in which Since impulses from the ports cause the speakers to pop, which could damage the speaker or a human ear, it is desirable to reduce the pops, caused by the CODEC ports. Since power can be applied at different slew rates (i.e., dv/dt), and the internal ground is referenced to VDDA, which should be ramped up slowly to reduce pops due to DC shifts at the port, it may be difficult to determine when to turn on the amplifier. To add to the problem, the amplifiers driving the ports generally will not operate correctly until the VDDA power supply is large enough to allow the amplifier to close the loop. Turning the amplifier on too early or too late will generally cause an impulse to be applied to the port and transferred to the speaker, causing an unwanted pop (par [0064], see Kanji).
It would have been obvious to one of ordinary skill in the art at the time the invention was made, in the absence of new or unexpected results, those of ordinary skill in the art when facing a design need of providing in which the percentage or slew rate is based on a pop noise level limit at the speaker would have recognized and would have been obvious to try to modify the method of Kanji such that to have obtained in which the percentage or slew rate is based on a pop noise level limit at the speaker as claimed since there are a finite number of identified, predictable potential solutions (i.e., in which the percentage or slew rate is not based on a pop noise level limit at the speaker, in which the percentage or slew rate is based on a pop noise level limit at the speaker) to the recognized need (i.e., modifying), and one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success. The motivation is in order to prevent to damage the speaker or a human ear, as suggested by Kanji in paragraph [0064]”.
Conclusion
18. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.P.T/Examiner, Art Unit 2695
/VIVIAN C CHIN/Supervisory Patent Examiner, Art Unit 2695
