DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 20, 22-23, 25-28, 35, 38-39 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2019/0089396).
As to claim 20, Kim discloses a communication circuit (see at least figures 16-18), comprising: an antenna 440 (see figure 16) configured to receive and send a first-mode signal and a second-mode signal (see paragraphs [0037], [0040]); a baseband processing circuit 410 (see figure 16); and a shared radio frequency circuit 450 (see figure 16) coupled between the baseband processing circuit 410 and the antenna 440, wherein the shared radio frequency circuit 450 is configured to process the first-mode signal and the second-mode signal in a time-division manner (see paragraph [0054], lines 4-9), wherein: the shared radio frequency circuit 450 comprises a first control interface 1150 (see figures 17 and 18; paragraphs [0133], [0135]), the baseband processing circuit 410 comprises a second control interface 1130 (see figure 17; see also paragraphs [0066], [0069] which disclose “Information about a change in the transmission mode may be provided from the baseband modem 110 (refer to FIG. 1), a processor, etc.”) coupled to the first control interface 1150 via a control bus 1160 (see figure 17; paragraph [0122]), and the second control interface 1130 is adapted to configure the shared radio frequency circuit to process the first-mode signal and the second-mode signal in the time-division manner (see paragraph [0038] which discloses configuring a shared switch unit 123; see paragraph [0071] which discloses configuring a shared amplifier 126).
As to claim 22, Kim discloses that the shared radio frequency circuit 450 is configured to switch from processing the first-mode signal to processing the second-mode signal while operating in a running mode. See paragraphs [0037], [0038], [0054], [0066], [0133].
As to claim 23, Kim discloses that the shared radio frequency circuit is configured to continuously switch between processing the first-mode signal and processing the second-mode signal. See paragraph [0054] which discloses “The transmitter combo circuit 120a of an embodiment of the inventive concept may transmit, for example, wireless signals of different standards in a time-division manner by using the first switch 123a and the second switch 123b and the first impedance circuit 125a and the second impedance circuit 125b, which may be integrated into a chip”.
As to claim 25, Kim discloses that the shared radio frequency circuit 150 (see at least figure 1) comprises a switch chip 123 (see figure 0038]); the first control interface 1150 (see figure 17) comprises a first slave control interface 1150; the first slave control interface 1150 is disposed on the switch chip 123; and the switch chip 123 is adapted to configure a transmission path of the first-mode signal and the second-mode signal based on a control signal received by the first slave control interface 1150 (see paragraph [0038]).
As to claim 26, Kim discloses that the shared radio frequency circuit 150 (see at least figure 1) comprises a power amplifier chip 122 or 126 (see at least figure 6); the first control interface 1150 (see figure 17) comprises a second slave control interface 1150; the second slave control interface 1150 is disposed on the power amplifier chip 122 or 126; and the power amplifier chip 122 or 126 is configured to amplify the first-mode signal and the second-mode signal based on a control signal received by the second slave control interface 1150 (see paragraphs [0052], [0071], [0072]).
As to claim 27, Kim discloses that a frequency range of the first-mode signal is different from (see paragraph [0040] which discloses “For example, if there was an additional frequency bands there may be an antenna for the additional band”), and overlaps a frequency range of the second-mode signal (see paragraph [0039] which discloses “For example, WLAN and Bluetooth use similar radio frequency bands”).
As to claim 28, Kim discloses that a frequency range of the first-mode signal is different from (see paragraph [0040] which discloses “For example, if there was an additional frequency bands there may be an antenna for the additional band”), and overlaps a frequency range of the second-mode signal (see paragraph [0039] which discloses “For example, WLAN and Bluetooth use similar radio frequency bands”).
As to claim 35, Kim discloses that the first-mode signal is a cellular network signal; and the second-mode signal is a wireless local area network signal. See paragraphs [0039], [0131].
As to claim 38, it is rejected for similar reasons with respect to independent claim 20 as set forth above. Kim further discloses a memory 1120 (see figure 17), a processor 1110.
As to claim 39, it is rejected for similar reasons with respect to independent claim 20 as set forth above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 21, 34, 36 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
As to claim 21, Kim fails to disclose that the control bus 1160 (see figure 17) comprises a mobile industry processor interface (MIPI) control line or a general purpose input/output (GPIO) control line. The examiner takes Official Notice that such a mobile industry processor interface (MIPI) control line or a general purpose input/output (GPIO) control line is known in the art. Therefore, it would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to modify Kim as claimed, in order to yield predictable results such as high speed, and efficient communication protocol.
As to claim 34, Kim fails to disclose that the first-mode signal is a 5G signal; and the second-mode signal is a 4G signal. Those skilled in the art would recognize that these claimed limitations do not involve any inventive concept. They merely depend on arbitrary types of the first and second mode signals. In addition, the specification of the instant application fails to disclose any unexpected results obtained from the fact that the first-mode signal is a 5G signal; and the second-mode signal is a 4G signal. Therefore, it would have been obvious, before the effective filling date of the claimed invention, to one of ordinary skill in the art to modify Kim as claimed, in order to yield predictable results such as delivering significantly faster data speeds, lower latency.
As to claim 36, Kim discloses that the first-mode signal is a 4G signal or a 5G signal; and the second-mode signal is a Wi-Fi 6 signal or a Wi-Fi 5 signal. Those skilled in the art would recognize that these claimed limitations do not involve any inventive concept. They merely depend on arbitrary types of the first and second mode signals. In addition, the specification of the instant application fails to disclose any unexpected results obtained from the fact that the first-mode signal is a 4G signal or a 5G signal; and the second-mode signal is a Wi-Fi 6 signal or a Wi-Fi 5 signal. Therefore, it would have been obvious, before the effective filling date of the claimed invention, to one of ordinary skill in the art to modify Kim as claimed, in order to yield predictable results such as delivering significantly faster data speeds, lower latency.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Makoto (JP2003196228A).
As to claim 24, Kim discloses allocating priorities for using system resources of the electronic device 1100 to the application 1121, by one or more applications (e.g., 1121); but fails to disclose that a signal transmitted by the control bus comprises a control bit signifying a priority of processing the first-mode signal and the second-mode signal by the shared radio frequency circuit. Makoto discloses that a signal transmitted by a control bus comprises a control bit signifying a priority of processing a first-mode signal (from one transmitting device) and a second-mode signal (from another transmitting device) by a shared radio frequency circuit 20-3 or 20-4 (see figure 24). Therefore, it would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to provide the above teaching of Makoto to Kim, in order to yield predictable results such as increasing transmitting efficiency and reliability.
Allowable Subject Matter
Claims 29-33, 37 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 29-31, the prior art of record fail to anticipate, or render obvious, that the shared radio frequency circuit comprises an envelope tracking chip; the first control interface comprises a third slave control interface; the third slave control interface is disposed on the envelope tracking chip; and the envelope tracking chip is configured to supply, based on a control signal received by the third slave control interface, power to a power amplifier used for the first-mode signal and the second-mode signal.
As to claims 32-33, the prior art of record fail to anticipate, or render obvious, that the shared radio frequency circuit comprises a radio frequency transceiver chip; the first control interface comprises a level-1 slave control interface and a level-2 master control interface; the level-1 slave control interface and the level-2 master control interface are jointly disposed on the radio frequency transceiver chip; the radio frequency transceiver chip receives configuration of the baseband processing circuit through the level-1 slave control interface; and the radio frequency transceiver chip configures a level-2 slave control interface through the level-2 master control interface.
As to claim 37, the prior art of record fail to anticipate, or render obvious, that the baseband processing circuit comprises a first baseband processing chip and a second baseband processing chip; the first control interface comprises a level-i slave control interface and a level-2 master control interface; the level-2 master control interface comprises a first master control interface and a second master control interface; the first master control interface is located on the first baseband processing chip; the second master control interface is located on the second baseband processing chip; and the first master control interface and the second master control interface are coupled to the slave control interface by using the control bus.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Khlat (US 2015/0303976) discloses RF front-end circuitry comprising a control bus.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN THANH VO whose telephone number is (571)272-7901. The examiner can normally be reached Mon-Fri 8-5.
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/NGUYEN T VO/ Primary Examiner, Art Unit 2646