Office Action Predictor
Application No. 18/362,424

POWER AMPLIFIER MODULE

Non-Final OA §102
Filed
Jul 31, 2023
Examiner
CHOE, HENRY
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., LTD.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
61%
With Interview

Examiner Intelligence

93%
Career Allow Rate
1238 granted / 1336 resolved
Without
With
+-32.0%
Interview Lift
avg trend
2y 1m
Avg Prosecution
32 pending
1368
Total Applications
career history

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
37.3%
-2.7% vs TC avg
§102
47.2%
+7.2% vs TC avg
§112
3.8%
-36.2% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-3 and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by [Otsuki et al (Fig. 3); 2016/0204743]. Regarding claim 1, Otsuki et al discloses an amplifier circuit comprising a carrier circuit (5, 6) comprising at least one carrier amplifier (5), a peak circuit (10, 11) comprising at least one peak amplifier (10), a carrier control circuit (23) which is configured to control a gate voltage of a given carrier amplifier (5) of the carrier circuit (5, 6), and a carrier output circuit (22) which is connected to the carrier amplifier (5) of the carrier circuit (5, 6) at an output side of the carrier circuit (5, 6) and that is configured to supply a carrier control signal (output signal of 22) to the carrier control circuit (23) and wherein the carrier control signal (output signal of 22) is configured to control the gate voltage of the given carrier amplifier (5). Regarding claim 2, wherein the carrier output circuit (22) is configured to output the carrier control signal (output signal of 22) based on a gate current of the carrier amplifier (5) at the output side of the carrier circuit (5, 6), and wherein the carrier control circuit (23) is configured to control the gate voltage of the given carrier amplifier (5) based on the carrier control signal (output signal of 22). Regarding claim 3, wherein the carrier control circuit (23) is configured to decrease a bias supplied to a gate of the given carrier amplifier (5) based on the carrier control signal (output signal of 22). Regarding claim 10, Otsuki et al further comprising a phase shifter (7) which is configured to vary a phase of a signal output (output signal of 6) from the carrier circuit (5, 6), and a combiner (12) configured to combine the signal output (output signal of 6) from the carrier circuit (5, 6) with a signal (output signal of 11) from the peak circuit (10, 11) and to output a combined signal (the signal going out of the node 12) and the signal output (output signal of 6) from the carrier circuit (5, 6) having a phase that is varied by the phase shifter (7) and wherein the carrier output circuit (22) is configured to supply the carrier control signal (output signal of 22) to the carrier control circuit (23) based on a frequency (frequency of the signal going out of the node 12) of the combined signal (the signal going out of the node 12). Allowable Subject Matter Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (703)774-4614. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HENRY CHOE/ Primary Examiner, Art Unit 2843 #2934
Read full office action

Prosecution Timeline

Jul 31, 2023
Application Filed
Dec 10, 2025
Non-Final Rejection — §102
Mar 16, 2026
Applicant Interview (Telephonic)
Mar 30, 2026
Response Filed
Apr 08, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology. Study what changed to get past this examiner.

Patent 12597890
OVER TEMPERATURE PROTECTION OF LDO CONTROLLING THE RF POWER AMPLIFIER COLLECTOR VOLTAGE
2y 5m to grant Granted Apr 07, 2026
Patent 12597893
SEMICONDUCTOR INTEGRATED CIRCUIT AND RADIO-FREQUENCY MODULE
2y 5m to grant Granted Apr 07, 2026
Patent 12597888
ADAPTIVE STABILIZATION AND/OR PERFORMANCE OPTIMIZATION OF POWER AMPLIFIERS
2y 5m to grant Granted Apr 07, 2026
Patent 12580545
DIFFERENTIAL AMPLIFICATION CIRCUIT
2y 5m to grant Granted Mar 17, 2026
Patent 12580537
SATURATION DETECTION BANDWIDTH ENHANCEMENT USING VIRTUAL GROUNDS
2y 5m to grant Granted Mar 17, 2026

AI Strategy Recommendation

Click below to generate an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
61%
With Interview (-32.0%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1336 resolved cases by this examiner