Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 11, 12, 15, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yaohui Hu (US 2016/0147556), hereinafter referred to as Hu.
Regarding claim 1, Hu discloses:
A method comprising: running, by a host computer system, a hypervisor managing a first virtual machine, wherein the first virtual machine manages a second virtual machine (see e.g., para. [0003]: “Nested virtualization enables a bare-metal hypervisor (level-0 or L0) to run one or more hypervisors (level-1 or L1), each of which can run its own set of VMs [18, 7, 29, 13] (level-2 or L2).”);
For clarity of the record, the Examiner would like to point to paragraph [0032] of the Specification, which recites “In nested virtualization, a virtual device may be created and implemented by a nested hypervisor (e.g., the Level 1 hypervisor, a level 2 hypervisor, etc.) and exposed to a VM (e.g., a Level 2 VM, a level 3 VM running on a Level 2 hypervisor, etc.) as a pass-through device.” Thus, a level 2 or level 3 VM require hypervisors one level above them to function. Running a hypervisor comprises creating VMs beneath them, thus we can maintain that running Level 1 and 2 hypervisors precludes the possibility of running Level 2 and 3 VMs on their respective hypervisor.
receiving, by the hypervisor, from a virtual device, a first request to perform a memory access operation with respect to a memory page of the second virtual machine (see e.g., para. [0028]: “and executing a virtual machine which relies on the at least two concurrently available hypervisors to interface with the physical host system, the virtual machine having a memory map which has portions accessible by each of the at least two hypervisors” and e.g., para. [0038]: “A single hypervisor controlling a virtual central processing unit of the virtual machine may be selected for relaying input/output requests generated from the virtual machine on at least one other virtual central processing unit controlled by another hypervisor.”);
responsive to determining, by the hypervisor, that the memory page of the second virtual machine is unavailable in a memory of the first virtual machine, forwarding the first request to the first virtual machine (see e.g., para. [0084]: “Thus a single virtio frontend with one vring is now associated with two virtio backends. If both virtio backends access the vring concurrently, race conditions would result in corruption of the vring buffers. To solve this problem, only one virtio backend is allowed to pick up I/O requests and deliver I/O responses through the vring. So, for example, assume that the virtio backend at the L1 source is configured to interact with the vring. If an L2 VCPU running at L1 source issues an I/O request, then the corresponding kick will be handled by L1 source QEMU. However, if an L2 VCPU running at the L1target issues an I/O request, then the corresponding kick will be redirected to the QEMU at L1target. The backend in L1target QEMU will not access the vring to fetch the I/O request. Instead, the QEMU backend at L1 target is modified so that it redirects the kick one more time to the QEMU at L1 source.”); Since we can’t have both accessors access the same information at the same time, due to race conditions, the memory requests are forwarded through so that there is a hierarchy of access.
and responsive to detecting, by the hypervisor, a page fault with respect to the memory page, performing, by the hypervisor, the memory access operation with respect to the memory page of the second virtual machine (see e.g., para. [0066]: “During runtime, page faults are handled as follows. If the first level translation, i.e. (L2 VA).fwdarw.(L2 GPA), is missing then let the L2 guest assign an L2 GPA page. If the second level translation (L2 GPA).fwdarw.(L0 GPA) is missing in the shadow EPT constructed via (say) L1 source′ then L0 first lets L1 source to populate the internal mapping (L2 GPA).fwdarw.(L1 GPA) by using a page from its reserved L1 GPA space for the corresponding L2 sub-VM. Next, if a physical page was already allocated to L1target for the corresponding L1 GPA, then L0 will map the same physical to L1 source′ else a new physical page will be allocated. Conversely, if the fault relates to a missing shadow EPT entry via L1target then L0 will try to locate and map the corresponding physical page allocated to L1 source. Regardless, the two shadow EPTs constructed via either L1 will finally translate a given L2 GPA to the same HPA.”). For each level of hypervisor, Hu teaches that if a page fault occurs, to assign a memory page so that operation may continue, then perform maintenance operations to allow the system to continue as usual.
Regarding claim 2, Hu discloses:
The method of claim 1, wherein responsive to detecting the page fault, the hypervisor causes the first virtual machine to make the memory page available in the memory of the first virtual machine (see e.g., para. [0062]: “Since unallocated VAs are backed by anonymous pages, a first-time write to a VA results in a page fault. If the first level translation, i.e. (L2 VA).fwdarw.(L1 GPA), is missing in the shadow page table, then the L1 hypervisor assigns a page from the reserved GPA space to the faulting L2 VA.”).
Regarding claim 5, Hu discloses:
The method of claim 1, wherein the virtual device is directly controlled by the hypervisor (see e.g., para. [0038]: “A single hypervisor controlling a virtual central processing unit of the virtual machine may be selected for relaying input/output requests generated from the virtual machine on at least one other virtual central processing unit controlled by another hypervisor.”).
Regarding claim 11, Hu discloses:
A system comprising: a memory device; a processing device operatively coupled to the memory device, to perform operations comprising: running, by a host computer system, a hypervisor managing a first virtual machine, wherein the first virtual machine manages a second virtual machine (see e.g., para. [0003]: “Nested virtualization enables a bare-metal hypervisor (level-0 or L0) to run one or more hypervisors (level-1 or L1), each of which can run its own set of VMs [18, 7, 29, 13] (level-2 or L2).”);
For clarity of the record, the Examiner would like to point to paragraph [0032] of the Specification, which recites “In nested virtualization, a virtual device may be created and implemented by a nested hypervisor (e.g., the Level 1 hypervisor, a level 2 hypervisor, etc.) and exposed to a VM (e.g., a Level 2 VM, a level 3 VM running on a Level 2 hypervisor, etc.) as a pass-through device.” Thus, a level 2 or level 3 VM require hypervisors one level above them to function. Running a hypervisor comprises creating VMs beneath them, thus we can maintain that running Level 1 and 2 hypervisors precludes the possibility of running Level 2 and 3 VMs on their respective hypervisor.
receiving, by the hypervisor, from a virtual device, a first request to perform a memory access operation with respect to a memory page of the second virtual machine (see e.g., para. [0028]: “It is a further object to provide a method for providing multiple hypervisors for a virtual machine, comprising: providing a unitary host machine; providing at least two hypervisors which are concurrently available and independently execute on the unitary host machine; and executing a virtual machine which relies on the at least two concurrently available hypervisors to interface with the physical host system, the virtual machine having a memory map which has portions accessible by each of the at least two hypervisors”); Given that each of the two hypervisors can access the memory map, they must both be able to receive an instruction to access the memory map, whether the instruction originates from itself or another program on the device.
responsive to determining, by the hypervisor, that the memory page of the second virtual machine is unavailable in a memory of the first virtual machine, forwarding the first request to the first virtual machine (see e.g., para. [0084]: “To solve this problem, only one virtio backend is allowed to pick up I/O requests and deliver I/O responses through the vring. So, for example, assume that the virtio backend at the L1 source is configured to interact with the vring. If an L2 VCPU running at L1 source issues an I/O request, then the corresponding kick will be handled by L1 source QEMU. However, if an L2 VCPU running at the L1target issues an I/O request, then the corresponding kick will be redirected to the QEMU at L1target. The backend in L1target QEMU will not access the vring to fetch the I/O request. Instead, the QEMU backend at L1 target is modified so that it redirects the kick one more time to the QEMU at L1 source.”);
and responsive to detecting, by the hypervisor, a page fault with respect to the memory page, performing, by the hypervisor, the memory access operation with respect to the memory page of the second virtual machine (see e.g., para. [0066]: “During runtime, page faults are handled as follows. If the first level translation, i.e. (L2 VA).fwdarw.(L2 GPA), is missing then let the L2 guest assign an L2 GPA page. If the second level translation (L2 GPA).fwdarw.(L0 GPA) is missing in the shadow EPT constructed via (say) L1 source′ then L0 first lets L1 source to populate the internal mapping (L2 GPA).fwdarw.(L1 GPA) by using a page from its reserved L1 GPA space for the corresponding L2 sub-VM. Next, if a physical page was already allocated to L1target for the corresponding L1 GPA, then L0 will map the same physical to L1 source′ else a new physical page will be allocated. Conversely, if the fault relates to a missing shadow EPT entry via L1target then L0 will try to locate and map the corresponding physical page allocated to L1 source. Regardless, the two shadow EPTs constructed via either L1 will finally translate a given L2 GPA to the same HPA.”). For each level of hypervisor, Hu teaches that if a page fault occurs, to assign a memory page so that operation may continue, then perform maintenance operations to allow the system to continue as usual.
Regarding claim 12, Hu discloses:
The system of claim 11, wherein responsive to detecting the page fault, the hypervisor causes the first virtual machine to make the memory page available in the memory of the first virtual machine (see e.g., para. [0062]: “Since unallocated VAs are backed by anonymous pages, a first-time write to a VA results in a page fault. If the first level translation, i.e. (L2 VA).fwdarw.(L1 GPA), is missing in the shadow page table, then the L1 hypervisor assigns a page from the reserved GPA space to the faulting L2 VA.”).
Regarding claim 15, Hu discloses:
The system of claim 11, wherein the virtual device is directly controlled by the hypervisor (see e.g., para. [0038]: “A single hypervisor controlling a virtual central processing unit of the virtual machine may be selected for relaying input/output requests generated from the virtual machine on at least one other virtual central processing unit controlled by another hypervisor.”).
Regarding claim 17, Hu discloses:
A non-transitory machine-readable storage medium including instructions that, when accessed by a processing device, cause the processing device to perform operations comprising: running, by a host computer system, a hypervisor managing a first virtual machine, wherein the first virtual machine manages a second virtual machine (see e.g., para. [0003]: “Nested virtualization enables a bare-metal hypervisor (level-0 or L0) to run one or more hypervisors (level-1 or L1), each of which can run its own set of VMs [18, 7, 29, 13] (level-2 or L2).”);
For clarity of the record, the Examiner would like to point to paragraph [0032] of the Specification, which recites “In nested virtualization, a virtual device may be created and implemented by a nested hypervisor (e.g., the Level 1 hypervisor, a level 2 hypervisor, etc.) and exposed to a VM (e.g., a Level 2 VM, a level 3 VM running on a Level 2 hypervisor, etc.) as a pass-through device.” Thus, a level 2 or level 3 VM require hypervisors one level above them to function. Running a hypervisor comprises creating VMs beneath them, thus we can maintain that running Level 1 and 2 hypervisors precludes the possibility of running Level 2 and 3 VMs on their respective hypervisor.
receiving, by the hypervisor, from a virtual device, a first request to perform a memory access operation with respect to a memory page of the second virtual machine (see e.g., para. [0028]: “It is a further object to provide a method for providing multiple hypervisors for a virtual machine, comprising: providing a unitary host machine; providing at least two hypervisors which are concurrently available and independently execute on the unitary host machine; and executing a virtual machine which relies on the at least two concurrently available hypervisors to interface with the physical host system, the virtual machine having a memory map which has portions accessible by each of the at least two hypervisors”); Given that each of the two hypervisors can access the memory map, they must both be able to receive an instruction to access the memory map, whether the instruction originates from itself or another program on the device.
responsive to determining, by the hypervisor, that the memory page of the second virtual machine is unavailable in a memory of the first virtual machine, forwarding the first request to the first virtual machine (see e.g., para. [0084]: “To solve this problem, only one virtio backend is allowed to pick up I/O requests and deliver I/O responses through the vring. So, for example, assume that the virtio backend at the L1 source is configured to interact with the vring. If an L2 VCPU running at L1 source issues an I/O request, then the corresponding kick will be handled by L1 source QEMU. However, if an L2 VCPU running at the L1target issues an I/O request, then the corresponding kick will be redirected to the QEMU at L1target. The backend in L1target QEMU will not access the vring to fetch the I/O request. Instead, the QEMU backend at L1 target is modified so that it redirects the kick one more time to the QEMU at L1 source.”);
and responsive to detecting, by the hypervisor, a page fault with respect to the memory page, performing, by the hypervisor, the memory access operation with respect to the memory page of the second virtual machine (see e.g., para. [0066]: “During runtime, page faults are handled as follows. If the first level translation, i.e. (L2 VA).fwdarw.(L2 GPA), is missing then let the L2 guest assign an L2 GPA page. If the second level translation (L2 GPA).fwdarw.(L0 GPA) is missing in the shadow EPT constructed via (say) L1 source′ then L0 first lets L1 source to populate the internal mapping (L2 GPA).fwdarw.(L1 GPA) by using a page from its reserved L1 GPA space for the corresponding L2 sub-VM. Next, if a physical page was already allocated to L1target for the corresponding L1 GPA, then L0 will map the same physical to L1 source′ else a new physical page will be allocated. Conversely, if the fault relates to a missing shadow EPT entry via L1target then L0 will try to locate and map the corresponding physical page allocated to L1 source. Regardless, the two shadow EPTs constructed via either L1 will finally translate a given L2 GPA to the same HPA.”). For each level of hypervisor, Hu teaches that if a page fault occurs, to assign a memory page so that operation may continue, then perform maintenance operations to allow the system to continue as usual.
Regarding claim 18, Hu discloses:
The non-transitory machine-readable storage medium of claim 17, wherein responsive to detecting the page fault, the hypervisor causes the first virtual machine to make the memory page available in the memory of the first virtual machine (see e.g., para. [0062]: “Since unallocated VAs are backed by anonymous pages, a first-time write to a VA results in a page fault. If the first level translation, i.e. (L2 VA).fwdarw.(L1 GPA), is missing in the shadow page table, then the L1 hypervisor assigns a page from the reserved GPA space to the faulting L2 VA.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, 13, 14, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hu, in view of VMWare (2009), hereinafter referred to as VMWare
Regarding claim 3, VMWare discloses:
The method of claim 1, further comprising: maintaining, by the hypervisor, a memory page list, wherein the memory page list comprises a plurality of records, wherein each record of the plurality of records specifies an address of a particular memory page of the second virtual machine, wherein the particular memory page is available in the memory of the first virtual machine. (VMWare, page 7, “A hash value is generated based on the candidate guest physical page’s content. The hash value is then used as a key to look up a global hash table, in which each entry records a hash value and the physical page number of a shared page. If the hash value of the candidate guest physical page matches an existing entry, a full comparison of the page contents is performed to exclude a false match. Once the candidate guest physical page’s content is confirmed to match the content of an existing shared host physical page, the guest physical to host physical mapping of the candidate guest physical page is changed to the shared host physical page, and the redundant host memory copy (the page pointed to by the dashed arrow in Figure 4) is reclaimed. This remapping is invisible to the virtual machine and inaccessible to the guest operating system. Because of this invisibility, sensitive information cannot be leaked from one virtual machine to another”)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the method for managing virtual machines as taught by Hu to incorporate a global hash table as described by VMWare in order to save memory by not having duplicate copies for each virtual machine.
Regarding claim 4, VMWare discloses:
The method of claim 3, wherein determining that the memory page of the second virtual machine is not available in the memory of the first virtual machine further comprises: determining that the memory page of the second virtual machine does not match any record of the plurality of records in the memory page list. (“The hash value is then used as a key to look up a global hash table, in which each entry records a hash value and the physical page number of a shared page. If the hash value of the candidate guest physical page matches an existing entry, a full comparison of the page contents is performed to exclude a false match. Once the candidate guest physical page’s content is confirmed to match the content of an existing shared host physical page, the guest physical to host physical mapping of the candidate guest physical page is changed to the shared host physical page, and the redundant host memory copy (the page pointed to by the dashed arrow in Figure 4) is reclaimed”)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of managing virtual machines as taught by Hu to incorporate a global hash table as described by VMWare in order to save memory by not having duplicate copies for each virtual machine. In addition, VMWare also recites that they only perform their memory management if the hash values line up, which would mean that if they do not match, “not available” would be an apt descriptor of the memory page (or hash).
Regarding claim 13, VMWare discloses:
The system of claim 11, wherein the operations further comprise: maintaining, by the hypervisor, a memory page list, wherein the memory page list comprises a plurality of records, wherein each record of the plurality of records specifies an address of a particular memory page of the second virtual machine, wherein the particular memory page is available in the memory of the first virtual machine. (VMWare, page 7, “A hash value is generated based on the candidate guest physical page’s content. The hash value is then used as a key to look up a global hash table, in which each entry records a hash value and the physical page number of a shared page. If the hash value of the candidate guest physical page matches an existing entry, a full comparison of the page contents is performed to exclude a false match. Once the candidate guest physical page’s content is confirmed to match the content of an existing shared host physical page, the guest physical to host physical mapping of the candidate guest physical page is changed to the shared host physical page, and the redundant host memory copy (the page pointed to by the dashed arrow in Figure 4) is reclaimed. This remapping is invisible to the virtual machine and inaccessible to the guest operating system. Because of this invisibility, sensitive information cannot be leaked from one virtual machine to another”)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the method for managing virtual machines as taught by Hu to incorporate a global hash table as described by VMWare in order to save memory by not having duplicate copies for each virtual machine.
Regarding claim 14, VMWare discloses:
The system of claim 13, wherein determining that the memory page of the second virtual machine is not available in the memory of the first virtual machine further comprises: determining that the memory page of the second virtual machine does not match any record of the plurality of records in the memory page list. (“The hash value is then used as a key to look up a global hash table, in which each entry records a hash value and the physical page number of a shared page. If the hash value of the candidate guest physical page matches an existing entry, a full comparison of the page contents is performed to exclude a false match. Once the candidate guest physical page’s content is confirmed to match the content of an existing shared host physical page, the guest physical to host physical mapping of the candidate guest physical page is changed to the shared host physical page, and the redundant host memory copy (the page pointed to by the dashed arrow in Figure 4) is reclaimed”)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of managing virtual machines as taught by Hu to incorporate a global hash table as described by VMWare in order to save memory by not having duplicate copies for each virtual machine. In addition, VMWare also recites that they only perform their memory management if the hash values line up, which would mean that if they do not match, “not available” would be an apt descriptor of the memory page (or hash).
Regarding claim 19, VMWare discloses:
The non-transitory machine-readable storage medium of claim 17, wherein the operations further comprise: maintaining, by the hypervisor, a memory page list, wherein the memory page list comprises a plurality of records, wherein each record of the plurality of records specifies an address of a particular memory page of the second virtual machine, wherein the particular memory page is available in the memory of the first virtual machine. (VMWare, page 7, “A hash value is generated based on the candidate guest physical page’s content. The hash value is then used as a key to look up a global hash table, in which each entry records a hash value and the physical page number of a shared page. If the hash value of the candidate guest physical page matches an existing entry, a full comparison of the page contents is performed to exclude a false match. Once the candidate guest physical page’s content is confirmed to match the content of an existing shared host physical page, the guest physical to host physical mapping of the candidate guest physical page is changed to the shared host physical page, and the redundant host memory copy (the page pointed to by the dashed arrow in Figure 4) is reclaimed. This remapping is invisible to the virtual machine and inaccessible to the guest operating system. Because of this invisibility, sensitive information cannot be leaked from one virtual machine to another”)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the method for managing virtual machines as taught by Hu to incorporate a global hash table as described by VMWare in order to save memory by not having duplicate copies for each virtual machine.
Regarding claim 20, VMWare discloses:
The non-transitory machine-readable storage medium of claim 19, wherein determining that the memory page of the second virtual machine is not available in the memory of the first virtual machine further comprises: determining that the memory page of the second virtual machine does not match any record of the plurality of records in the memory page list. (“The hash value is then used as a key to look up a global hash table, in which each entry records a hash value and the physical page number of a shared page. If the hash value of the candidate guest physical page matches an existing entry, a full comparison of the page contents is performed to exclude a false match. Once the candidate guest physical page’s content is confirmed to match the content of an existing shared host physical page, the guest physical to host physical mapping of the candidate guest physical page is changed to the shared host physical page, and the redundant host memory copy (the page pointed to by the dashed arrow in Figure 4) is reclaimed”)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of managing virtual machines as taught by Hu to incorporate a global hash table as described by VMWare in order to save memory by not having duplicate copies for each virtual machine. In addition, VMWare also recites that they only perform their memory management if the hash values line up, which would mean that if they do not match, “not available” would be an apt descriptor of the memory page (or hash).
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over L1, in view of Chen et al. (US 2019/0004850), hereinafter referred to as Chen.
Regarding claim 8, Chen discloses:
The method of claim 1, wherein determining that the memory page of the second virtual machine is unavailable further comprises determining that the memory page is encrypted. (Chen, Figure 8A & 8B [Note: Flowchart] “Is Page Encrypted? -Yes-> A -> […] -> Does NH [New Hash] = H [Hash (old)]? -No-> Assert Fault Condition”)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of managing virtual machines as taught by Hu to incorporate determining whether or not a memory page is encrypted as part of the process to determine whether or not the memory page in question is available in order to account for the possibility that the memory page is present but unreadable (e.g. encrypted) via either the L0 hypervisor or some other program, in which case the process to manage the memory page would be different.
Allowable Subject Matter
Claims 6, 9-10, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Connor Imiola Blackburn whose telephone number is (571) 272 - 6547. The examiner can normally be reached M-Th 7-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin Young can be reached at (571) 270 - 3180. The fax phone number for the organization where this application or proceeding is assigned is (571) 273 - 8300.
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/C.I.B./Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194