DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Oath/Declaration
Applicant has mislabeled the declaration as being a declaration under 37 C.F.R. 1.130(b) instead of being a declaration under 37 C.F.R. 1.130(a). For the sake of examination, Examiner will treat the declaration as a declaration under 37 C.F.R. 1.130(a). Applicant is encouraged, but not required, to resubmit the declaration under 37 C.F.R. 1.130(a).
The declaration under 37 CFR 1.130(a) filed on June 9, 2026, is sufficient to overcome the rejection of claims 1-13 based on “DRAM Based Processing-In-Memory Architecture for Data Analytics” by Donghyuk Kim.
Examiner’s Note
Examiner notes that some of the deletions, such as the deletion of the comma in claim 1, line 7, do not comply with 37 CFR 1.121(c)(2), which states "The text of any deleted subject matter must be shown by being placed within double brackets if strike-through cannot be easily perceived." Ensure that deletions comply with 37 CFR 1.121(c)(2) in the future.
Drawings
The currently amended drawings and Fig. 8 of the original drawings are objected for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(I), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. When zooming into the images, pixelation of the drawings can be seen. This is an indicator that the images were drawn in a color other than black or were upscaled beyond its native resolution, making the drawings look “blurry”.
Fig. 1 is further objected to for failing to comply with 37 CFR 1.84(p)(3), which requires that numbers, letters, and reference characters should not cross or mingle with the lines. The letter “B” of “BPU” mingles with the lead line of 1310.
The drawings are objected to because of the following informalities:
Fig. 1: Reference character 10 has an underline. Underlines should only be used when a lead line for a reference character has not been left out by mistake (37 C.F.R. 1.84(q)). Applicant is advised to delete the underline.
Fig. 3: Reference characters 20, 110, 120, and 130 have underlines. Underlines should only be used when a lead line for a reference character has not been left out by mistake (37 C.F.R. 1.84(q)). Applicant is advised to delete the underline.
Fig. 4: Reference character 121 has an underline. Underlines should only be used when a lead line for a reference character has not been left out by mistake (37 C.F.R. 1.84(q)). Applicant is advised to delete the underline.
Applicant is reminded of 37 CFR 1.84(i), which indicates that, if possible, a view should stand so that it can be read with the sheet held in an upright position. Examiner believes Figs. 2-4 can stand upright based on the current size of the figures.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1-2, 4, and 6-9 are objected to because of the following informalities:
Claim 1, line 15: replace the comma near the end of the line with a semicolon to match the punctuation used with the rest of the claim.
Claim 2, line 3: Change “the bank group” to “a bank group” to address antecedent basis issues.
Claim 4, lines 1-2: Change “the rank buffer” to “a rank buffer” to address antecedent basis issues.
Claim 6, line 3: Change “the DA engine” to “a DA engine” to address antecedent basis issues.
Claim 7, lines 1-2: Change “the bank group processing unit” to “a bank group processing unit” to address antecedent basis issues.
Claim 8, lines 1-2: Change “the bank group processing unit” to “a bank group processing unit” to address antecedent basis issues.
Claim 9, lines 1-2: Change “the bank group processing unit” to “a bank group processing unit” to address antecedent basis issues.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“data analytics (DA) engine to perform an irregular operation” in claim 1, invokes 112(f). Examiner finds the functions (performing a join operation, which is an irregular operation, see [0036]) which is done by the join unit, located within the DA engine of the BGPU (e.g., see [0063, 0065] and Fig. 5). The join unit comprises at least one comparator, which is used to perform the join operation.
“Bank group controller configured to receive results of the Project and the Join-merge operations and to generate a command” in claim 6, invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings to perform the functions mentioned above. Examiner finds that the functions are performed by the PIM command generator (e.g., see [0061, 0065] and Fig. 5), not the bank group controller. Furthermore, the term “PIM command generator” is not sufficient structure to perform the functions mentioned. For the purposes of prior art examination, Examiner is interpreting “Bank group controller” as any circuit that performs the functions mentioned.
“project unit… to perform Project” in claim 6, invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings to perform the functions mentioned above. Examiner finds the function performed by the project unit, located within the DA engine of the BGPU (e.g., see [0063] and Fig. 5). The project unit comprises an index selector to perform the operation. However, the term “index selector” is not sufficient structure to perform the function. For the purposes of prior art examination, Examiner is interpreting “project unit” as any circuit that performs the project operation. Examiner recommends Applicant to replace “unit” with “circuit” to avoid having the limitation be interpreted under 112(f) (MPEP 2181(I)(A), paragraph 3).
“join unit… to perform… Join-merge operations” in claim 6, invokes 112(f). Examiner finds the function performed by the join unit, located within the DA engine of the BGPU (e.g., see [0065] and Fig. 5). The join unit comprises at least one comparator, which is used to perform the join operation.
“PIM command generator configured to receive operation results from the DA engine and generate a command at the bank group level” in claim 7, invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings to perform the functions mentioned above. Examiner finds that the functions performed by the PIM command generator (e.g., see [0064, 0068] and Fig. 6). However, the term “PIM command generator” is not sufficient structure to perform the functions mentioned. For the purposes of prior art examination, Examiner is interpreting “PIM command generator” as any circuit that performs the functions mentioned. Examiner recommends Applicant to insert “circuit” after “generator” to avoid having the limitation be interpreted under 112(f) (MPEP 2181(I)(A), paragraph 3).
“permutation unit configured to perform permutation” in claim 9, invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings to perform the functions mentioned above. Examiner finds the functions are performed by the OID permute unit, located within the OID processing engine (e.g., see [0072, 0077]). However, the term “OID permute unit” is not sufficient structure to perform permutation. For the purposes of prior art examination, Examiner is interpreting “OID processing engine” as any circuit that performs permutation. Examiner recommends Applicant to replace “unit” with “circuit” to avoid having the limitation be interpreted under 112(f) (MPEP 2181(I)(A), paragraph 3).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6-7 and 9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 6-7 and 9, as described below in the 112(b) rejection, the disclosure does not provide adequate structure to perform the claimed functions of receiving results of the Project and the Join-merge operations, generating a command, performing project, receiving operation results from the DA engine, generating a command at the bank group level, and performing permutation. The application does not demonstrate that the applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claim 7 is rejected for inheriting the rejection of the claims in which they depend on.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 6-7 and 9, the claims contain the claim limitations “Bank group controller”, “project unit”, “PIM command generator”, and/or “permutation unit”, in which they invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structures, materials, or acts for performing the entire claimed functions and to clearly link the structures, materials, or acts to the functions. The specification is devoid of adequate structure to perform the claimed function. In particular, the specification states that the claimed functions of receiving results of the Project and the Join-merge operations, generating a command, performing project, receiving operation results from the DA engine, generating a command at the bank group level, and performing permutation are done by either a “Bank group controller”, “project unit”, “PIM command generator”, and/or “permutation unit”. The use of the terms are not adequate structures for performing the claimed functions mentioned previously because it does not describe a particular structure for performing the functions. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure would perform the claimed function. Therefore, the claims are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 7 is rejected for inheriting the rejection of the claims in which they depend on.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 2-3, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Madan et al. (US 20240103745 A1) in view of Nale (US 20260140894 A1), Huangfu et al. (US 20260079850 A1), Kim et al. (US 20240354278 A1), and Torii et al. (US 4779192 A).
Chang (US 20220215863 A1) is cited as extrinsic evidence to explain that DRAM comprises of data pins.
Regarding claim 1, Madan teaches a multilevel processing in memory processing-in-memory (PIM) system (Fig. 1 and [0034]: Memory system 100 comprises of PIM blocks 108(0-X). Therefore, the memory system is a processing-in-memory system) comprising:
a memory module comprising at least one rank in which a computation operation and a data storage operation are performed in response to a control command from a memory controller (Fig. 1 and [0011-0012, 0034-0035]: Memory module 102 receives PIM and memory requests from memory controller 104, in which a memory controller may concurrently issue a memory request and a PIM request. Memory module comprises of one rank, which includes PIM blocks 108(0-X). The concurrent memory and PIM request as the control command), wherein:
each of the at least one rank comprises a plurality of chips ; and
each of the plurality of chips comprises a bank group processing unit, and a plurality of bank groups (Fig. 1 and [0037]: Each PIM block 108 includes an in-memory processor and a plurality of multi-cast groups 114 and 116, each comprising a bank 112. Therefore, the plurality of multi-cast groups as the plurality of bank groups), and
Madan does not teach that each rank comprises a rank buffer, where the rank buffer manages a data movement between the plurality of chips in response to the control command.
Nale teaches data buffers that manages data movement between a plurality of chips in response to a command (Fig. 1 and [0029, 0033]: The data buffers 144 are to be used to move data for the DRAM chips 142 in response to commands involving data exchange, such as read and write commands. The DRAM chips as the plurality of chips).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Madan with the teachings of Nale to have the rank to include a buffer for data to be stored during data movement. One of ordinary skill would recognize that by utilizing buffers, a slower unit can go ahead and process the data while the faster unit can continue to add more data to the buffer and to not stall on the slower unit, which may improve processing performance.
Madan, in view of Nale, still does not teach that each of the plurality of chips comprise a PIM command scheduler and a plurality of bank group processing units, wherein the PIM command scheduler is to manage a command necessary for computation.
Huangfu teaches a plurality of chips, wherein each chip comprises a command scheduler and a plurality of bank group processing units (Figs. 8-9 and [0072, 0106]: Each rank chip 820 in memory module 804 comprises of a near-memory computing module 824, where each module comprises of a workload monitor 938 and processing elements 932). The workload monitor as the command scheduler and the processing elements as the plurality of bank group processing units, since the elements use data from a plurality of banks 910, which results in a group of banks), wherein the command scheduler is to manage a command necessary for computation (Figs. 8-9 and [0106]: The workload monitor may perform task scheduling between the processing elements. Therefore, the workload monitor manages one or more commands necessary for computations between the processing elements).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Madan, in view of Nale, with the teachings of Huangfu, for each chip to comprise of multiple processors, and each chip to comprise of a command scheduler to manage commands between the plurality of processors. One of ordinary skill would recognize that by including multiple processors and having a scheduler to manage the workload between the processors, multiple commands can be processed at the same time, which increase processing output.
Madan, in view of Nale and Huangfu, still does not teach that each of the bank group processing units comprises a DA engine to perform an irregular operation and a bank group processing unit included in each of the plurality of bank groups, the bank processing units comprising a SIMD architecture to perform a regular operation.
Note that in the current combination, the plurality of in-memory processors in each PIM block act as both the bank processing units and bank group processing units since the processors processes data from a multi-cast group, comprising of a bank to fetch memory from (see Madan, Fig. 1). Therefore, they are considered bank processing units and bank group processing units.
Kim teaches a processor, comprising a DA engine to perform an irregular operation and the processor is to also perform a regular operation (Figs. 2A-C, [0036, 0075]: The memory processor may perform a sort-merge join, which is a mix of a sort operation and a join operation that merges data together (which are indicated as a regular and irregular operation in Applicant’s specification. See [0036]), which means the processor must have a comparator to perform the join segment of the operation. Therefore, the processor must have a DA engine (see “Claim Interpretation” section)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Madan, in view of Nale and Huangfu, with the teachings of Kim to have the in-memory processor comprise a DA engine to perform an irregular operation and the processor to perform a regular operation. One of ordinary skill would recognize that by utilizing a processor to perform operations which requires moving/modifying data, such as join and sort operations, in memory, those operations would be processed faster compared to fetching the data from memory to a main processor located outside the memory.
Madan, in view of Nale, Huangfu, and Kim, still does not teach that the bank group processing unit comprises of a SIMD architecture to perform the regular operation.
Torii teaches to use a SIMD architecture to perform a merge-join operation (Fig. 3 and Col. 2, lines 37-51: Vectors V14 and V15 are used to perform a merge join between the two vectors. Since the operation involves vector registers, it must be that the processor has a SIMD architecture).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Madan, in view of Nale, Huangfu, and Kim, with the teachings of Torii to have the processor use a SIMD architecture to perform the join operation. One of ordinary skill would recognize that by using a SIMD architecture, more data can be fetched and processed at the same time, which may be appreciated.
Regarding claim 2, Madan, in view of Nale, Huangfu, Kim, and Torii, teaches the multilevel PIM system of claim 1, wherein the regular operation is distributed across and performed in parallel in a plurality of banks (Kim, Figs. 2A-C, [0036, 0075]; Madan, [0039]: In the current combination, a PIM request, which would include performing sort-merge join, may include using data between banks from different bank groups in a PIM block).
Madan, in view of Nale, Huangfu, Kim, and Torii, does not teach a plurality of banks are included in the bank group.
Huangfu also teaches a plurality of devices included in a device group installed in a chip (Fig.9 and [0071]: A plurality of memory devices 910 exists, which makes up a device group installed on a rank 920 (i.e., a memory chip)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further combined the teachings of Madan, in view of Nale, Huangfu, Kim, and Torii, with the teachings of Huangfu to have multiple banks located within the multi-cast group to perform an operation between the banks within the same multicast group. By including more memory banks, more storage can be realized without needing more processors to control the banks, which reduces hardware in exchange for hardware complexity, which may be preferred by one of ordinary skill. Furthermore, duplication of parts, i.e., duplication the number of banks in a multi-cast group, is a routine expedient, not a patentable distinction (MPEP 2144.04(VI)(B)).
Regarding claim 3, Madan, in view of Nale, Huangfu, Kim, and Torii, teaches the multilevel PIM system of claim 1, wherein the regular operation comprises at least one of Select, Aggregate, or Sort, and the irregular operation comprises at least one of Project or Join-merge (See claim 1 above, the current system combination would perform a sort-merge join operation, which comprises of multiple operations, including a sort operation and a Join operation (which includes merging data, hence a Join operation is a Join-merge operation)).
Regarding claim 10, Madan, in view of Nale, Huangfu, Kim, and Torii, teaches the multilevel PIM system of claim 1, wherein the PIM command scheduler of a chip among the plurality of chips retrieves an instruction through a plurality of data pins (Madan, Fig. 1 and [0034]: In the current combination, the memory module 102 may be DRAM, which would include a plurality of data pins (see Chang, [0045]), in which the memory controller 104 would send PIM requests through those plurality of data pins to the schedulers located within the PIM blocks).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Madan et al. (US 20240103745 A1) in view of Nale (US 20260140894 A1), Huangfu et al. (US 20260079850 A1), Kim et al. (US 20240354278 A1), Torii et al. (US 4779192 A), and Resnick (US 20090150624 A1).
Regarding claim 4, Madan, in view of Nale, Huangfu, Kim, and Torii, teaches the multilevel PIM system of claim 1.
Madan, in view of Nale, Huangfu, Kim, and Torii, does not explicitly teach that the rank buffer reads data stored in a bank of a first chip, among the plurality of chips, in response to a data read command received from the memory controller, stores the data, and transmits the data to a second chip in response to a write command received from the memory controller.
Resnick teaches to read data stored in a bank of a first chip, among the plurality of chips, in response to a data read command received from the memory controller (Figs. 1-2 and 4, [0023, 0032-0033, 0061-0062]: A read operation initiates a read command, which indicates that data is to be read from a bank (from memory 292, indicated as banks) located in a memory card 290 (i.e., a chip). The read command is sent by the memory controller 100 through memory data bus 175), stores the data (Figs. 2 and 4, [0063]: A read buffer 154 stores returned read data), and transmits the data to a second chip in response to a write command received from the memory controller (Figs. 2 and 5, [0032-0033, 0070-0073]: In response to a read-modify-write operation, if data is already stored in a data buffer, such as read buffer 154, the data is read from the buffer, modifies the data, and sends the modified data to a memory card 290 (which does not necessarily indicate the same memory card that performed the read operation) via a write command. The write command is sent by the memory controller 100 through memory data bus 175).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Madan, in view of Nale, Huangfu, Kim, and Torii, with the teachings of Resnick to have rank buffer store data read from a chip in response to a read command, and transmit the written data to another chip in response to a write command. One of ordinary skill would recognize that by having data stored in a buffer after read operations and a write operation (such as a read-modify-write operation) requires that read data, rather than re-fetching the data, the rank buffer can instead provide the read data, perform any necessary modifications, and writeback to the other chip. This process avoids the burdensome process of having to activate and wait for the bank to activate, which improves processing performance.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Madan et al. (US 20240103745 A1) in view of Nale (US 20260140894 A1), Huangfu et al. (US 20260079850 A1), Kim et al. (US 20240354278 A1), Torii et al. (US 4779192 A), and La Fratta et al. (US 20230060826 A1).
Regarding claim 5, Madan, in view of Nale, Huangfu, Kim, and Torii, teaches the multilevel PIM system of claim 1, wherein the PIM command scheduler in each of the plurality of chips supervises a bank included in a bank group installed in a chip, among the plurality of chips, in which the PIM command scheduler is installed (Madan, Fig. 1 and [0034]; Huangfu, Figs. 8-9 and [0072, 0106]: In the current combination, the command scheduler supervises and oversees a bank of a multi-cast group in each PIM block, in which the command scheduler oversees the multi-cast groups that are on the same PIM block as the command scheduler itself).
Madan, in view of Nale, Huangfu, Kim, and Torii, does not teach a plurality of banks are included in a bank group installed in a chip.
Huangfu also teaches a plurality of devices included in a device group installed in a chip (Fig.9 and [0071]: A plurality of memory devices 910 exists, which makes up a device group installed on a rank 920 (i.e., a memory chip)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further combined the teachings of Madan, in view of Nale, Huangfu, Kim, and Torii, with the teachings of Huangfu to have multiple banks located within the multi-cast group. By including more memory banks, more storage can be realized without needing more processors to control the banks, which may be appreciated by one of ordinary skill. Furthermore, duplication of parts, i.e., duplication the number of banks in a multi-cast group, is a routine expedient, not a patentable distinction (MPEP 2144.04(VI)(B)).
Madan, in view of Nale, Huangfu, Kim, and Torii, still does not teach PIM command scheduler in each of the plurality of chips supervises a command queue of a plurality of banks.
La Fratta teaches a command scheduler supervising a command queue of a plurality of banks (Fig. 3 and [0037]: A command scheduler 301 oversees and supervises a command queue component, which comprises of queues for a plurality of banks).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Madan, in view of Nale, Huangfu, Kim, and Torii, with the teachings of La Fratta to have the command scheduler to be coupled with a command queue to supervise the plurality of banks. One of ordinary skill would recognize that by buffering commands to the command queues for the plurality of banks, data could be temporarily stored for a unit that may be unavailable, allowing the unit that sent the data (such as the command scheduler) to continue processing and sending other data, improving the performance of the system.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Madan et al. (US 20240103745 A1) in view of Nale (US 20260140894 A1), Huangfu et al. (US 20260079850 A1), Kim et al. (US 20240354278 A1), Torii et al. (US 4779192 A), and Anderson et al. (“A 1.5 Ghz VLIW DSP CPU with integrated floating point and fixed point instructions in 40 nm CMOS”).
Regarding claim 8, Madan, in view of Nale, Huangfu, Kim, and Torii, teaches the multilevel PIM system of claim 1.
Madan, in view of Nale, Huangfu, Kim, and Torii, does not teach that the bank processing unit comprises a set of fixed-point adders and a set of fixed-point multipliers within the SIMD architecture that are used to process the regular operation.
Anderson teaches a processing unit comprising a set of fixed-point adders and a set of fixed-point multipliers within a SIMD architecture that are used to process a regular operation (Page 2, Figure 2 and section “Datapath Overview”: A CPU has a datapath comprising two fixed-point multiplier units (referring to M1 and M2 in figure 2) to perform multiplication operations and two fixed-point adder units (referring to L1 and L2 in figure 2) to perform addition operations. The datapath supports SIMD instructions to perform SIMD operations. Therefore, the datapath comprises a SIMD architecture. The multiplication and addition operations as regular operations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Madan, in view of Nale, Huangfu, Kim, and Torii, with the teachings of Anderson to have the bank processing unit comprise of fixed-point adders and fixed-point multipliers to perform fixed-point addition and fixed-point multiplication. By including fixed-point adders and fixed-point multipliers in the bank processing unit, the processing unit would be able to utilize and store numbers with fractions or very small numbers that can’t be represented with an integer number, which may be appreciated by one of ordinary skill.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Madan et al. (US 20240103745 A1) in view of Nale (US 20260140894 A1), Huangfu et al. (US 20260079850 A1), Kim et al. (US 20240354278 A1), Torii et al. (US 4779192 A), and Lea et al. (US 20190065111 A1).
Wikipedia “Very long instruction word” is cited as extrinsic evidence to explain the structure of VLIW instructions.
Regarding claim 11, Madan, in view of Nale, Huangfu, Kim, and Torii, teaches the multilevel PIM system of claim 10.
Madan, in view of Nale, Huangfu, Kim, and Torii, does not teach that the instruction is composed of instruction segments that are arranged in an interleaving manner.
Lea teaches to send an instruction composed of instruction segments that are arranged in an interleaving manner to a PIM device (Fig. 1A, [0015, 0059]: The PIM device 101 may receive VLIW instructions, which is an instruction composed of instruction segments arranged in an interleaving manner (See Wikipedia, page 2, under “Design”, a VLIW instruction comprises of multiple operations, interleaved so that the operations can occur in parallel)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Madan, in view of Nale, Huangfu, Kim, and Torii, with the teachings of Lea to have the PIM commands sent to the memory module be VLIW instructions. One of ordinary skill would recognize that by utilizing VLIW instructions, hardware complexity within the processors executing the instruction may be reduced.
Regarding claim 12, Madan, in view of Nale, Huangfu, Kim, Torii, and Lea, teaches the multilevel PIM system of claim 11, wherein a transmission cycle of an arrangement of the instruction segments is determined by a burst length (Lea, [0115]; Madan, Fig. 1: In the current combination, up to 150 bits may be transmitted at once from the memory controller to a PIM block (i.e., a burst length of bits) to transmit the VLIW instruction (i.e., a transmission cycle of an arrangement of the instruction segments)).
Regarding claim 13, Madan, in view of Nale, Huangfu, Kim, Torii, and Lea, teaches the multilevel PIM system of claim 10, wherein the instruction comprises any one of activation, precharge, read, and write operations for a chip among the plurality of chips (Madan, [0039]: In the current combination, the VLIW instruction may comprise a read-modify-write operation from one memory bank and into another memory bank within a PIM block, which is a combination of a read operation and a write operation).
Allowable Subject Matter
Claims 6-7 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable, over the prior art, if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 6-7, the prior art of record has not taught, either individually or in combination, and together with all other claimed features, that each of the plurality of bank group processing units comprises:
a DA engine comprising a demultiplexer, a project unit, and a join unit configured to perform Project and Join-merge operations, and
a bank group controller configured to receive results of the project and the Join-merge operations and to generate a command at a bank group level.
Regarding claim 9, the prior art of record has not taught, either individually or in combination, and together with all other claimed features, that the bank processing unit further comprises an object identifier (OID) processing engine comprising at least one permutation unit configured to perform permutation on result data of the regular operation and an address to which a tag has been designated.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 12517817 B2: Heo et al. teaches a plurality of memory chips comprising a processing unit coupled to a plurality of memory banks.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
