DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. When zooming into the images, pixelation of the drawings can be seen. This is an indicator that the images were drawn in a color other than black or were upscaled beyond its native resolution.
Figs. 9-10 are further objected to for failing to comply with 37 CFR 1.84(i), which requires that words appear in a horizontal, left-to-right fashion when the page is either upright or turned so that the top becomes the right side. Note, from 37 CFR 1.84(f), that the top of the sheet is regarded as one of the shorter sides. For example, in Fig. 9, the text “Rank0” needs to be rotated 180 degrees.
Figs. 1, 6-7, and 12 are further objected to for failing to comply with 37 CFR 1.84(p)(3), which requires that numbers, letters, and reference characters should not cross or mingle with the lines.
Figs. 1-2, 7, and 11-12 are further objected to for failing to comply with 37 CFR 1.84(p)(3), which requires that numbers, letters, and reference characters should not be placed upon hatched or shaded surfaces.
Figs. 1 and 5-7 are further objected to for failing to comply with 37 CFR 1.84(p)(3), which requires that numbers, letters, and reference characters must measure at least .32 cm. (1/8 inch) in height. Examiner believes that the letters in the drawings do not meet this requirement, although Examiner has not measured every letter, number, and reference character.
Figure 12 is objected to because of the minor informalities:
Rightmost “Thread 2” should instead read as “Thread 3”.
The following recommendations are made for the drawings:
Figs, 9-10: A space could be added between “Rank” and “0”, “group” and “0”, etc., to improve readability.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The abstract of the disclosure is objected to because of the following informalities:
Line 1: Hyphens should be added between “processing in memory”, which should read as “processing-in-memory”.
Line 1: The term “processing-in-memory” is unclear in its current form. Examiner recommends that the line reads as “processor-in-memory (PIM)” or “multilevel processing-in-memory (PIM) system”.
Line 5: Applicant should replace “processing in memory” with the abbreviation “PIM” as established in line 1.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
[0001, 0003, 0005, 0020]: Hyphens should be added between “processing in memory”, which should read as “processing-in-memory”.
[0072]: In line 2, the phrase “an Select” is grammatically incorrect and should be change to “a Select”.
[0077]: In line 1, the phrase “sixteen output data” is unclear and should be addressed.
[0107]: In line 3, remove “basically” to improve conciseness of the sentence.
Appropriate correction is required.
Examiner makes the following recommendations:
Examiner recommends that Applicant reviews the specification for any phrases which may contain grammatical and idiomatic errors.
[0075]: In lines 4-5, the phrase “the two Permute units 1627 and 1628 may be deployed before and behind the SIMD 1624” can be made clearer by replacing “behind” with “after”.
Claim Objections
Claims 1-13 are objected to because of the following informalities:
Claim 1, line 1: Hyphens should be added between “processing in memory”, which should read as “processing-in-memory”.
Claim 1, line 1: The term “processing-in-memory” is unclear in its current form. Examiner recommends that the line reads as “processor-in-memory (PIM) comprising:” or “A multilevel processing-in-memory (PIM) system”.
Claim 1, line 9: The use of “wherein” in the line would indicate that the “wherein” clause applies to all limitations after. To alleviate this issue, Examiner recommends that Applicant inserts “wherein:” at the end of line 4, remove the three subsequent instances of “wherein”, and indent everything after the first paragraph.
Claim 6, line 6: Insert “the” before “Join-merge” for clarity.
Claim 10: The claim is written in a way that’s difficult to read/understand. Applicant is advised to re-write the claim so that it’s readable and understandable. Examiner makes the following recommendation: “wherein the PIM command scheduler of the chip retrieves an instruction through a plurality of data pins”.
Claims 2-13 are objected to for inheriting the objection of the claims in which they depend on.
Appropriate correction is required.
Examiner makes the following recommendations:
In claim 1, replace the usage of commas (,) with semicolons (;) when appropriate, as it improves the readability of the claims (see claim 6 as an example of how the claim should be structured with semicolons).
Claim 3, line 1: Remove the colon (:) after “wherein” and place the limitations all within one continuous line, such that it reads as “wherein the regular operation comprises at least one of Select, Aggregate, or Sort, and the irregular operation comprises at least one of Project or Join-merge.”
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“Bank group processing unit performs an irregular operation” in claim 1, invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings to perform the functions mentioned above. Examiner finds the functions (performing join and project operations, see [0036]) are performed by the bank group processing unit (BGPU), which are done by the project unit and join unit, located within the DA engine of the BGPU (e.g., see [0035, 0060-0063]). However, the terms “project unit” and “join unit” are not sufficient structures to perform the functions. For the purposes of prior art examination, Examiner is interpreting “Bank group processing unit” as any circuit that performs the project operation and the join operation.
“Bank processing unit… performs a regular operation” in claim 1, invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings to perform the functions mentioned above. Examiner finds the functions (perform select, aggregate, and select operations, see [0036]) are performed by the bank processing unit (BPU), which are performed by the SIMD unit and permute unit of the BPU (e.g., see [0034, 0071-0077]). However, the term “permute unit” is not sufficient structure to perform the sort operation. For the purposes of prior art examination, Examiner is interpreting “bank processing unit” as any circuit that performs the sort operation.
“Bank group controller configured to receive results of the Project and Join-merge operations and to generate a command” in claim 6, invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings to perform the functions mentioned above. Examiner finds that the functions are performed by the PIM command generator (e.g., see [0061, 0065] and Fig. 6), not the bank group controller. Furthermore, the term “PIM command generator” is not sufficient structure to perform the functions mentioned. For the purposes of prior art examination, Examiner is interpreting “Bank group controller” as any circuit that performs the functions mentioned.
“DA engine configured to perform Project and Join-merge operations” in claim 6, invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings to perform the functions mentioned above. Examiner finds the functions (perform join and project operations) are performed by the project unit and join unit, located within the DA engine of the BGPU (e.g., see [0035, 0060-0063]). However, the terms “project unit” and “join unit” are not sufficient structures to perform the functions. For the purposes of prior art examination, Examiner is interpreting “DA engine” as any circuit that performs the project operation and the join operation.
“An object identifier (OID) processing engine configured to perform permutation” in claim 9, invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings to perform the functions mentioned above. Examiner finds the functions are performed by the OID permute unit, located within the OID processing engine (e.g., see [0072, 0077]). However, the term “OID permute unit” is not sufficient structure to perform permutation. For the purposes of prior art examination, Examiner is interpreting “OID processing engine” as any circuit that performs permutation.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1, 6, and 9, as described below in the 112(b) rejection, the disclosure does not provide adequate structure to perform the claimed functions of performing an irregular operation, performing the sort operation, receiving results of the Project and Join-merge operations, generating a command, performing Project and Join-merge operations, and performing permutation. The application does not demonstrate that the applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claims 2-13 are rejected for inheriting the rejection of the claims in which they depend on.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the rank" in line 5. There is insufficient antecedent basis for this limitation in the claim. Although there was a prior recitation of “at least one rank”, the phrase “at least one” encompasses “one or more”. Therefore, antecedent basis cannot be established for “the rank”. For the sake of examination, Examiner will interpret this limitation to be “the at least one rank”.
Claim 1 recites the limitation "the PIM command scheduler" in line 5. There is insufficient antecedent basis for this limitation in the claim. Although there was a prior recitation of “a PIM command scheduler” in claim 1, lines 9-10, there are multiple “PIM command schedulers” in each of the chips, so it’s unclear which “PIM command scheduler” the claim is referring to. For the sake of examination, Examiner will interpret this limitation to be “the PIM command scheduler in each of the plurality of chips”.
Claim 2 recites the limitation "the regular operations" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Although there was a prior recitation of a “regular operation” in claim 1, last line, the limitation encompasses a singular “regular operation”. For the sake of examination, Examiner will interpret this limitation to read as “wherein regular operations are performed in parallel”.
Claim 5 recites the limitation "the PIM command scheduler" in line 5. There is insufficient antecedent basis for this limitation in the claim. Although there was a prior recitation of “a PIM command scheduler” in claim 1, lines 9-10, there are multiple “PIM command schedulers” in each of the chips, so it’s unclear which “PIM command scheduler” the claim is referring to. For the sake of examination, Examiner will interpret this limitation to be “the PIM command scheduler in each of the plurality of chips”.
Claim 5 recites the limitation "the chip" in line 3. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “a chip” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret this limitation to be “a chip, among the plurality of chips”.
Claim 10 recites the limitation "the chip" in line 1. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “a chip” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret this limitation to be “a chip, among the plurality of chips”.
Claim 12 recites the limitation "the arrangement of the commands" in line 1. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “an arrangement of commands” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret this limitation to be “the arrangement of the instruction segments” as Examiner believes “the commands” refers to the “instruction segments” in claim 11.
Claim 13 recites the limitation "the chip" in line 3. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “a chip” within the claim or the claim it depends on. For the sake of examination, Examiner will interpret this limitation to be “a chip, among the plurality of chips”.
Claim 1 contains the claim limitations “Bank group processing unit” and “Bank processing unit”, which invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. In particular, the specification states that the claimed function of performing an irregular operation is performed using a “Bank group processing unit” and the claimed function of performing a regular operation is performed by a “Bank processing unit.” The use of the terms “Bank group processing unit” and “Bank processing unit” are not adequate structures for performing the claimed functions mentioned previously because it does not describe a particular structure for performing the functions. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure would perform the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claim 6 contains the claim limitations “PIM command generator” and “DA engine”, which invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. In particular, the specification states that the claimed functions of receiving results of the Project and Join-merge operations and generating a command are performed using a “PIM command generator” and the claimed function of performing Project and Join-merge operations is performed using a “DA engine.” The use of the terms “DA engine” and “PIM command generator” are not adequate structures for performing the claimed functions mentioned previously because it does not describe a particular structure for performing the functions. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure would perform the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claim 9 contains the claim limitations “OID processing engine”, which invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. In particular, the specification states that the claimed function of performing permutation is performed using a “OID processing engine.” The use of the term “OID processing engine” is not an adequate structure for performing the claimed functions mentioned previously because it does not describe a particular structure for performing the functions. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure would perform the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 2-13 are rejected for inheriting the rejection of the claims in which they depend on.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 5-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (“DRAM based processing-in-memory architecture for data analytics”, see IDS filed 07/31/2023).
Regarding claim 1, Kim teaches a multilevel processing in memory (PIM) (Pages 8-9, Fig. 4.1(a): DB DRAMPIM architecture) comprising:
a memory module comprising at least one rank in which a computation operation and a data storage operation are performed in response to a control command from a memory controller (Pages 4-6 and 8-9, Figs. 2.1 and 4.1(a), Sections 2.2, 3.1, and 4.2: The DBRAM architecture is to be implemented on LRDIMMs of a main memory system. The rank buffer of an LRDIMM would receive commands from a memory controller to perform operations which uses the computation units (i.e., bank group processing units and bank processing units) of the LRDIMM to perform operations in memory, which includes data storage operations such as reading from one or more memory banks. The main memory system as the memory module. LRDIMMs as the ranks),
wherein the rank comprises a plurality of chips and a rank buffer (Pages 8-9, Fig. 4.1(a), Section 4.2: Fig. 4.1(a) shows a plurality of die chips and a buffer chip comprising of a rank buffer),
wherein the rank buffer manages a data movement between the plurality of chips in response to the control command (Pages 4-5 and 8-9, Figs. 2.1 and 4.1(a), Sections 2.2 and 4.2: The rank buffer may perform data movement between banks or bank groups from other dies in response to an operation (such as a command) received from the memory controller of the main memory system),
wherein each of the plurality of chips comprises a PIM command scheduler, a plurality of bank group processing units, and a plurality of bank groups (Pages 8-9 and Fig. 4.1(a), Section 4.2: The die chips of the DBRAM architecture comprises of a PIM command scheduler, a plurality of bank group processing units, and a plurality of bank groups),
the PIM command scheduler individually manages a command necessary for computation (Page 10-11, Section 4.4: PIM command scheduler manages PIM commands that are to be executed),
a bank group processing unit performs an irregular operation (Pages 10-11, Section 4.4: Bank group processing units can perform project and join operations, indicated as irregular operations in Applicant’s specification (see [0036])), and
a bank processing unit included in a bank group performs a regular operation (Pages 9-10, Section 4.3: Bank processing units can perform select, aggregate, and sort operations, indicated as regular operations in Applicant’s specification (see [0036])).
Regarding claim 2, Kim teaches the multilevel PIM of claim 1, wherein the regular operations are performed in parallel in a plurality of banks included in the bank group (Pages 8-9, Fig. 4.1(a), Sections 4.2 and 4.3: Bank level parallelism may occur. Therefore, a plurality of banks in a bank group (e.g., bank group 0 of die 1) may independently execute select, aggregate, or sort operations).
Regarding claim 3, Kim teaches the multilevel PIM of claim 1, wherein: the regular operation comprises at least one of Select, Aggregate, or Sort, and the irregular operation comprises at least one of Project or Join-merge (Pages 9-11, Sections 4.3 and 4.4: Bank group processing units can perform project and join operations. Bank processing units can perform select, aggregate, and sort operations).
Regarding claim 5, Kim teaches the multilevel PIM of claim 1, wherein the PIM command scheduler supervises a command queue of a plurality of banks included in a bank group installed in the chip in which the PIM command scheduler is installed (Pages 9-11, Fig. 4.1(a-b), Section 4.4: Each bank group comprises of a bank group controller and a plurality of banks, in which the bank group controller consists of a command queue. The PIM command scheduler is on the same die chip as the bank group controller. The bank group controller receives commands from the PIM command scheduler, therefore, the bank group controller is supervised by the PIM command scheduler).
Regarding claim 6, Kim teaches the multilevel PIM of claim 1, wherein the bank group processing unit comprises:
a DA engine configured to perform Project and Join-merge operations (Pages 9-11, Fig. 4.1(b), Section 4.4: Bank group processing unit comprises of a DA engine (mis-labeled as DB Engine in the figure), which performs project and join (which performs a merge, hence a join-merge) operations); and
a bank group controller configured to receive results of the Project and Join-merge operations and to generate a command at a bank group level (Pages 9-11, Fig. 4.1(b), Section 4.4: The results of both project and join operations produce memory requests (i.e., results) to the group command generator. Each bank group processing unit comprises of a bank group command generator to generate commands to be sent to the bank group controller. Therefore, the commands are generated for the bank group level. The bank group controller and the bank group command generator as the bank group controller).
Regarding claim 7, Kim teaches the multilevel PIM of claim 6, wherein the bank group processing unit further comprises a PIM command generator (Pages 9-11, Fig. 4.1(b), Section 4.4: The bank group processing unit comprises of a bank group command generator (indicated as DRAM CMD GEN in Fig. 4.1(b)). The bank group command generator (located within the PIM) as the PIM command generator).
Regarding claim 8, Kim teaches the multilevel PIM of claim 1, wherein the bank processing unit comprises an adder and a multiplier that are used to process the regular operation (Page 9, Fig. 4.1(e), Section 4.3: Bank processing units comprise of a data processing engine, comprising a SIMD unit, which includes a SIMD adder and a SIMD multiplier, which are used to perform regular operations such as select, aggregate, and sort).
Regarding claim 9, Kim teaches the multilevel PIM of claim 8, wherein the bank processing unit further comprises an object identifier (OID) processing engine configured to perform permutation on result data of the regular operation and an address to which a tag has been designated (Pages 9-10, Fig. 4.1(c-d), Section 4.3: Bank processing units comprise of an object-ID processing engine, which comprise of permutation units. The permutation units can be used to perform permutation on OIDs and may also perform permutation of result data received from the SIMD units performing a regular operation (See Fig. 4.1(c) where the DPE result, which comes from the SIMD units, is entered into a Mux/Demux unit, which receives results from the data processing unit and the object-id processing engine as inputs)).
Regarding claim 10, Kim teaches the multilevel PIM of claim 1, wherein the chip transmits and receives an instruction of the PIM command scheduler through a plurality of data pins (Pages 8-11, Figs. 4.1(a-b), Sections 4.1 and 4.4: The PIM command scheduler of a die receives and schedules PIM instructions to bank group controllers. Instruction transmission is achieved by using data pins).
Regarding claim 11, Kim teaches the multilevel PIM of claim 10, wherein the instruction is composed of instruction segments that are arranged in an interleaving manner (Page 8, Section 4.1: 8 sequential PIM commands are interleaved within a single PIM instruction. The PIM commands as the instruction segments).
Regarding claim 12, Kim teaches the multilevel PIM of claim 11, wherein a transmission cycle of the arrangement of the commands is determined by a burst length (Page 8, Section 4.1: The minimum latency that can occur between write commands is T_ccds, which indicates that the transmission cycle of an arrangement of the commands (i.e., the PIM commands) is 64 commands per cycle. T_ccds as the minimum latency length between write commands in which the PIM may provide a burst of commands (i.e., a burst length)).
Regarding claim 13, Kim teaches the multilevel PIM of claim 10, wherein the instruction comprises any one of activation, precharge, read, and write operations for the chip (Page 8, Section 4.1: PIM instructions include BGPU setup and start the join and project units, which could be considered an activation operation for a die).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (“DRAM based processing-in-memory architecture for data analytics”, see IDS filed 07/31/2023) in view of Resnick (US 20090150624 A1).
Regarding claim 4, Kim teaches the multilevel PIM of claim 1
Kim does not teach that the rank buffer reads data stored in a bank of a first chip, among the plurality of chips, in response to a data read command received from the memory controller, stores the data, and transmits the data to a second chip in response to a write command received from the memory controller.
Note that Kim indicates that the rank buffer is to perform inter-bank data communication within the same rank, but does not explicitly indicate that it’s done using read or write commands from the memory controller (see Page 9, first continuing paragraph).
Resnick teaches to read data stored in a bank of a first chip, among the plurality of chips, in response to a data read command received from the memory controller (Figs. 1-2 and 4, [0023, 0032-0033, 0061-0062]: A read operation initiates a read command, which indicates that data is to be read from a bank (from memory 292, indicated as banks) located in a memory card 290 (i.e., a chip). The read command is sent by the memory controller 100 through memory data bus 175), stores the data (Figs. 2 and 4, [0063]: A read buffer 154 stores returned read data), and transmits the data to a second chip in response to a write command received from the memory controller (Figs. 2 and 5, [0032-0033, 0070-0073]: In response to a read-modify-write operation, if data is already stored in a data buffer, such as read buffer 154, the data is read from the buffer, modifies the data, and sends the modified data to a memory card 290 (which does not necessarily indicate the same memory card that performed the read operation) via a write command. The write command is sent by the memory controller 100 through memory data bus 175).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Kim with the teachings of Resnick to have rank buffer store data read from a chip in response to a read command, and transmit the written data to another chip in response to a write command. One of ordinary skill would recognize that by having data stored in a buffer after read operations and a write operation (such as a read-modify-write operation) requires that read data, rather than re-fetching the data, the rank buffer can instead provide the read data, perform any necessary modifications, and writeback to the other chip. This process avoids the burdensome process of having to activate and wait for the bank to activate, which improves processing performance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 12175587 B2: Shin et al. teaches a graphic processing unit comprising of a memory controller connected a plurality of DIMM chips
US 20230130969 A1: Dutu et al. teaches a system which allows data to be moved between different memories.
US 20240354278 A1: Kim et al. teaches a PIM which performs join operations.
Database Processing-in-Memory: An Experimental Study: Kepe et al. teaches a PIM used alongside a processor for database query processing.
Processing-in-Memory for Databases: Query Processing and Data Transfer: Baumstark et al. discusses the uses of PIMs in database query processing.
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/E.A./Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183