DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claims 1, 9, and 19 have been amended to include “write the plurality of sets of performance settings to the cache during a boot sequence of the device” or “storing, in a processor cache during a boot sequence, a plurality of sets of performance settings”. These limitations are not supported by the specification as originally filed.
Paragraphs 0028-0029 and 0039-0040 do not provide support as argued. Paragraph 0028 discusses tuning settings during boot. Paragraph 0028 also discusses that the settings are stored in registers 222, but the only temporal limitation there is that the settings are stored when transitioning to a new memory state. Paragraph 0028 is silent as to where the settings are stored from the time they are tuned during boot to the time they are read from the registers when transitioning to a new memory state. It is not inherent that paragraph 0028 teaches storing the settings in the register at boot, since the settings could be stored in a SPI flash from the tuning at boot until just before the memory is transitioned to a new memory state. Paragraph 0040 teaches that firmware stored data in system SRAM but is silent as to when that occurs. It is not inherent that paragraph 0040 teaches this limitation since the firmware could be the system management mode firmware that is called as a result of a system management interrupt during normal operation.
The specification discloses the boot sequence in paragraphs 0009, 0013, 0024, and 0028. Paragraphs 0009, 0013, and 0024 do not discuss writing or storing the performance settings. Therefore, these limitations are not supported by the specification as originally filed. Claims 2-8, 10-18, and 20 are rejected based on their dependance from claims 1, 9, or 20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 9-11, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Henderson et al. (US 2013/0262791) in view of Paul et al. (US 2022/0206850) and Chien et al. (US 2023/0215475).
In regards to claim 1, Henderson teaches a device comprising:
a plurality of sets of performance settings for memory, each set corresponding to a memory performance state operating at a memory frequency (“In an embodiment, the memory system includes a memory controller that performs initial calibration for a plurality of operating frequencies during boot or power up of the memory system. Values from the initial calibration are then stored and the system begins operating at a first or nominal frequency.”, paragraph 0014);
a plurality of registers of the memory configured to store a current set of performance settings for a current memory performance state of the memory operating at a current memory frequency (“In block 206, commands program or write mode registers (MRs) on the memory device 104 to alter frequency-dependent memory device settings to support the new operating frequency.”, paragraph 0019); and
a control circuit (memory controller 102, figure 2) configured to:
detect a change in workload associated with the memory transitioning from the current memory performance state at the current memory frequency to a new memory performance state at a new memory frequency (“Accordingly, the user experience and performance are improved by providing a dynamic process for changing memory device frequency between supported frequencies, where the frequency may be adjusted to conserve power during periods of reduced activity.”, paragraph 0023; “Therefore, the memory device 104 is in a state that allows a frequency change and provides that the memory bus 106 will experience no interruptions during the procedure. In block 204, the frequency is adjusted to one of a plurality of operating frequencies.”, paragraph 0018);
read, in response to the detecting, a new set of performance settings corresponding to the new memory performance state (“In block 204, the frequency is adjusted to one of a plurality of operating frequencies. As discussed below, an initial calibration is performed at each of the plurality of operating frequencies during boot to provide calibration values that are used by the memory system 100 during frequency change operations. In block 206, commands program or write mode registers (MRs) on the memory device 104 to alter frequency-dependent memory device settings to support the new operating frequency.”, paragraphs 0018-0019); and
write, to the plurality of registers, the new set of performance settings (“In block 206, commands program or write mode registers (MRs) on the memory device 104 to alter frequency-dependent memory device settings to support the new operating frequency.”, paragraph 0019).
Henderson fails to teach a cache of a processor configured to store the plurality of sets of performance settings for memory;
write the plurality of sets of performance settings to the cache during a boot sequence of the device; and
read, from the cache, a new set of performance settings.
Paul teaches a cache of a processor configured to store the plurality of sets of performance settings for memory (“In this example, memory 112, such as cache memory, register memory or any other suitable memory provides memory performance state tables 114 for the power management logic 108 to control clock frequency and voltage settings for the non-compute units 104.”, paragraph 0047);
write the plurality of sets of performance settings to the cache (“In certain implementations the memory performance state tables 114 are stored in memory and accessible by the power management logic.”, paragraph 0047); and
read, from the cache, a new set of performance settings (“The power management logic 302 adjusts the power level by accessing the memory performance state table 700.”, paragraph 0079)
in order to reduce latency (paragraph 0084).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Henderson with Paul to include a cache of a processor configured to store a plurality of sets of performance settings for memory;
write the plurality of sets of performance settings to the cache; and
read, from the cache, a new set of performance settings
in order to reduce latency (id.).
Henderson in view of Paul fails to teach write the plurality of sets of performance settings during a boot sequence of the device. Chien teaches write the plurality of sets of performance settings during a boot sequence of the device (“In step S230, when the BIOS 131 receives the selection request corresponding to the first overclocking option, the BIOS 131 reads the multiple first memory setting parameters corresponding to the first XMP 131a_1.”, paragraph 0024) such that “the user can achieve overclocking of the memory module through the UI in a fast and convenient way” (paragraph 0008). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Henderson with Paul and Chien to include write the plurality of sets of performance settings during a boot sequence of the device such that “the user can achieve overclocking of the memory module through the UI in a fast and convenient way” (id.).
In regards to claim 9, Henderson teaches a system comprising:
a memory configured to operate at one of a plurality of memory performance states, each corresponding to a memory frequency (“In an embodiment, the memory system includes a memory controller that performs initial calibration for a plurality of operating frequencies during boot or power up of the memory system. Values from the initial calibration are then stored and the system begins operating at a first or nominal frequency.”, paragraph 0014);
a plurality of registers of the memory configured to store a current set of performance settings for a current memory performance state of the memory operating at a current memory frequency (“In block 206, commands program or write mode registers (MRs) on the memory device 104 to alter frequency-dependent memory device settings to support the new operating frequency.”, paragraph 0019);
a plurality of sets of performance settings for the memory, each set corresponding to settings for mitigating signal degradation at respective memory frequencies for one of the plurality of memory performance states (“In an embodiment, the memory system includes a memory controller that performs initial calibration for a plurality of operating frequencies during boot or power up of the memory system. Values from the initial calibration are then stored and the system begins operating at a first or nominal frequency.”, paragraph 0014; “In an embodiment, the memory buses 106 transmit clock, data, commands, and a data strobe between the memory controller 102 and the memory devices 104, wherein calibration of timing for one or more of these signals improve timing and communication accuracy for the memory system.”, paragraph 0015); and
a control circuit (memory controller 102, figure 2) configured to:
detect a change in workload associated with a new memory performance state for the memory to operate at a new memory frequency (“Accordingly, the user experience and performance are improved by providing a dynamic process for changing memory device frequency between supported frequencies, where the frequency may be adjusted to conserve power during periods of reduced activity.”, paragraph 0023);
initiate, in response to the detecting, a transition sequence of the memory from the current memory frequency of the current memory performance state to the new memory frequency for the new memory performance state (“Therefore, the memory device 104 is in a state that allows a frequency change and provides that the memory bus 106 will experience no interruptions during the procedure. In block 204, the frequency is adjusted to one of a plurality of operating frequencies.”, paragraph 0018);
read, in response to initiating the transition sequence, a new set of performance settings corresponding to the new memory performance state (“In block 204, the frequency is adjusted to one of a plurality of operating frequencies. As discussed below, an initial calibration is performed at each of the plurality of operating frequencies during boot to provide calibration values that are used by the memory system 100 during frequency change operations. In block 206, commands program or write mode registers (MRs) on the memory device 104 to alter frequency-dependent memory device settings to support the new operating frequency.”, paragraphs 0018-0019); and
write, to the plurality of registers, the new set of performance settings to replace the current set of performance settings (“In block 206, commands program or write mode registers (MRs) on the memory device 104 to alter frequency-dependent memory device settings to support the new operating frequency.”, paragraph 0019).
Henderson fails to teach a processor including a cache configured to store the plurality of sets of performance settings for the memory;
write the plurality of sets of performance settings to the cache during a boot sequence of the device; and
read, from the cache, the new set of performance settings.
Paul teaches a processor including a cache (“FIG. 1 illustrates an example of an integrated circuit 100 such as a system on-chip or any other suitable integrated circuit, that includes a plurality of compute units 102 that each process data and access memory, such as cache memory, shared memory such as volatile or non-volatile memory or any suitable memory.”, paragraph 0046) configured to store the plurality of sets of performance settings for the memory (“In this example, memory 112, such as cache memory, register memory or any other suitable memory provides memory performance state tables 114 for the power management logic 108 to control clock frequency and voltage settings for the non-compute units 104.”, paragraph 0047);
write the plurality of sets of performance settings to the cache (“In certain implementations the memory performance state tables 114 are stored in memory and accessible by the power management logic.”, paragraph 0047); and
read, from the cache, the new set of performance settings (“The power management logic 302 adjusts the power level by accessing the memory performance state table 700.”, paragraph 0079)
in order to reduce latency (paragraph 0084).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Henderson with Paul to include a processor including a cache configured to store the plurality of sets of performance settings for the memory;
write the plurality of sets of performance settings to the cache; and
read, from the cache, the new set of performance settings
in order to reduce latency (id.).
Henderson in view of Paul fails to teach write the plurality of sets of performance settings during a boot sequence of the device. Chien teaches write the plurality of sets of performance settings during a boot sequence of the device (“In step S230, when the BIOS 131 receives the selection request corresponding to the first overclocking option, the BIOS 131 reads the multiple first memory setting parameters corresponding to the first XMP 131a_1.”, paragraph 0024) such that “the user can achieve overclocking of the memory module through the UI in a fast and convenient way” (paragraph 0008). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Henderson with Paul and Chien to include write the plurality of sets of performance settings during a boot sequence of the device such that “the user can achieve overclocking of the memory module through the UI in a fast and convenient way” (id.).
In regards to claim 19, Henderson teaches a method comprising:
storing a plurality of sets of performance settings for a memory, each set corresponding to settings for mitigating signal degradation at a respective memory frequency for a plurality of memory performance states for the memory (“In an embodiment, the memory system includes a memory controller that performs initial calibration for a plurality of operating frequencies during boot or power up of the memory system. Values from the initial calibration are then stored and the system begins operating at a first or nominal frequency.”, paragraph 0014; “In an embodiment, the memory buses 106 transmit clock, data, commands, and a data strobe between the memory controller 102 and the memory devices 104, wherein calibration of timing for one or more of these signals improve timing and communication accuracy for the memory system.”, paragraph 0015);
storing, in a plurality of memory channel registers of the memory and from the plurality of sets of performance settings, a current set of performance settings for the memory for a current memory performance state for the memory to operate at a current memory frequency (“In block 206, commands program or write mode registers (MRs) on the memory device 104 to alter frequency-dependent memory device settings to support the new operating frequency.”, paragraph 0019);
detecting a change in workload associated with a new memory frequency for the memory frequency (“Accordingly, the user experience and performance are improved by providing a dynamic process for changing memory device frequency between supported frequencies, where the frequency may be adjusted to conserve power during periods of reduced activity.”, paragraph 0023);
initiating, in response to the detected change in workload, a transition sequence of the memory from the current memory performance state operating the current memory frequency to a new memory performance state for the new memory frequency (“Therefore, the memory device 104 is in a state that allows a frequency change and provides that the memory bus 106 will experience no interruptions during the procedure. In block 204, the frequency is adjusted to one of a plurality of operating frequencies.”, paragraph 0018);
reading a new set of performance settings corresponding to the new memory performance state (“In block 204, the frequency is adjusted to one of a plurality of operating frequencies. As discussed below, an initial calibration is performed at each of the plurality of operating frequencies during boot to provide calibration values that are used by the memory system 100 during frequency change operations. In block 206, commands program or write mode registers (MRs) on the memory device 104 to alter frequency-dependent memory device settings to support the new operating frequency.”, paragraphs 0018-0019); and
writing, to the plurality of memory channel registers of the memory, the new set of performance settings to replace the current set of performance settings (“In block 206, commands program or write mode registers (MRs) on the memory device 104 to alter frequency-dependent memory device settings to support the new operating frequency.”, paragraph 0019).
Henderson fails to teach storing, in a processor cache during a boot sequence, the plurality of sets of performance settings; and
reading, from the processor cache, a new set of performance settings.
Paul teaches storing, in a processor cache, the plurality of sets of performance settings (“In this example, memory 112, such as cache memory, register memory or any other suitable memory provides memory performance state tables 114 for the power management logic 108 to control clock frequency and voltage settings for the non-compute units 104.”, paragraph 0047; “FIG. 1 illustrates an example of an integrated circuit 100 such as a system on-chip or any other suitable integrated circuit, that includes a plurality of compute units 102 that each process data and access memory, such as cache memory, shared memory such as volatile or non-volatile memory or any suitable memory.”, paragraph 0046); and
reading, from the processor cache, a new set of performance settings (“The power management logic 302 adjusts the power level by accessing the memory performance state table 700.”, paragraph 0079)
in order to reduce latency (paragraph 0084).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Henderson with Paul to include storing, in a processor cache, the plurality of sets of performance settings; and
reading, from a processor cache, a new set of performance settings
in order to reduce latency (id.).
Henderson in view of Paul fails to teach storing, during a boot sequence, the plurality of sets of performance settings. Chien teaches storing, during a boot sequence, the plurality of sets of performance settings (“In the embodiment, the BIOS 131 stores at least one extreme memory profile (XMP), such as the first XMP 131a_1 and the second XMP 131a_2.”, paragraph 0017; “In the embodiment, the data items displayed in the selection list in the window 331e are memory setting parameters. In the embodiment, the respective memory setting parameters represented by the second column to the rightmost column of the selection list include the memory operating frequency of the memory module 110”, paragraph 0032; See also figure 3) such that “the user can achieve overclocking of the memory module through the UI in a fast and convenient way” (paragraph 0008). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Henderson with Paul and Chien to include storing, during a boot sequence, the plurality of sets of performance settings such that “the user can achieve overclocking of the memory module through the UI in a fast and convenient way” (id.).
In regards to claims 2 and 10, Henderson and Paul teach that each of the plurality of sets of performance settings includes frequency-dependent settings (“In an embodiment, the memory system includes a memory controller that performs initial calibration for a plurality of operating frequencies during boot or power up of the memory system. Values from the initial calibration are then stored and the system begins operating at a first or nominal frequency.”, Henderson, paragraph 0014; “The memory performance state table 700 includes a plurality of memory performance states (P0-P3) wherein each state includes data representing an allowable memory data transfer speed for the performance state (e.g., 3200 MT/sec, 1600 MT/sec), a non-compute memory system voltage setting (e.g., uncore voltage used for data fabric, memory controller and PHY), a data fabric clock frequency setting (FCLK) a memory clock frequency setting (MEMCLK) and a memory controller (UCLK) setting.”, Paul, paragraph 0079).
In regards to claims 3 and 11, Paul further teaches the frequency-dependent settings correspond to at least one of:
noise compensation settings;
voltage settings (“The memory performance state table 700 includes a plurality of memory performance states (P0-P3) wherein each state includes data representing an allowable memory data transfer speed for the performance state (e.g., 3200 MT/sec, 1600 MT/sec), a non-compute memory system voltage setting (e.g., uncore voltage used for data fabric, memory controller and PHY), a data fabric clock frequency setting (FCLK) a memory clock frequency setting (MEMCLK) and a memory controller (UCLK) setting.”, Paul, paragraph 0079); or
timing settings (id.).
In regards to claim 14, Henderson further teaches that the control circuit is configured to initiate the transition sequence in response to a power management decision (“Accordingly, the user experience and performance are improved by providing a dynamic process for changing memory device frequency between supported frequencies, where the frequency may be adjusted to conserve power during periods of reduced activity.”, paragraph 0023).
Claims 4, 12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Henderson et al. (US 2013/0262791) in view of Paul et al. (US 2022/0206850), Chien et al. (US 2023/0215475), and Mutnury et al. (US 2019/0227885).
In regards to claims 4 and 12, Henderson in view of Paul and Chien teaches claims 3 and 11. Henderson in view of Paul and Chien fails to teach that the noise compensation settings are tuned during a boot sequence of the device. Mutnury teaches that the noise compensation settings are tuned during a boot sequence of the device (“Mode registers 134 include various ODT value settings 135, and an ODT mode setting 136. … In some instances, the settings of mode registers 134 are configured at boot time for information handling system 100”, paragraph 0022) in order to achieve “an impedance level that matches the impedance of the transmission lines associated with the circuit trace” (paragraph 0021). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Henderson with Paul, Chien, and Mutnury such that the noise compensation settings are tuned during a boot sequence of the device ) in order to achieve “an impedance level that matches the impedance of the transmission lines associated with the circuit trace” (id.).
In regards to claim 15, Henderson in view of Paul and Chien teaches claim 9. Henderson in view of Paul and Chien fails to teach that the plurality of registers corresponds to memory channel registers. Mutnury teaches that the plurality of registers corresponds to memory channel registers (“For example, memory controller 112 and DIMM 120 may operate in accordance with a Double-Data Rate (DDR) standard, such as a JEDEC DDR4 or DDR5 standard. It will be understood that, where memory controller 112 and DIMM 120 operate in accordance with the DDR5 standard, then the memory controller will be configured to provide two channels to the one or more DIMM, and that DIMM 120 will include functions and features appropriate to the implementation of the dual-channel architecture of the DDR5 standard.”, paragraph 0014). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Henderson with Paul, Chien, and Mutnury such that the plurality of registers corresponds to memory channel registers in order to increase memory efficiency.
Claims 5, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Henderson et al. (US 2013/0262791) in view of Paul et al. (US 2022/0206850), Chien et al. (US 2023/0215475), and Ito et al. (US 2004/0221098).
In regards to claims 5, 13, and 20, Henderson in view of Paul and Chien teaches claims 1, 9, and 19. Henderson in view of Paul and Chien fails to teach that a transition sequence for transitioning from the current memory performance state to the new memory performance state includes a self-refresh operation and the control circuit is configured to write the new set of performance settings to the plurality of registers before the self-refresh operation initiates. Ito teaches that a transition sequence for transitioning from the current memory performance state to the new memory performance state includes a self-refresh operation and the control circuit is configured to write the new set of performance settings to the plurality of registers before the self-refresh operation initiates (“The entry/exit command may be same as the self-refresh command. In this case, the meaning of the command may be switched between the ‘super self-refresh’ and the normal self-refresh by setting of MRS (Mode Register Set)or EMRS (Extended Mode Register Set).”, paragraph 0044) in order “to minimize current consumption required in a refresh operation of a memory device” (paragraph 0072). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Henderson with Paul, Chien, and Ito such that a transition sequence for transitioning from the current memory performance state to the new memory performance state includes a self-refresh operation and the control circuit is configured to write the new set of performance settings to the plurality of registers before the self-refresh operation initiates in order “to minimize current consumption required in a refresh operation of a memory device” (id.).
Claims 6-8 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Henderson et al. (US 2013/0262791) in view of Paul et al. (US 2022/0206850), Chien et al. (US 2023/0215475), and Lee et al. (US 2020/0225859).
In regards to claims 6 and 16, Henderson in view of Paul and Chien teaches claims 1 and 9. Henderson in view of Paul and Chien fails to adequately teach that writing the new set of performance settings comprises selectively writing the new set of performance settings. Lee teaches that writing the new set of performance settings comprises selectively writing the new set of performance settings (“In an embodiment, the change data display (MASK) field may represent a position of data to be changed in a parameter stored in the memory device 100. That is, the memory device 100 may change only the data located at the position represented by the change data display (MASK) field, based on the change data display (MASK) field.”, paragraph 0075) in order “to prevent a storage or change of an unintended parameter” (paragraph 0144). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Henderson with Paul, Chien, and Lee such that writing the new set of performance settings comprises selectively writing the new set of performance settings in order “to prevent a storage or change of an unintended parameter” (id.).
In regards to claims 7 and 17, Lee further teaches that selectively writing the new set of performance settings includes writing updated performance settings to corresponding registers of the plurality of registers for performance settings of the current set of performance settings that require updating for the new set of performance settings (“In an embodiment, the change data display (MASK) field may represent a position of data to be changed in a parameter stored in the memory device 100. That is, the memory device 100 may change only the data located at the position represented by the change data display (MASK) field, based on the change data display (MASK) field.”, paragraph 0075).
In regards to claims 8 and 18, Lee further teaches that selectively writing the new set of performance settings further comprises maintaining registers of the plurality of registers corresponding to performance settings that are not updated (“In an embodiment, the change data display (MASK) field may represent a position of data to be changed in a parameter stored in the memory device 100. That is, the memory device 100 may change only the data located at the position represented by the change data display (MASK) field, based on the change data display (MASK) field.”, paragraph 0075).
Response to Arguments
Applicants’ arguments, see section I, filed 14 July 2026, with respect to the indefinite rejection have been fully considered and are persuasive. The 112(b) rejection of claims 19 and 20 has been withdrawn.
Applicants’ arguments with respect to the prior art rejections have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicants’ amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 25 August 2026
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